1 /* $OpenBSD: if_athn_cardbus.c,v 1.19 2024/05/24 06:26:47 jsg Exp $ */
2
3 /*-
4 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19 /*
20 * CardBus front-end for Atheros 802.11a/g/n chipsets.
21 */
22
23 #include "bpfilter.h"
24
25 #include <sys/param.h>
26 #include <sys/systm.h>
27 #include <sys/timeout.h>
28 #include <sys/device.h>
29
30 #include <machine/bus.h>
31 #include <machine/intr.h>
32
33 #include <net/if.h>
34 #include <net/if_media.h>
35
36 #include <netinet/in.h>
37 #include <netinet/if_ether.h>
38
39 #include <net80211/ieee80211_var.h>
40 #include <net80211/ieee80211_amrr.h>
41 #include <net80211/ieee80211_ra.h>
42 #include <net80211/ieee80211_radiotap.h>
43
44 #include <dev/ic/athnreg.h>
45 #include <dev/ic/athnvar.h>
46
47 #include <dev/pci/pcireg.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pcidevs.h>
50
51 #include <dev/cardbus/cardbusvar.h>
52
53 struct athn_cardbus_softc {
54 struct athn_softc sc_sc;
55
56 /* CardBus specific goo. */
57 cardbus_devfunc_t sc_ct;
58 pcitag_t sc_tag;
59 void *sc_ih;
60 bus_space_tag_t sc_st;
61 bus_space_handle_t sc_sh;
62 bus_size_t sc_mapsize;
63 pcireg_t sc_bar_val;
64 int sc_intrline;
65 pci_chipset_tag_t sc_pc;
66 };
67
68 int athn_cardbus_match(struct device *, void *, void *);
69 void athn_cardbus_attach(struct device *, struct device *, void *);
70 int athn_cardbus_detach(struct device *, int);
71 int athn_cardbus_enable(struct athn_softc *);
72 void athn_cardbus_disable(struct athn_softc *);
73 void athn_cardbus_power(struct athn_softc *, int);
74 void athn_cardbus_setup(struct athn_cardbus_softc *);
75 uint32_t athn_cardbus_read(struct athn_softc *, uint32_t);
76 void athn_cardbus_write(struct athn_softc *, uint32_t, uint32_t);
77 void athn_cardbus_write_barrier(struct athn_softc *);
78
79 const struct cfattach athn_cardbus_ca = {
80 sizeof (struct athn_cardbus_softc),
81 athn_cardbus_match,
82 athn_cardbus_attach,
83 athn_cardbus_detach
84 };
85
86 static const struct pci_matchid athn_cardbus_devices[] = {
87 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5416 },
88 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5418 },
89 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9160 },
90 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9280 },
91 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR928X },
92 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9285 },
93 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR2427 },
94 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9227 },
95 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9287 },
96 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9300 }
97 };
98
99 int
athn_cardbus_match(struct device * parent,void * match,void * aux)100 athn_cardbus_match(struct device *parent, void *match, void *aux)
101 {
102 return (cardbus_matchbyid(aux, athn_cardbus_devices,
103 nitems(athn_cardbus_devices)));
104 }
105
106 void
athn_cardbus_attach(struct device * parent,struct device * self,void * aux)107 athn_cardbus_attach(struct device *parent, struct device *self, void *aux)
108 {
109 struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)self;
110 struct athn_softc *sc = &csc->sc_sc;
111 struct cardbus_attach_args *ca = aux;
112 cardbus_devfunc_t ct = ca->ca_ct;
113 bus_addr_t base;
114 int error;
115
116 sc->sc_dmat = ca->ca_dmat;
117 csc->sc_ct = ct;
118 csc->sc_tag = ca->ca_tag;
119 csc->sc_intrline = ca->ca_intrline;
120 csc->sc_pc = ca->ca_pc;
121
122 /* Power management hooks. */
123 sc->sc_enable = athn_cardbus_enable;
124 sc->sc_disable = athn_cardbus_disable;
125 sc->sc_power = athn_cardbus_power;
126
127 sc->ops.read = athn_cardbus_read;
128 sc->ops.write = athn_cardbus_write;
129 sc->ops.write_barrier = athn_cardbus_write_barrier;
130
131 /* Map control/status registers. */
132 error = Cardbus_mapreg_map(ct, CARDBUS_BASE0_REG,
133 PCI_MAPREG_TYPE_MEM, 0, &csc->sc_st, &csc->sc_sh, &base,
134 &csc->sc_mapsize);
135 if (error != 0) {
136 printf(": can't map mem space\n");
137 return;
138 }
139 csc->sc_bar_val = base | PCI_MAPREG_TYPE_MEM;
140
141 /* Set up the PCI configuration registers. */
142 athn_cardbus_setup(csc);
143
144 printf(": irq %d\n", csc->sc_intrline);
145
146 athn_attach(sc);
147 Cardbus_function_disable(ct);
148 }
149
150 int
athn_cardbus_detach(struct device * self,int flags)151 athn_cardbus_detach(struct device *self, int flags)
152 {
153 struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)self;
154 struct athn_softc *sc = &csc->sc_sc;
155 cardbus_devfunc_t ct = csc->sc_ct;
156 cardbus_chipset_tag_t cc = ct->ct_cc;
157 cardbus_function_tag_t cf = ct->ct_cf;
158
159 athn_detach(sc);
160
161 /* Unhook the interrupt handler. */
162 if (csc->sc_ih != NULL)
163 cardbus_intr_disestablish(cc, cf, csc->sc_ih);
164
165 /* Release bus space and close window. */
166 Cardbus_mapreg_unmap(ct, CARDBUS_BASE0_REG, csc->sc_st, csc->sc_sh,
167 csc->sc_mapsize);
168
169 return (0);
170 }
171
172 int
athn_cardbus_enable(struct athn_softc * sc)173 athn_cardbus_enable(struct athn_softc *sc)
174 {
175 struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)sc;
176 cardbus_devfunc_t ct = csc->sc_ct;
177 cardbus_chipset_tag_t cc = ct->ct_cc;
178 cardbus_function_tag_t cf = ct->ct_cf;
179
180 /* Power on the socket. */
181 Cardbus_function_enable(ct);
182
183 /* Setup the PCI configuration registers. */
184 athn_cardbus_setup(csc);
185
186 /* Map and establish the interrupt handler. */
187 csc->sc_ih = cardbus_intr_establish(cc, cf, csc->sc_intrline, IPL_NET,
188 athn_intr, sc, sc->sc_dev.dv_xname);
189 if (csc->sc_ih == NULL) {
190 printf("%s: could not establish interrupt at %d\n",
191 sc->sc_dev.dv_xname, csc->sc_intrline);
192 Cardbus_function_disable(ct);
193 return (1);
194 }
195 return (0);
196 }
197
198 void
athn_cardbus_disable(struct athn_softc * sc)199 athn_cardbus_disable(struct athn_softc *sc)
200 {
201 struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)sc;
202 cardbus_devfunc_t ct = csc->sc_ct;
203 cardbus_chipset_tag_t cc = ct->ct_cc;
204 cardbus_function_tag_t cf = ct->ct_cf;
205
206 /* Unhook the interrupt handler. */
207 cardbus_intr_disestablish(cc, cf, csc->sc_ih);
208 csc->sc_ih = NULL;
209
210 /* Power down the socket. */
211 Cardbus_function_disable(ct);
212 }
213
214 void
athn_cardbus_power(struct athn_softc * sc,int why)215 athn_cardbus_power(struct athn_softc *sc, int why)
216 {
217 struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)sc;
218
219 if (why == DVACT_RESUME) {
220 /* Restore the PCI configuration registers. */
221 athn_cardbus_setup(csc);
222 }
223 }
224
225 void
athn_cardbus_setup(struct athn_cardbus_softc * csc)226 athn_cardbus_setup(struct athn_cardbus_softc *csc)
227 {
228 cardbus_devfunc_t ct = csc->sc_ct;
229 cardbus_chipset_tag_t cc = ct->ct_cc;
230 pci_chipset_tag_t pc = csc->sc_pc;
231 cardbus_function_tag_t cf = ct->ct_cf;
232 pcireg_t reg;
233
234 /* Program the BAR. */
235 pci_conf_write(pc, csc->sc_tag, CARDBUS_BASE0_REG,
236 csc->sc_bar_val);
237
238 /* Make sure the right access type is on the cardbus bridge. */
239 (*cf->cardbus_ctrl)(cc, CARDBUS_MEM_ENABLE);
240 (*cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE);
241
242 /* Enable the appropriate bits in the PCI CSR. */
243 reg = pci_conf_read(pc, csc->sc_tag,
244 PCI_COMMAND_STATUS_REG);
245 reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
246 pci_conf_write(pc, csc->sc_tag, PCI_COMMAND_STATUS_REG,
247 reg);
248
249 /*
250 * Noone knows why this shit is necessary but there are claims that
251 * not doing this may cause very frequent PCI FATAL interrupts from
252 * the card: http://bugzilla.kernel.org/show_bug.cgi?id=13483
253 */
254 reg = pci_conf_read(pc, csc->sc_tag, 0x40);
255 if (reg & 0xff00)
256 pci_conf_write(pc, csc->sc_tag, 0x40, reg & ~0xff00);
257
258 /* Change latency timer; default value yields poor results. */
259 reg = pci_conf_read(pc, csc->sc_tag, PCI_BHLC_REG);
260 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
261 reg |= 168 << PCI_LATTIMER_SHIFT;
262 pci_conf_write(pc, csc->sc_tag, PCI_BHLC_REG, reg);
263 }
264
265 uint32_t
athn_cardbus_read(struct athn_softc * sc,uint32_t addr)266 athn_cardbus_read(struct athn_softc *sc, uint32_t addr)
267 {
268 struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)sc;
269
270 return (bus_space_read_4(csc->sc_st, csc->sc_sh, addr));
271 }
272
273 void
athn_cardbus_write(struct athn_softc * sc,uint32_t addr,uint32_t val)274 athn_cardbus_write(struct athn_softc *sc, uint32_t addr, uint32_t val)
275 {
276 struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)sc;
277
278 bus_space_write_4(csc->sc_st, csc->sc_sh, addr, val);
279 }
280
281 void
athn_cardbus_write_barrier(struct athn_softc * sc)282 athn_cardbus_write_barrier(struct athn_softc *sc)
283 {
284 struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)sc;
285
286 bus_space_barrier(csc->sc_st, csc->sc_sh, 0, csc->sc_mapsize,
287 BUS_SPACE_BARRIER_WRITE);
288 }
289