1 /* $OpenBSD: if_athn_cardbus.c,v 1.14 2015/11/24 17:11:39 mpi Exp $ */ 2 3 /*- 4 * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * CardBus front-end for Atheros 802.11a/g/n chipsets. 21 */ 22 23 #include "bpfilter.h" 24 25 #include <sys/param.h> 26 #include <sys/sockio.h> 27 #include <sys/mbuf.h> 28 #include <sys/kernel.h> 29 #include <sys/socket.h> 30 #include <sys/systm.h> 31 #include <sys/malloc.h> 32 #include <sys/timeout.h> 33 #include <sys/device.h> 34 35 #include <machine/bus.h> 36 #include <machine/intr.h> 37 38 #include <net/if.h> 39 #include <net/if_media.h> 40 41 #include <netinet/in.h> 42 #include <netinet/if_ether.h> 43 44 #include <net80211/ieee80211_var.h> 45 #include <net80211/ieee80211_amrr.h> 46 #include <net80211/ieee80211_radiotap.h> 47 48 #include <dev/ic/athnreg.h> 49 #include <dev/ic/athnvar.h> 50 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pcidevs.h> 54 55 #include <dev/cardbus/cardbusvar.h> 56 57 struct athn_cardbus_softc { 58 struct athn_softc sc_sc; 59 60 /* CardBus specific goo. */ 61 cardbus_devfunc_t sc_ct; 62 pcitag_t sc_tag; 63 void *sc_ih; 64 bus_space_tag_t sc_st; 65 bus_space_handle_t sc_sh; 66 bus_size_t sc_mapsize; 67 pcireg_t sc_bar_val; 68 int sc_intrline; 69 pci_chipset_tag_t sc_pc; 70 }; 71 72 int athn_cardbus_match(struct device *, void *, void *); 73 void athn_cardbus_attach(struct device *, struct device *, void *); 74 int athn_cardbus_detach(struct device *, int); 75 int athn_cardbus_enable(struct athn_softc *); 76 void athn_cardbus_disable(struct athn_softc *); 77 void athn_cardbus_power(struct athn_softc *, int); 78 void athn_cardbus_setup(struct athn_cardbus_softc *); 79 uint32_t athn_cardbus_read(struct athn_softc *, uint32_t); 80 void athn_cardbus_write(struct athn_softc *, uint32_t, uint32_t); 81 void athn_cardbus_write_barrier(struct athn_softc *); 82 83 struct cfattach athn_cardbus_ca = { 84 sizeof (struct athn_cardbus_softc), 85 athn_cardbus_match, 86 athn_cardbus_attach, 87 athn_cardbus_detach 88 }; 89 90 static const struct pci_matchid athn_cardbus_devices[] = { 91 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5416 }, 92 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR5418 }, 93 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9160 }, 94 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9280 }, 95 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9281 }, 96 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9285 }, 97 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR2427 }, 98 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9227 }, 99 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9287 }, 100 { PCI_VENDOR_ATHEROS, PCI_PRODUCT_ATHEROS_AR9300 } 101 }; 102 103 int 104 athn_cardbus_match(struct device *parent, void *match, void *aux) 105 { 106 return (cardbus_matchbyid(aux, athn_cardbus_devices, 107 nitems(athn_cardbus_devices))); 108 } 109 110 void 111 athn_cardbus_attach(struct device *parent, struct device *self, void *aux) 112 { 113 struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)self; 114 struct athn_softc *sc = &csc->sc_sc; 115 struct cardbus_attach_args *ca = aux; 116 cardbus_devfunc_t ct = ca->ca_ct; 117 bus_addr_t base; 118 int error; 119 120 sc->sc_dmat = ca->ca_dmat; 121 csc->sc_ct = ct; 122 csc->sc_tag = ca->ca_tag; 123 csc->sc_intrline = ca->ca_intrline; 124 csc->sc_pc = ca->ca_pc; 125 126 /* Power management hooks. */ 127 sc->sc_enable = athn_cardbus_enable; 128 sc->sc_disable = athn_cardbus_disable; 129 sc->sc_power = athn_cardbus_power; 130 131 sc->ops.read = athn_cardbus_read; 132 sc->ops.write = athn_cardbus_write; 133 sc->ops.write_barrier = athn_cardbus_write_barrier; 134 135 /* Map control/status registers. */ 136 error = Cardbus_mapreg_map(ct, CARDBUS_BASE0_REG, 137 PCI_MAPREG_TYPE_MEM, 0, &csc->sc_st, &csc->sc_sh, &base, 138 &csc->sc_mapsize); 139 if (error != 0) { 140 printf(": can't map mem space\n"); 141 return; 142 } 143 csc->sc_bar_val = base | PCI_MAPREG_TYPE_MEM; 144 145 /* Set up the PCI configuration registers. */ 146 athn_cardbus_setup(csc); 147 148 printf(": irq %d\n", csc->sc_intrline); 149 150 athn_attach(sc); 151 Cardbus_function_disable(ct); 152 } 153 154 int 155 athn_cardbus_detach(struct device *self, int flags) 156 { 157 struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)self; 158 struct athn_softc *sc = &csc->sc_sc; 159 cardbus_devfunc_t ct = csc->sc_ct; 160 cardbus_chipset_tag_t cc = ct->ct_cc; 161 cardbus_function_tag_t cf = ct->ct_cf; 162 163 athn_detach(sc); 164 165 /* Unhook the interrupt handler. */ 166 if (csc->sc_ih != NULL) 167 cardbus_intr_disestablish(cc, cf, csc->sc_ih); 168 169 /* Release bus space and close window. */ 170 Cardbus_mapreg_unmap(ct, CARDBUS_BASE0_REG, csc->sc_st, csc->sc_sh, 171 csc->sc_mapsize); 172 173 return (0); 174 } 175 176 int 177 athn_cardbus_enable(struct athn_softc *sc) 178 { 179 struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)sc; 180 cardbus_devfunc_t ct = csc->sc_ct; 181 cardbus_chipset_tag_t cc = ct->ct_cc; 182 cardbus_function_tag_t cf = ct->ct_cf; 183 184 /* Power on the socket. */ 185 Cardbus_function_enable(ct); 186 187 /* Setup the PCI configuration registers. */ 188 athn_cardbus_setup(csc); 189 190 /* Map and establish the interrupt handler. */ 191 csc->sc_ih = cardbus_intr_establish(cc, cf, csc->sc_intrline, IPL_NET, 192 athn_intr, sc, sc->sc_dev.dv_xname); 193 if (csc->sc_ih == NULL) { 194 printf("%s: could not establish interrupt at %d\n", 195 sc->sc_dev.dv_xname, csc->sc_intrline); 196 Cardbus_function_disable(ct); 197 return (1); 198 } 199 return (0); 200 } 201 202 void 203 athn_cardbus_disable(struct athn_softc *sc) 204 { 205 struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)sc; 206 cardbus_devfunc_t ct = csc->sc_ct; 207 cardbus_chipset_tag_t cc = ct->ct_cc; 208 cardbus_function_tag_t cf = ct->ct_cf; 209 210 /* Unhook the interrupt handler. */ 211 cardbus_intr_disestablish(cc, cf, csc->sc_ih); 212 csc->sc_ih = NULL; 213 214 /* Power down the socket. */ 215 Cardbus_function_disable(ct); 216 } 217 218 void 219 athn_cardbus_power(struct athn_softc *sc, int why) 220 { 221 struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)sc; 222 223 if (why == DVACT_RESUME) { 224 /* Restore the PCI configuration registers. */ 225 athn_cardbus_setup(csc); 226 } 227 } 228 229 void 230 athn_cardbus_setup(struct athn_cardbus_softc *csc) 231 { 232 cardbus_devfunc_t ct = csc->sc_ct; 233 cardbus_chipset_tag_t cc = ct->ct_cc; 234 pci_chipset_tag_t pc = csc->sc_pc; 235 cardbus_function_tag_t cf = ct->ct_cf; 236 pcireg_t reg; 237 238 /* Program the BAR. */ 239 pci_conf_write(pc, csc->sc_tag, CARDBUS_BASE0_REG, 240 csc->sc_bar_val); 241 242 /* Make sure the right access type is on the cardbus bridge. */ 243 (*cf->cardbus_ctrl)(cc, CARDBUS_MEM_ENABLE); 244 (*cf->cardbus_ctrl)(cc, CARDBUS_BM_ENABLE); 245 246 /* Enable the appropriate bits in the PCI CSR. */ 247 reg = pci_conf_read(pc, csc->sc_tag, 248 PCI_COMMAND_STATUS_REG); 249 reg |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE; 250 pci_conf_write(pc, csc->sc_tag, PCI_COMMAND_STATUS_REG, 251 reg); 252 253 /* 254 * Noone knows why this shit is necessary but there are claims that 255 * not doing this may cause very frequent PCI FATAL interrupts from 256 * the card: http://bugzilla.kernel.org/show_bug.cgi?id=13483 257 */ 258 reg = pci_conf_read(pc, csc->sc_tag, 0x40); 259 if (reg & 0xff00) 260 pci_conf_write(pc, csc->sc_tag, 0x40, reg & ~0xff00); 261 262 /* Change latency timer; default value yields poor results. */ 263 reg = pci_conf_read(pc, csc->sc_tag, PCI_BHLC_REG); 264 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT); 265 reg |= 168 << PCI_LATTIMER_SHIFT; 266 pci_conf_write(pc, csc->sc_tag, PCI_BHLC_REG, reg); 267 } 268 269 uint32_t 270 athn_cardbus_read(struct athn_softc *sc, uint32_t addr) 271 { 272 struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)sc; 273 274 return (bus_space_read_4(csc->sc_st, csc->sc_sh, addr)); 275 } 276 277 void 278 athn_cardbus_write(struct athn_softc *sc, uint32_t addr, uint32_t val) 279 { 280 struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)sc; 281 282 bus_space_write_4(csc->sc_st, csc->sc_sh, addr, val); 283 } 284 285 void 286 athn_cardbus_write_barrier(struct athn_softc *sc) 287 { 288 struct athn_cardbus_softc *csc = (struct athn_cardbus_softc *)sc; 289 290 bus_space_barrier(csc->sc_st, csc->sc_sh, 0, csc->sc_mapsize, 291 BUS_SPACE_BARRIER_WRITE); 292 } 293