1 /* $OpenBSD: rkpmic.c,v 1.17 2024/05/26 18:06:21 kettenis Exp $ */
2 /*
3 * Copyright (c) 2017 Mark Kettenis <kettenis@openbsd.org>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18 #include <sys/param.h>
19 #include <sys/systm.h>
20 #include <sys/device.h>
21 #include <sys/malloc.h>
22 #include <sys/proc.h>
23 #include <sys/signalvar.h>
24
25 #include <machine/fdt.h>
26
27 #include <dev/ofw/openfirm.h>
28 #include <dev/ofw/ofw_regulator.h>
29 #include <dev/ofw/fdt.h>
30
31 #include <dev/i2c/i2cvar.h>
32 #include <dev/spi/spivar.h>
33
34 #include <dev/clock_subr.h>
35
36 #define RK80X_SECONDS 0x00
37 #define RK80X_MINUTES 0x01
38 #define RK80X_HOURS 0x02
39 #define RK80X_DAYS 0x03
40 #define RK80X_MONTHS 0x04
41 #define RK80X_YEARS 0x05
42 #define RK80X_WEEKS 0x06
43 #define RK80X_NRTC_REGS 7
44
45 #define RK805_RTC_CTRL 0x10
46 #define RK808_RTC_CTRL 0x10
47 #define RK809_RTC_CTRL 0x0d
48 #define RK80X_RTC_CTRL_STOP_RTC 0x01
49
50 #define RK805_RTC_STATUS 0x11
51 #define RK808_RTC_STATUS 0x11
52 #define RK809_RTC_STATUS 0x0e
53 #define RK80X_RTC_STATUS_POWER_UP 0x80
54
55 #define RK809_PMIC_SYS_CFG3 0xf4
56 #define RK809_PMIC_SYS_CFG3_SLP_FUN_MASK 0x18
57 #define RK809_PMIC_SYS_CFG3_SLP_FUN_NONE 0x00
58 #define RK809_PMIC_SYS_CFG3_SLP_FUN_SLEEP 0x08
59 #define RK809_PMIC_INT_STS0 0xf8
60 #define RK809_PMIC_INT_MSK0 0xf9
61 #define RK809_PMIC_INT_MSK0_PWRON_FALL_INT_IM 0x01
62 #define RK809_PMIC_INT_STS1 0xfa
63 #define RK809_PMIC_INT_MSK1 0xfb
64 #define RK809_PMIC_INT_STS2 0xfc
65 #define RK809_PMIC_INT_MSK2 0xfd
66 #define RK809_PMIC_GPIO_INT_CONFIG 0xfe
67 #define RK809_PMIC_GPIO_INT_CONFIG_INT_POL 0x02
68
69 #define RKSPI_CMD_READ (0 << 7)
70 #define RKSPI_CMD_WRITE (1 << 7)
71
72 struct rkpmic_vsel_range {
73 uint32_t base, delta;
74 uint8_t vsel_min, vsel_max;
75 };
76
77 struct rkpmic_regdata {
78 const char *name;
79 uint8_t vreg, vmask;
80 uint8_t sreg, smask;
81 const struct rkpmic_vsel_range *vsel_range;
82 };
83
84 /*
85 * Used by RK805 for BUCK1, BUCK2
86 * 0-59: 0.7125V-1.45V, step=12.5mV
87 * 60-62: 1.8V-2.2V, step=200mV
88 * 63: 2.3V
89 */
90 const struct rkpmic_vsel_range rk805_vsel_range1[] = {
91 { 712500, 12500, 0, 59 },
92 { 1800000, 200000, 60, 62 },
93 { 2300000, 0, 63, 63 },
94 {}
95 };
96
97 /*
98 * Used by RK805 for BUCK4
99 * 0-27: 0.8V-3.5V, step=100mV
100 */
101 const struct rkpmic_vsel_range rk805_vsel_range2[] = {
102 { 800000, 100000, 0, 27 },
103 {}
104 };
105
106 /*
107 * Used by RK805 for LDO1-3
108 * 0-26: 0.8V-3.4V, step=100mV
109 */
110 const struct rkpmic_vsel_range rk805_vsel_range3[] = {
111 { 800000, 100000, 0, 26 },
112 {}
113 };
114
115 const struct rkpmic_regdata rk805_regdata[] = {
116 { "DCDC_REG1", 0x2f, 0x3f, 0, 0, rk805_vsel_range1 },
117 { "DCDC_REG2", 0x33, 0x3f, 0, 0, rk805_vsel_range1 },
118 { "DCDC_REG4", 0x38, 0x1f, 0, 0, rk805_vsel_range2 },
119 { "LDO_REG1", 0x3b, 0x1f, 0, 0, rk805_vsel_range3 },
120 { "LDO_REG2", 0x3d, 0x1f, 0, 0, rk805_vsel_range3 },
121 { "LDO_REG3", 0x3f, 0x1f, 0, 0, rk805_vsel_range3 },
122 { }
123 };
124
125 /*
126 * Used by RK806 for BUCK
127 * 0-159: 0.5V-1.5V, step=6.25mV
128 * 160-236: 1.5V-3.4V, step=25mV
129 * 237-255: 3.4V-3.4V, step=0mV
130 */
131 const struct rkpmic_vsel_range rk806_vsel_range1[] = {
132 { 500000, 6250, 0, 159 },
133 { 1500000, 25000, 160, 236 },
134 { 3400000, 0, 237, 255 },
135 {}
136 };
137
138 /*
139 * Used by RK806 for LDO
140 * 0-232: 0.5V-3.4V, step=12.5mV
141 * 233-255: 3.4V-3.4V, step=0mV
142 */
143 const struct rkpmic_vsel_range rk806_vsel_range2[] = {
144 { 500000, 12500, 0, 232 },
145 { 3400000, 0, 233, 255 },
146 {}
147 };
148
149 const struct rkpmic_regdata rk806_regdata[] = {
150 { "dcdc-reg1", 0x1a, 0xff, 0, 0, rk806_vsel_range1 },
151 { "dcdc-reg2", 0x1b, 0xff, 0, 0, rk806_vsel_range1 },
152 { "dcdc-reg3", 0x1c, 0xff, 0, 0, rk806_vsel_range1 },
153 { "dcdc-reg4", 0x1d, 0xff, 0, 0, rk806_vsel_range1 },
154 { "dcdc-reg5", 0x1e, 0xff, 0, 0, rk806_vsel_range1 },
155 { "dcdc-reg6", 0x1f, 0xff, 0, 0, rk806_vsel_range1 },
156 { "dcdc-reg7", 0x20, 0xff, 0, 0, rk806_vsel_range1 },
157 { "dcdc-reg8", 0x21, 0xff, 0, 0, rk806_vsel_range1 },
158 { "dcdc-reg9", 0x22, 0xff, 0, 0, rk806_vsel_range1 },
159 { "dcdc-reg10", 0x23, 0xff, 0, 0, rk806_vsel_range1 },
160 { "nldo-reg1", 0x43, 0xff, 0, 0, rk806_vsel_range2 },
161 { "nldo-reg2", 0x44, 0xff, 0, 0, rk806_vsel_range2 },
162 { "nldo-reg3", 0x45, 0xff, 0, 0, rk806_vsel_range2 },
163 { "nldo-reg4", 0x46, 0xff, 0, 0, rk806_vsel_range2 },
164 { "nldo-reg5", 0x47, 0xff, 0, 0, rk806_vsel_range2 },
165 { "pldo-reg1", 0x4e, 0xff, 0, 0, rk806_vsel_range2 },
166 { "pldo-reg2", 0x4f, 0xff, 0, 0, rk806_vsel_range2 },
167 { "pldo-reg3", 0x50, 0xff, 0, 0, rk806_vsel_range2 },
168 { "pldo-reg4", 0x51, 0xff, 0, 0, rk806_vsel_range2 },
169 { "pldo-reg5", 0x52, 0xff, 0, 0, rk806_vsel_range2 },
170 { "pldo-reg6", 0x53, 0xff, 0, 0, rk806_vsel_range2 },
171 { }
172 };
173
174 /*
175 * Used by RK808 for BUCK1 & BUCK2
176 * 0-63: 0.7125V-1.5V, step=12.5mV
177 */
178 const struct rkpmic_vsel_range rk808_vsel_range1[] = {
179 { 712500, 12500, 0, 63 },
180 {}
181 };
182
183 /*
184 * Used by RK808 for BUCK4
185 * 0-15: 1.8V-3.3V,step=100mV
186 */
187 const struct rkpmic_vsel_range rk808_vsel_range2[] = {
188 { 1800000, 100000, 0, 15 },
189 {}
190 };
191
192 /*
193 * Used by RK808 for LDO1-2, 4-5, 8
194 * 0-16: 1.8V-3.4V, step=100mV
195 */
196 const struct rkpmic_vsel_range rk808_vsel_range3[] = {
197 { 1800000, 100000, 0, 16 },
198 {}
199 };
200
201 /*
202 * Used by RK808 for LDO3
203 * 0-12: 0.8V~2.0V, step=100mV
204 * 13: 2.2V
205 * 15: 2.5V
206 */
207 const struct rkpmic_vsel_range rk808_vsel_range4[] = {
208 { 800000, 100000, 0, 12 },
209 { 2200000, 0, 13, 13 },
210 { 2500000, 0, 15, 15 },
211 {}
212 };
213
214 /*
215 * Used by RK808 for LDO6-7
216 * 0-17: 0.8V-2.5V,step=100mV
217 */
218 const struct rkpmic_vsel_range rk808_vsel_range5[] = {
219 { 800000, 100000, 0, 17 },
220 {}
221 };
222
223 const struct rkpmic_regdata rk808_regdata[] = {
224 { "DCDC_REG1", 0x2f, 0x3f, 0, 0, rk808_vsel_range1 },
225 { "DCDC_REG2", 0x33, 0x3f, 0, 0, rk808_vsel_range1 },
226 { "DCDC_REG4", 0x38, 0x0f, 0, 0, rk808_vsel_range2 },
227 { "LDO_REG1", 0x3b, 0x1f, 0, 0, rk808_vsel_range3 },
228 { "LDO_REG2", 0x3d, 0x1f, 0, 0, rk808_vsel_range3 },
229 { "LDO_REG3", 0x3f, 0x0f, 0, 0, rk808_vsel_range4 },
230 { "LDO_REG4", 0x41, 0x1f, 0, 0, rk808_vsel_range3 },
231 { "LDO_REG5", 0x43, 0x1f, 0, 0, rk808_vsel_range3 },
232 { "LDO_REG6", 0x45, 0x1f, 0, 0, rk808_vsel_range5 },
233 { "LDO_REG7", 0x47, 0x1f, 0, 0, rk808_vsel_range5 },
234 { "LDO_REG8", 0x49, 0x1f, 0, 0, rk808_vsel_range3 },
235 { }
236 };
237
238 /*
239 * Used by RK809 for BUCK1-3
240 * 0-80: 0.5V-1.5V,step=12.5mV
241 * 81-89: 1.6V-2.4V,step=100mV
242 */
243 const struct rkpmic_vsel_range rk809_vsel_range1[] = {
244 { 500000, 12500, 0, 80 },
245 { 1600000, 100000, 81, 89 },
246 {}
247 };
248
249 /*
250 * Used by RK809 for BUCK4
251 * 0-80: 0.5V-1.5V,step=12.5mV
252 * 81-99: 1.6V-3.4V,step=100mV
253 */
254 const struct rkpmic_vsel_range rk809_vsel_range2[] = {
255 { 500000, 12500, 0, 80 },
256 { 1600000, 100000, 81, 99 },
257 {}
258 };
259
260 /*
261 * Used by RK809 for BUCK5
262 * 0: 1.5V
263 * 1-3: 1.8V-2.2V,step=200mV
264 * 4-5: 2.8V-3.0V,step=200mV
265 * 6-7: 3.3V-3.6V,step=300mV
266 */
267 const struct rkpmic_vsel_range rk809_vsel_range3[] = {
268 { 1500000, 0, 0, 0 },
269 { 1800000, 200000, 1, 3 },
270 { 2800000, 200000, 4, 5 },
271 { 3300000, 300000, 6, 7 },
272 {}
273 };
274
275 /*
276 * Used by RK809 for LDO1-7
277 * 0-112: 0.6V-3.4V,step=25mV
278 */
279 const struct rkpmic_vsel_range rk809_vsel_range4[] = {
280 { 600000, 25000, 0, 112 },
281 {}
282 };
283
284 const struct rkpmic_regdata rk809_regdata[] = {
285 { "DCDC_REG1", 0xbb, 0x7f, 0xb5, 0x01, rk809_vsel_range1 },
286 { "DCDC_REG2", 0xbe, 0x7f, 0xb5, 0x02, rk809_vsel_range1 },
287 { "DCDC_REG3", 0xc1, 0x7f, 0xb5, 0x04, rk809_vsel_range1 },
288 { "DCDC_REG4", 0xc4, 0x7f, 0xb5, 0x08, rk809_vsel_range2 },
289 { "DCDC_REG5", 0xde, 0x0f, 0xb5, 0x20, rk809_vsel_range3 },
290 { "LDO_REG1", 0xcc, 0x7f, 0xb6, 0x01, rk809_vsel_range4 },
291 { "LDO_REG2", 0xce, 0x7f, 0xb6, 0x02, rk809_vsel_range4 },
292 { "LDO_REG3", 0xd0, 0x7f, 0xb6, 0x04, rk809_vsel_range4 },
293 { "LDO_REG4", 0xd2, 0x7f, 0xb6, 0x08, rk809_vsel_range4 },
294 { "LDO_REG5", 0xd4, 0x7f, 0xb6, 0x10, rk809_vsel_range4 },
295 { "LDO_REG6", 0xd6, 0x7f, 0xb6, 0x20, rk809_vsel_range4 },
296 { "LDO_REG7", 0xd8, 0x7f, 0xb6, 0x40, rk809_vsel_range4 },
297 { "LDO_REG8", 0xda, 0x7f, 0xb6, 0x80, rk809_vsel_range4 },
298 { "LDO_REG9", 0xdc, 0x7f, 0xb5, 0x10, rk809_vsel_range4 },
299 { "SWITCH_REG1", 0, 0, 0xb5, 0x40, NULL },
300 { "SWITCH_REG2", 0, 0, 0xb5, 0x80, NULL },
301 { }
302 };
303
304 /*
305 * Used by RK817 for BOOST
306 * 0-7: 4.7V-5.4V,step=100mV
307 */
308 const struct rkpmic_vsel_range rk817_boost_range[] = {
309 { 4700000, 100000, 0, 7 },
310 {}
311 };
312
313 const struct rkpmic_regdata rk817_regdata[] = {
314 { "DCDC_REG1", 0xbb, 0x7f, 0, 0, rk809_vsel_range1 },
315 { "DCDC_REG2", 0xbe, 0x7f, 0, 0, rk809_vsel_range1 },
316 { "DCDC_REG3", 0xc1, 0x7f, 0, 0, rk809_vsel_range1 },
317 { "DCDC_REG4", 0xc4, 0x7f, 0, 0, rk809_vsel_range2 },
318 { "LDO_REG1", 0xcc, 0x7f, 0, 0, rk809_vsel_range4 },
319 { "LDO_REG2", 0xce, 0x7f, 0, 0, rk809_vsel_range4 },
320 { "LDO_REG3", 0xd0, 0x7f, 0, 0, rk809_vsel_range4 },
321 { "LDO_REG4", 0xd2, 0x7f, 0, 0, rk809_vsel_range4 },
322 { "LDO_REG5", 0xd4, 0x7f, 0, 0, rk809_vsel_range4 },
323 { "LDO_REG6", 0xd6, 0x7f, 0, 0, rk809_vsel_range4 },
324 { "LDO_REG7", 0xd8, 0x7f, 0, 0, rk809_vsel_range4 },
325 { "LDO_REG8", 0xda, 0x7f, 0, 0, rk809_vsel_range4 },
326 { "LDO_REG9", 0xdc, 0x7f, 0, 0, rk809_vsel_range4 },
327 { "BOOST", 0xde, 0x07, 0, 0, rk817_boost_range },
328 { }
329 };
330
331 struct rkpmic_softc {
332 struct device sc_dev;
333 int sc_node;
334
335 i2c_tag_t sc_i2c_tag;
336 i2c_addr_t sc_i2c_addr;
337 spi_tag_t sc_spi_tag;
338 struct spi_config sc_spi_conf;
339
340 int sc_rtc_ctrl_reg, sc_rtc_status_reg;
341 struct todr_chip_handle sc_todr;
342 const struct rkpmic_regdata *sc_regdata;
343
344 int (*sc_read)(struct rkpmic_softc *, uint8_t, void *, size_t);
345 int (*sc_write)(struct rkpmic_softc *, uint8_t, void *, size_t);
346
347 void *sc_ih;
348 };
349
350 int rkpmic_i2c_match(struct device *, void *, void *);
351 void rkpmic_i2c_attach(struct device *, struct device *, void *);
352 int rkpmic_i2c_read(struct rkpmic_softc *, uint8_t, void *, size_t);
353 int rkpmic_i2c_write(struct rkpmic_softc *, uint8_t, void *, size_t);
354
355 int rkpmic_spi_match(struct device *, void *, void *);
356 void rkpmic_spi_attach(struct device *, struct device *, void *);
357 int rkpmic_spi_read(struct rkpmic_softc *, uint8_t, void *, size_t);
358 int rkpmic_spi_write(struct rkpmic_softc *, uint8_t, void *, size_t);
359
360 void rkpmic_attach(struct device *, struct device *, void *);
361 int rkpmic_activate(struct device *, int);
362
363 const struct cfattach rkpmic_i2c_ca = {
364 sizeof(struct rkpmic_softc), rkpmic_i2c_match, rkpmic_i2c_attach,
365 NULL, rkpmic_activate
366 };
367
368 const struct cfattach rkpmic_spi_ca = {
369 sizeof(struct rkpmic_softc), rkpmic_spi_match, rkpmic_spi_attach
370 };
371
372 struct cfdriver rkpmic_cd = {
373 NULL, "rkpmic", DV_DULL
374 };
375
376 int rkpmic_intr(void *);
377 void rkpmic_attach_regulator(struct rkpmic_softc *, int);
378 uint8_t rkpmic_reg_read(struct rkpmic_softc *, int);
379 void rkpmic_reg_write(struct rkpmic_softc *, int, uint8_t);
380 int rkpmic_clock_read(struct rkpmic_softc *, struct clock_ymdhms *);
381 int rkpmic_clock_write(struct rkpmic_softc *, struct clock_ymdhms *);
382 int rkpmic_gettime(struct todr_chip_handle *, struct timeval *);
383 int rkpmic_settime(struct todr_chip_handle *, struct timeval *);
384
385 int
rkpmic_i2c_match(struct device * parent,void * match,void * aux)386 rkpmic_i2c_match(struct device *parent, void *match, void *aux)
387 {
388 struct i2c_attach_args *ia = aux;
389
390 return (strcmp(ia->ia_name, "rockchip,rk805") == 0 ||
391 strcmp(ia->ia_name, "rockchip,rk808") == 0 ||
392 strcmp(ia->ia_name, "rockchip,rk809") == 0 ||
393 strcmp(ia->ia_name, "rockchip,rk817") == 0);
394 }
395
396 void
rkpmic_i2c_attach(struct device * parent,struct device * self,void * aux)397 rkpmic_i2c_attach(struct device *parent, struct device *self, void *aux)
398 {
399 struct rkpmic_softc *sc = (struct rkpmic_softc *)self;
400 struct i2c_attach_args *ia = aux;
401
402 sc->sc_i2c_tag = ia->ia_tag;
403 sc->sc_i2c_addr = ia->ia_addr;
404 sc->sc_node = *(int *)ia->ia_cookie;
405 sc->sc_read = rkpmic_i2c_read;
406 sc->sc_write = rkpmic_i2c_write;
407
408 rkpmic_attach(parent, self, aux);
409 }
410
411 int
rkpmic_spi_match(struct device * parent,void * match,void * aux)412 rkpmic_spi_match(struct device *parent, void *match, void *aux)
413 {
414 struct spi_attach_args *sa = aux;
415
416 return (strcmp(sa->sa_name, "rockchip,rk806") == 0);
417 }
418
419 void
rkpmic_spi_attach(struct device * parent,struct device * self,void * aux)420 rkpmic_spi_attach(struct device *parent, struct device *self, void *aux)
421 {
422 struct rkpmic_softc *sc = (struct rkpmic_softc *)self;
423 struct spi_attach_args *sa = aux;
424
425 sc->sc_spi_tag = sa->sa_tag;
426 sc->sc_node = *(int *)sa->sa_cookie;
427 sc->sc_read = rkpmic_spi_read;
428 sc->sc_write = rkpmic_spi_write;
429
430 sc->sc_spi_conf.sc_bpw = 8;
431 sc->sc_spi_conf.sc_freq =
432 OF_getpropint(sc->sc_node, "spi-max-frequency", 1000000);
433 sc->sc_spi_conf.sc_cs = OF_getpropint(sc->sc_node, "reg", 0);
434
435 rkpmic_attach(parent, self, aux);
436 }
437
438 void
rkpmic_attach(struct device * parent,struct device * self,void * aux)439 rkpmic_attach(struct device *parent, struct device *self, void *aux)
440 {
441 struct rkpmic_softc *sc = (struct rkpmic_softc *)self;
442 const char *chip;
443 uint8_t val;
444 int node;
445
446 if (OF_is_compatible(sc->sc_node, "rockchip,rk805")) {
447 chip = "RK805";
448 sc->sc_rtc_ctrl_reg = RK805_RTC_CTRL;
449 sc->sc_rtc_status_reg = RK805_RTC_STATUS;
450 sc->sc_regdata = rk805_regdata;
451 } else if (OF_is_compatible(sc->sc_node, "rockchip,rk806")) {
452 chip = "RK806";
453 sc->sc_regdata = rk806_regdata;
454 } else if (OF_is_compatible(sc->sc_node, "rockchip,rk808")) {
455 chip = "RK808";
456 sc->sc_rtc_ctrl_reg = RK808_RTC_CTRL;
457 sc->sc_rtc_status_reg = RK808_RTC_STATUS;
458 sc->sc_regdata = rk808_regdata;
459 } else if (OF_is_compatible(sc->sc_node, "rockchip,rk809")) {
460 chip = "RK809";
461 sc->sc_rtc_ctrl_reg = RK809_RTC_CTRL;
462 sc->sc_rtc_status_reg = RK809_RTC_STATUS;
463 sc->sc_regdata = rk809_regdata;
464 } else {
465 chip = "RK817";
466 sc->sc_rtc_ctrl_reg = RK809_RTC_CTRL;
467 sc->sc_rtc_status_reg = RK809_RTC_STATUS;
468 sc->sc_regdata = rk817_regdata;
469 }
470 printf(": %s\n", chip);
471
472 if (sc->sc_rtc_ctrl_reg) {
473 sc->sc_todr.cookie = sc;
474 sc->sc_todr.todr_gettime = rkpmic_gettime;
475 sc->sc_todr.todr_settime = rkpmic_settime;
476 sc->sc_todr.todr_quality = 0;
477 todr_attach(&sc->sc_todr);
478 }
479
480 node = OF_getnodebyname(sc->sc_node, "regulators");
481 if (node == 0)
482 return;
483 for (node = OF_child(node); node; node = OF_peer(node))
484 rkpmic_attach_regulator(sc, node);
485
486 if (OF_is_compatible(sc->sc_node, "rockchip,rk809")) {
487 /* Mask all interrupts. */
488 rkpmic_reg_write(sc, RK809_PMIC_INT_MSK0, 0xff);
489 rkpmic_reg_write(sc, RK809_PMIC_INT_MSK1, 0xff);
490 rkpmic_reg_write(sc, RK809_PMIC_INT_MSK2, 0xff);
491
492 /* Ack all interrupts. */
493 rkpmic_reg_write(sc, RK809_PMIC_INT_STS0, 0xff);
494 rkpmic_reg_write(sc, RK809_PMIC_INT_STS1, 0xff);
495 rkpmic_reg_write(sc, RK809_PMIC_INT_STS2, 0xff);
496
497 /* Set interrupt pin to active-low. */
498 val = rkpmic_reg_read(sc, RK809_PMIC_GPIO_INT_CONFIG);
499 rkpmic_reg_write(sc, RK809_PMIC_GPIO_INT_CONFIG,
500 val & ~RK809_PMIC_GPIO_INT_CONFIG_INT_POL);
501
502 sc->sc_ih = fdt_intr_establish(sc->sc_node, IPL_TTY,
503 rkpmic_intr, sc, sc->sc_dev.dv_xname);
504
505 /* Unmask power button interrupt. */
506 rkpmic_reg_write(sc, RK809_PMIC_INT_MSK0,
507 ~RK809_PMIC_INT_MSK0_PWRON_FALL_INT_IM);
508
509 #ifdef SUSPEND
510 if (OF_getpropbool(sc->sc_node, "wakeup-source"))
511 device_register_wakeup(&sc->sc_dev);
512 #endif
513 }
514 }
515
516 int
rkpmic_activate(struct device * self,int act)517 rkpmic_activate(struct device *self, int act)
518 {
519 struct rkpmic_softc *sc = (struct rkpmic_softc *)self;
520 uint8_t val;
521
522 switch (act) {
523 case DVACT_SUSPEND:
524 if (OF_is_compatible(sc->sc_node, "rockchip,rk809")) {
525 val = rkpmic_reg_read(sc, RK809_PMIC_SYS_CFG3);
526 val &= ~RK809_PMIC_SYS_CFG3_SLP_FUN_MASK;
527 val |= RK809_PMIC_SYS_CFG3_SLP_FUN_SLEEP;
528 rkpmic_reg_write(sc, RK809_PMIC_SYS_CFG3, val);
529 }
530 break;
531 case DVACT_RESUME:
532 if (OF_is_compatible(sc->sc_node, "rockchip,rk809")) {
533 val = rkpmic_reg_read(sc, RK809_PMIC_SYS_CFG3);
534 val &= ~RK809_PMIC_SYS_CFG3_SLP_FUN_MASK;
535 val |= RK809_PMIC_SYS_CFG3_SLP_FUN_NONE;
536 rkpmic_reg_write(sc, RK809_PMIC_SYS_CFG3, val);
537 rkpmic_reg_write(sc, RK809_PMIC_INT_STS0, 0xff);
538 }
539 break;
540 }
541
542 return 0;
543 }
544
545 int
rkpmic_intr(void * arg)546 rkpmic_intr(void *arg)
547 {
548 extern int allowpowerdown;
549 struct rkpmic_softc *sc = arg;
550
551 if (allowpowerdown) {
552 allowpowerdown = 0;
553 prsignal(initprocess, SIGUSR2);
554 }
555
556 rkpmic_reg_write(sc, RK809_PMIC_INT_STS0, 0xff);
557 return 1;
558 }
559
560 struct rkpmic_regulator {
561 struct rkpmic_softc *rr_sc;
562
563 uint8_t rr_vreg, rr_vmask;
564 const struct rkpmic_vsel_range *rr_vsel_range;
565
566 struct regulator_device rr_rd;
567 };
568
569 uint32_t rkpmic_get_voltage(void *);
570 int rkpmic_set_voltage(void *, uint32_t);
571 int rkpmic_do_set_voltage(struct rkpmic_regulator *, uint32_t, int);
572
573 void
rkpmic_attach_regulator(struct rkpmic_softc * sc,int node)574 rkpmic_attach_regulator(struct rkpmic_softc *sc, int node)
575 {
576 struct rkpmic_regulator *rr;
577 char name[32];
578 uint32_t voltage;
579 int i, snode;
580 uint8_t val;
581
582 name[0] = 0;
583 OF_getprop(node, "name", name, sizeof(name));
584 name[sizeof(name) - 1] = 0;
585 for (i = 0; sc->sc_regdata[i].name; i++) {
586 if (strcmp(sc->sc_regdata[i].name, name) == 0)
587 break;
588 }
589 if (sc->sc_regdata[i].name == NULL)
590 return;
591
592 rr = malloc(sizeof(*rr), M_DEVBUF, M_WAITOK | M_ZERO);
593 rr->rr_sc = sc;
594
595 rr->rr_vreg = sc->sc_regdata[i].vreg;
596 rr->rr_vmask = sc->sc_regdata[i].vmask;
597 rr->rr_vsel_range = sc->sc_regdata[i].vsel_range;
598
599 rr->rr_rd.rd_node = node;
600 rr->rr_rd.rd_cookie = rr;
601 rr->rr_rd.rd_get_voltage = rkpmic_get_voltage;
602 rr->rr_rd.rd_set_voltage = rkpmic_set_voltage;
603 regulator_register(&rr->rr_rd);
604
605 if (sc->sc_regdata[i].smask) {
606 snode = OF_getnodebyname(node, "regulator-state-mem");
607 if (snode) {
608 val = rkpmic_reg_read(sc, sc->sc_regdata[i].sreg);
609 if (OF_getpropbool(snode, "regulator-on-in-suspend"))
610 val |= sc->sc_regdata[i].smask;
611 if (OF_getpropbool(snode, "regulator-off-in-suspend"))
612 val &= ~sc->sc_regdata[i].smask;
613 rkpmic_reg_write(sc, sc->sc_regdata[i].sreg, val);
614
615 voltage = OF_getpropint(snode,
616 "regulator-suspend-min-microvolt", 0);
617 voltage = OF_getpropint(snode,
618 "regulator-suspend-microvolt", voltage);
619 if (voltage > 0)
620 rkpmic_do_set_voltage(rr, voltage, 1);
621 }
622 }
623 }
624
625 uint32_t
rkpmic_get_voltage(void * cookie)626 rkpmic_get_voltage(void *cookie)
627 {
628 struct rkpmic_regulator *rr = cookie;
629 const struct rkpmic_vsel_range *vsel_range = rr->rr_vsel_range;
630 uint8_t vsel;
631 uint32_t ret = 0;
632
633 if (vsel_range == NULL)
634 return 0;
635
636 vsel = rkpmic_reg_read(rr->rr_sc, rr->rr_vreg) & rr->rr_vmask;
637
638 while (vsel_range->base) {
639 ret = vsel_range->base;
640 if (vsel >= vsel_range->vsel_min &&
641 vsel <= vsel_range->vsel_max) {
642 ret += (vsel - vsel_range->vsel_min) *
643 vsel_range->delta;
644 break;
645 } else
646 ret += (vsel_range->vsel_max - vsel_range->vsel_min) *
647 vsel_range->delta;
648 vsel_range++;
649
650 }
651
652 return ret;
653 }
654
655 int
rkpmic_set_voltage(void * cookie,uint32_t voltage)656 rkpmic_set_voltage(void *cookie, uint32_t voltage)
657 {
658 return rkpmic_do_set_voltage(cookie, voltage, 0);
659 }
660
661 int
rkpmic_do_set_voltage(struct rkpmic_regulator * rr,uint32_t voltage,int sleep)662 rkpmic_do_set_voltage(struct rkpmic_regulator *rr, uint32_t voltage, int sleep)
663 {
664 const struct rkpmic_vsel_range *vsel_range = rr->rr_vsel_range;
665 uint32_t vmin, vmax, volt;
666 uint8_t reg, vsel;
667
668 if (vsel_range == NULL)
669 return ENODEV;
670
671 while (vsel_range->base) {
672 vmin = vsel_range->base;
673 vmax = vmin + (vsel_range->vsel_max - vsel_range->vsel_min) *
674 vsel_range->delta;
675 if (voltage < vmin)
676 return EINVAL;
677 if (voltage <= vmax) {
678 vsel = vsel_range->vsel_min;
679 volt = vsel_range->base;
680 while (vsel <= vsel_range->vsel_max) {
681 if (volt == voltage)
682 break;
683 else {
684 vsel++;
685 volt += vsel_range->delta;
686 }
687 }
688 if (volt != voltage)
689 return EINVAL;
690 break;
691 }
692 vsel_range++;
693 }
694
695 if (vsel_range->base == 0)
696 return EINVAL;
697
698 reg = rkpmic_reg_read(rr->rr_sc, rr->rr_vreg + sleep);
699 reg &= ~rr->rr_vmask;
700 reg |= vsel;
701 rkpmic_reg_write(rr->rr_sc, rr->rr_vreg + sleep, reg);
702
703 return 0;
704 }
705
706 int
rkpmic_gettime(struct todr_chip_handle * handle,struct timeval * tv)707 rkpmic_gettime(struct todr_chip_handle *handle, struct timeval *tv)
708 {
709 struct rkpmic_softc *sc = handle->cookie;
710 struct clock_ymdhms dt;
711 time_t secs;
712 int error;
713
714 error = rkpmic_clock_read(sc, &dt);
715 if (error)
716 return error;
717
718 if (dt.dt_sec > 59 || dt.dt_min > 59 || dt.dt_hour > 23 ||
719 dt.dt_day > 31 || dt.dt_day == 0 ||
720 dt.dt_mon > 12 || dt.dt_mon == 0 ||
721 dt.dt_year < POSIX_BASE_YEAR)
722 return EINVAL;
723
724 /*
725 * The RTC thinks November has 31 days. Match what Linux does
726 * and undo the damage by considering the calendars to be in
727 * sync on January 1st 2016.
728 */
729 secs = clock_ymdhms_to_secs(&dt);
730 secs += (dt.dt_year - 2016 + (dt.dt_mon == 12 ? 1 : 0)) * 86400;
731
732 tv->tv_sec = secs;
733 tv->tv_usec = 0;
734 return 0;
735 }
736
737 int
rkpmic_settime(struct todr_chip_handle * handle,struct timeval * tv)738 rkpmic_settime(struct todr_chip_handle *handle, struct timeval *tv)
739 {
740 struct rkpmic_softc *sc = handle->cookie;
741 struct clock_ymdhms dt;
742 time_t secs;
743
744 /*
745 * Take care of the November 31st braindamage here as well.
746 * Don't try to be clever, just do the conversion in two
747 * steps, first taking care of November 31 in previous years,
748 * and then taking care of days in December of the current
749 * year. December 1st turns into November 31st!
750 */
751 secs = tv->tv_sec;
752 clock_secs_to_ymdhms(secs, &dt);
753 secs -= (dt.dt_year - 2016) * 86400;
754 clock_secs_to_ymdhms(secs, &dt);
755 if (dt.dt_mon == 12) {
756 dt.dt_day--;
757 if (dt.dt_day == 0) {
758 dt.dt_mon = 11;
759 dt.dt_day = 31;
760 }
761 }
762
763 return rkpmic_clock_write(sc, &dt);
764 }
765
766 uint8_t
rkpmic_reg_read(struct rkpmic_softc * sc,int reg)767 rkpmic_reg_read(struct rkpmic_softc *sc, int reg)
768 {
769 uint8_t cmd = reg;
770 uint8_t val;
771
772 if (sc->sc_read(sc, cmd, &val, sizeof(val))) {
773 printf("%s: can't read register 0x%02x\n",
774 sc->sc_dev.dv_xname, reg);
775 val = 0xff;
776 }
777
778 return val;
779 }
780
781 void
rkpmic_reg_write(struct rkpmic_softc * sc,int reg,uint8_t val)782 rkpmic_reg_write(struct rkpmic_softc *sc, int reg, uint8_t val)
783 {
784 uint8_t cmd = reg;
785
786 if (sc->sc_write(sc, cmd, &val, sizeof(val))) {
787 printf("%s: can't write register 0x%02x\n",
788 sc->sc_dev.dv_xname, reg);
789 }
790 }
791
792 int
rkpmic_clock_read(struct rkpmic_softc * sc,struct clock_ymdhms * dt)793 rkpmic_clock_read(struct rkpmic_softc *sc, struct clock_ymdhms *dt)
794 {
795 uint8_t regs[RK80X_NRTC_REGS];
796 uint8_t cmd = RK80X_SECONDS;
797 uint8_t status;
798 int error;
799
800 error = sc->sc_read(sc, cmd, regs, RK80X_NRTC_REGS);
801
802 if (error) {
803 printf("%s: can't read RTC\n", sc->sc_dev.dv_xname);
804 return error;
805 }
806
807 /*
808 * Convert the RK80x's register values into something useable.
809 */
810 dt->dt_sec = FROMBCD(regs[0]);
811 dt->dt_min = FROMBCD(regs[1]);
812 dt->dt_hour = FROMBCD(regs[2]);
813 dt->dt_day = FROMBCD(regs[3]);
814 dt->dt_mon = FROMBCD(regs[4]);
815 dt->dt_year = FROMBCD(regs[5]) + 2000;
816
817 /* Consider the time to be invalid if the POWER_UP bit is set. */
818 status = rkpmic_reg_read(sc, sc->sc_rtc_status_reg);
819 if (status & RK80X_RTC_STATUS_POWER_UP)
820 return EINVAL;
821
822 return 0;
823 }
824
825 int
rkpmic_clock_write(struct rkpmic_softc * sc,struct clock_ymdhms * dt)826 rkpmic_clock_write(struct rkpmic_softc *sc, struct clock_ymdhms *dt)
827 {
828 uint8_t regs[RK80X_NRTC_REGS];
829 uint8_t cmd = RK80X_SECONDS;
830 int error;
831
832 /*
833 * Convert our time representation into something the RK80x
834 * can understand.
835 */
836 regs[0] = TOBCD(dt->dt_sec);
837 regs[1] = TOBCD(dt->dt_min);
838 regs[2] = TOBCD(dt->dt_hour);
839 regs[3] = TOBCD(dt->dt_day);
840 regs[4] = TOBCD(dt->dt_mon);
841 regs[5] = TOBCD(dt->dt_year - 2000);
842 regs[6] = TOBCD(dt->dt_wday);
843
844 /* Stop RTC such that we can write to it. */
845 rkpmic_reg_write(sc, sc->sc_rtc_ctrl_reg, RK80X_RTC_CTRL_STOP_RTC);
846
847 error = sc->sc_write(sc, cmd, regs, RK80X_NRTC_REGS);
848
849 /* Restart RTC. */
850 rkpmic_reg_write(sc, sc->sc_rtc_ctrl_reg, 0);
851
852 if (error) {
853 printf("%s: can't write RTC\n", sc->sc_dev.dv_xname);
854 return error;
855 }
856
857 /* Clear POWER_UP bit to indicate the time is now valid. */
858 rkpmic_reg_write(sc, sc->sc_rtc_status_reg, RK80X_RTC_STATUS_POWER_UP);
859
860 return 0;
861 }
862
863 int
rkpmic_i2c_read(struct rkpmic_softc * sc,uint8_t cmd,void * buf,size_t buflen)864 rkpmic_i2c_read(struct rkpmic_softc *sc, uint8_t cmd, void *buf, size_t buflen)
865 {
866 int error;
867
868 iic_acquire_bus(sc->sc_i2c_tag, I2C_F_POLL);
869 error = iic_exec(sc->sc_i2c_tag, I2C_OP_READ_WITH_STOP,
870 sc->sc_i2c_addr, &cmd, sizeof(cmd), buf, buflen, I2C_F_POLL);
871 iic_release_bus(sc->sc_i2c_tag, I2C_F_POLL);
872
873 return error;
874 }
875
876 int
rkpmic_i2c_write(struct rkpmic_softc * sc,uint8_t cmd,void * buf,size_t buflen)877 rkpmic_i2c_write(struct rkpmic_softc *sc, uint8_t cmd, void *buf, size_t buflen)
878 {
879 int error;
880
881 iic_acquire_bus(sc->sc_i2c_tag, I2C_F_POLL);
882 error = iic_exec(sc->sc_i2c_tag, I2C_OP_WRITE_WITH_STOP,
883 sc->sc_i2c_addr, &cmd, sizeof(cmd), buf, buflen, I2C_F_POLL);
884 iic_release_bus(sc->sc_i2c_tag, I2C_F_POLL);
885
886 return error;
887 }
888
889 int
rkpmic_spi_read(struct rkpmic_softc * sc,uint8_t cmd,void * buf,size_t buflen)890 rkpmic_spi_read(struct rkpmic_softc *sc, uint8_t cmd, void *buf, size_t buflen)
891 {
892 uint8_t cmdbuf[3];
893 int error;
894
895 cmdbuf[0] = RKSPI_CMD_READ | (buflen - 1);
896 cmdbuf[1] = cmd; /* 16-bit addr low */
897 cmdbuf[2] = 0x00; /* 16-bit addr high */
898
899 spi_acquire_bus(sc->sc_spi_tag, 0);
900 spi_config(sc->sc_spi_tag, &sc->sc_spi_conf);
901 error = spi_transfer(sc->sc_spi_tag, cmdbuf, NULL, sizeof(cmdbuf),
902 SPI_KEEP_CS);
903 if (!error)
904 error = spi_read(sc->sc_spi_tag, buf, buflen);
905 spi_release_bus(sc->sc_spi_tag, 0);
906
907 return error;
908 }
909
910 int
rkpmic_spi_write(struct rkpmic_softc * sc,uint8_t cmd,void * buf,size_t buflen)911 rkpmic_spi_write(struct rkpmic_softc *sc, uint8_t cmd, void *buf, size_t buflen)
912 {
913 uint8_t cmdbuf[3];
914 int error;
915
916 cmdbuf[0] = RKSPI_CMD_WRITE | (buflen - 1);
917 cmdbuf[1] = cmd; /* 16-bit addr low */
918 cmdbuf[2] = 0x00; /* 16-bit addr high */
919
920 spi_acquire_bus(sc->sc_spi_tag, 0);
921 spi_config(sc->sc_spi_tag, &sc->sc_spi_conf);
922 error = spi_transfer(sc->sc_spi_tag, cmdbuf, NULL, sizeof(cmdbuf),
923 SPI_KEEP_CS);
924 if (!error)
925 error = spi_write(sc->sc_spi_tag, buf, buflen);
926 spi_release_bus(sc->sc_spi_tag, 0);
927
928 return error;
929 }
930