1 /* $OpenBSD: dwiicreg.h,v 1.2 2019/08/06 06:56:29 kettenis Exp $ */ 2 /* 3 * Synopsys DesignWare I2C controller 4 * 5 * Copyright (c) 2015, 2016 joshua stein <jcs@openbsd.org> 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* register offsets */ 21 #define DW_IC_CON 0x0 22 #define DW_IC_TAR 0x4 23 #define DW_IC_DATA_CMD 0x10 24 #define DW_IC_SS_SCL_HCNT 0x14 25 #define DW_IC_SS_SCL_LCNT 0x18 26 #define DW_IC_FS_SCL_HCNT 0x1c 27 #define DW_IC_FS_SCL_LCNT 0x20 28 #define DW_IC_INTR_STAT 0x2c 29 #define DW_IC_INTR_MASK 0x30 30 #define DW_IC_RAW_INTR_STAT 0x34 31 #define DW_IC_RX_TL 0x38 32 #define DW_IC_TX_TL 0x3c 33 #define DW_IC_CLR_INTR 0x40 34 #define DW_IC_CLR_RX_UNDER 0x44 35 #define DW_IC_CLR_RX_OVER 0x48 36 #define DW_IC_CLR_TX_OVER 0x4c 37 #define DW_IC_CLR_RD_REQ 0x50 38 #define DW_IC_CLR_TX_ABRT 0x54 39 #define DW_IC_CLR_RX_DONE 0x58 40 #define DW_IC_CLR_ACTIVITY 0x5c 41 #define DW_IC_CLR_STOP_DET 0x60 42 #define DW_IC_CLR_START_DET 0x64 43 #define DW_IC_CLR_GEN_CALL 0x68 44 #define DW_IC_ENABLE 0x6c 45 #define DW_IC_STATUS 0x70 46 #define DW_IC_TXFLR 0x74 47 #define DW_IC_RXFLR 0x78 48 #define DW_IC_SDA_HOLD 0x7c 49 #define DW_IC_TX_ABRT_SOURCE 0x80 50 #define DW_IC_ENABLE_STATUS 0x9c 51 #define DW_IC_COMP_PARAM_1 0xf4 52 #define DW_IC_TX_FIFO_DEPTH(x) ((((x) >> 16) & 0xff) + 1) 53 #define DW_IC_RX_FIFO_DEPTH(x) ((((x) >> 8) & 0xff) + 1) 54 #define DW_IC_COMP_VERSION 0xf8 55 #define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A 56 #define DW_IC_COMP_TYPE 0xfc 57 #define DW_IC_COMP_TYPE_VALUE 0x44570140 58 59 #define DW_IC_CON_MASTER 0x1 60 #define DW_IC_CON_SPEED_STD 0x2 61 #define DW_IC_CON_SPEED_FAST 0x4 62 #define DW_IC_CON_10BITADDR_MASTER 0x10 63 #define DW_IC_CON_RESTART_EN 0x20 64 #define DW_IC_CON_SLAVE_DISABLE 0x40 65 66 #define DW_IC_DATA_CMD_READ 0x100 67 #define DW_IC_DATA_CMD_STOP 0x200 68 #define DW_IC_DATA_CMD_RESTART 0x400 69 70 #define DW_IC_INTR_RX_UNDER 0x001 71 #define DW_IC_INTR_RX_OVER 0x002 72 #define DW_IC_INTR_RX_FULL 0x004 73 #define DW_IC_INTR_TX_OVER 0x008 74 #define DW_IC_INTR_TX_EMPTY 0x010 75 #define DW_IC_INTR_RD_REQ 0x020 76 #define DW_IC_INTR_TX_ABRT 0x040 77 #define DW_IC_INTR_RX_DONE 0x080 78 #define DW_IC_INTR_ACTIVITY 0x100 79 #define DW_IC_INTR_STOP_DET 0x200 80 #define DW_IC_INTR_START_DET 0x400 81 #define DW_IC_INTR_GEN_CALL 0x800 82 83 #define DW_IC_STATUS_ACTIVITY 0x1 84 85 /* hardware abort codes from the DW_IC_TX_ABRT_SOURCE register */ 86 #define ABRT_7B_ADDR_NOACK 0 87 #define ABRT_10ADDR1_NOACK 1 88 #define ABRT_10ADDR2_NOACK 2 89 #define ABRT_TXDATA_NOACK 3 90 #define ABRT_GCALL_NOACK 4 91 #define ABRT_GCALL_READ 5 92 #define ABRT_SBYTE_ACKDET 7 93 #define ABRT_SBYTE_NORSTRT 9 94 #define ABRT_10B_RD_NORSTRT 10 95 #define ABRT_MASTER_DIS 11 96 #define ARB_LOST 12 97