1 /* $OpenBSD: eephy.c,v 1.66 2024/06/26 01:40:49 jsg Exp $ */
2 /*
3 * Principal Author: Parag Patel
4 * Copyright (c) 2001
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * Additional Copyright (c) 2001 by Traakan Software under same licence.
30 * Secondary Author: Matthew Jacob
31 */
32
33 /*
34 * driver for the Marvell 88E1000 series external 1000/100/10-BT PHY.
35 */
36
37 /*
38 * Support added for the Marvell 88E1011 (Alaska) 1000/100/10baseTX and
39 * 1000baseSX PHY.
40 * Nathan Binkert <nate@openbsd.org>
41 */
42
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/device.h>
46 #include <sys/socket.h>
47
48 #include <net/if.h>
49 #include <net/if_var.h>
50 #include <net/if_media.h>
51
52 #include <dev/mii/mii.h>
53 #include <dev/mii/miivar.h>
54 #include <dev/mii/miidevs.h>
55
56 #include <dev/mii/eephyreg.h>
57
58 #ifdef __HAVE_FDT
59 #include <machine/fdt.h>
60 #include <dev/ofw/openfirm.h>
61 #endif
62
63 int eephy_match(struct device *, void *, void *);
64 void eephy_attach(struct device *, struct device *, void *);
65
66 const struct cfattach eephy_ca = {
67 sizeof (struct mii_softc), eephy_match, eephy_attach, mii_phy_detach
68 };
69
70 struct cfdriver eephy_cd = {
71 NULL, "eephy", DV_DULL
72 };
73
74 int eephy_service(struct mii_softc *, struct mii_data *, int);
75 void eephy_status(struct mii_softc *);
76 void eephy_reset(struct mii_softc *);
77
78 #ifdef __HAVE_FDT
79 void eephy_fdt_reg_init(struct mii_softc *);
80 #endif
81
82 const struct mii_phy_funcs eephy_funcs = {
83 eephy_service, eephy_status, eephy_reset,
84 };
85
86 static const struct mii_phydesc eephys[] = {
87 { MII_OUI_MARVELL, MII_MODEL_MARVELL_E1000_1,
88 MII_STR_MARVELL_E1000_1 },
89 { MII_OUI_MARVELL, MII_MODEL_MARVELL_E1000_2,
90 MII_STR_MARVELL_E1000_2 },
91 { MII_OUI_MARVELL, MII_MODEL_MARVELL_E1000_3,
92 MII_STR_MARVELL_E1000_3 },
93 { MII_OUI_MARVELL, MII_MODEL_MARVELL_E1000_4,
94 MII_STR_MARVELL_E1000_4 },
95 { MII_OUI_MARVELL, MII_MODEL_MARVELL_E1000S,
96 MII_STR_MARVELL_E1000S },
97 { MII_OUI_MARVELL, MII_MODEL_MARVELL_E1011,
98 MII_STR_MARVELL_E1011 },
99 { MII_OUI_MARVELL, MII_MODEL_MARVELL_E1111,
100 MII_STR_MARVELL_E1111 },
101 { MII_OUI_MARVELL, MII_MODEL_MARVELL_E1112,
102 MII_STR_MARVELL_E1112 },
103 { MII_OUI_MARVELL, MII_MODEL_MARVELL_E1116,
104 MII_STR_MARVELL_E1116 },
105 { MII_OUI_MARVELL, MII_MODEL_MARVELL_E1116R,
106 MII_STR_MARVELL_E1116R },
107 { MII_OUI_MARVELL, MII_MODEL_MARVELL_E1118,
108 MII_STR_MARVELL_E1118 },
109 { MII_OUI_MARVELL, MII_MODEL_MARVELL_E1149,
110 MII_STR_MARVELL_E1149 },
111 { MII_OUI_MARVELL, MII_MODEL_MARVELL_E1512,
112 MII_STR_MARVELL_E1512 },
113 { MII_OUI_MARVELL, MII_MODEL_MARVELL_E1545,
114 MII_STR_MARVELL_E1545 },
115 { MII_OUI_MARVELL, MII_MODEL_MARVELL_E3016,
116 MII_STR_MARVELL_E3016},
117 { MII_OUI_MARVELL, MII_MODEL_MARVELL_E3082,
118 MII_STR_MARVELL_E3082 },
119 { MII_OUI_MARVELL, MII_MODEL_MARVELL_PHYG65G,
120 MII_STR_MARVELL_PHYG65G },
121 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1000_5,
122 MII_STR_xxMARVELL_E1000_5 },
123 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1000_6,
124 MII_STR_xxMARVELL_E1000_6 },
125 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1000_7,
126 MII_STR_xxMARVELL_E1000_7 },
127 { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1111,
128 MII_STR_xxMARVELL_E1111 },
129
130 { 0, 0,
131 NULL },
132 };
133
134 int
eephy_match(struct device * parent,void * match,void * aux)135 eephy_match(struct device *parent, void *match, void *aux)
136 {
137 struct mii_attach_args *ma = aux;
138
139 if (mii_phy_match(ma, eephys) != NULL)
140 return (10);
141
142 return (0);
143 }
144
145 void
eephy_attach(struct device * parent,struct device * self,void * aux)146 eephy_attach(struct device *parent, struct device *self, void *aux)
147 {
148 struct mii_softc *sc = (struct mii_softc *)self;
149 struct mii_attach_args *ma = aux;
150 struct mii_data *mii = ma->mii_data;
151 const struct mii_phydesc *mpd;
152 int reg, page;
153
154 mpd = mii_phy_match(ma, eephys);
155 printf(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
156
157 sc->mii_inst = mii->mii_instance;
158 sc->mii_phy = ma->mii_phyno;
159 sc->mii_funcs = &eephy_funcs;
160 sc->mii_model = MII_MODEL(ma->mii_id2);
161 sc->mii_pdata = mii;
162 sc->mii_flags = ma->mii_flags;
163
164 /* XXX No loopback support yet, although the hardware can do it. */
165 sc->mii_flags |= MIIF_NOLOOP;
166
167 /* Make sure page 0 is selected. */
168 PHY_WRITE(sc, E1000_EADR, 0);
169
170 /* Switch to copper-only mode if necessary. */
171 if (sc->mii_model == MII_MODEL_MARVELL_E1111 &&
172 (sc->mii_flags & MIIF_HAVEFIBER) == 0) {
173 /*
174 * The onboard 88E1111 PHYs on the Sun X4100 M2 come
175 * up with fiber/copper auto-selection enabled, even
176 * though the machine only has copper ports. This
177 * makes the chip autoselect to 1000baseX, and makes
178 * it impossible to select any other media. So
179 * disable fiber/copper autoselection.
180 */
181 reg = PHY_READ(sc, E1000_ESSR);
182 if ((reg & E1000_ESSR_HWCFG_MODE) == E1000_ESSR_RGMII_COPPER) {
183 reg |= E1000_ESSR_DIS_FC;
184 PHY_WRITE(sc, E1000_ESSR, reg);
185 }
186 }
187
188 /* Switch to fiber-only mode if necessary. */
189 if (sc->mii_model == MII_MODEL_MARVELL_E1112 &&
190 sc->mii_flags & MIIF_HAVEFIBER) {
191 page = PHY_READ(sc, E1000_EADR);
192 PHY_WRITE(sc, E1000_EADR, 2);
193 reg = PHY_READ(sc, E1000_SCR);
194 reg &= ~E1000_SCR_MODE_MASK;
195 reg |= E1000_SCR_MODE_1000BX;
196 PHY_WRITE(sc, E1000_SCR, reg);
197 PHY_WRITE(sc, E1000_EADR, page);
198 }
199
200 /*
201 * GCR1 MII mode defaults to an invalid value on E1512/E1514
202 * and must be programmed with the desired mode of operation.
203 */
204 if (sc->mii_model == MII_MODEL_MARVELL_E1512) {
205 uint32_t mode;
206
207 page = PHY_READ(sc, E1000_EADR);
208 PHY_WRITE(sc, E1000_EADR, 18);
209
210 reg = PHY_READ(sc, E1000_GCR1);
211 mode = reg & E1000_GCR1_MODE_MASK;
212
213 if (mode == E1000_GCR1_MODE_UNSET)
214 mode = E1000_GCR1_MODE_RGMII;
215 if (sc->mii_flags & MIIF_SGMII)
216 mode = E1000_GCR1_MODE_SGMII;
217
218 reg &= ~E1000_GCR1_MODE_MASK;
219 reg |= E1000_GCR1_RESET | mode;
220 PHY_WRITE(sc, E1000_GCR1, reg);
221
222 PHY_WRITE(sc, E1000_EADR, page);
223 }
224
225 #ifdef __HAVE_FDT
226 eephy_fdt_reg_init(sc);
227 #endif
228
229 PHY_RESET(sc);
230
231 sc->mii_capabilities = PHY_READ(sc, E1000_SR) & ma->mii_capmask;
232 if (sc->mii_capabilities & BMSR_EXTSTAT)
233 sc->mii_extcapabilities = PHY_READ(sc, E1000_ESR);
234
235 mii_phy_add_media(sc);
236
237 }
238
239 void
eephy_reset(struct mii_softc * sc)240 eephy_reset(struct mii_softc *sc)
241 {
242 int reg, i;
243
244 reg = PHY_READ(sc, E1000_CR);
245 reg |= E1000_CR_RESET;
246 PHY_WRITE(sc, E1000_CR, reg);
247
248 for (i = 0; i < 500; i++) {
249 DELAY(1);
250 reg = PHY_READ(sc, E1000_CR);
251 if (!(reg & E1000_CR_RESET))
252 break;
253 }
254
255 /*
256 * Initialize PHY Specific Control Register.
257 */
258 reg = PHY_READ(sc, E1000_SCR);
259
260 /* Assert CRS on transmit. */
261 reg |= E1000_SCR_ASSERT_CRS_ON_TX;
262
263 /* Enable auto crossover. */
264 switch (sc->mii_model) {
265 case MII_MODEL_MARVELL_E3016:
266 case MII_MODEL_MARVELL_E3082:
267 /* Bits are in a different position. */
268 reg |= (E1000_SCR_AUTO_X_MODE >> 1);
269 break;
270 default:
271 /* Automatic crossover causes problems for 1000baseX. */
272 if (sc->mii_flags & MIIF_IS_1000X)
273 reg &= ~E1000_SCR_AUTO_X_MODE;
274 else
275 reg |= E1000_SCR_AUTO_X_MODE;
276 }
277
278 /* Disable energy detect; only available on some models. */
279 switch(sc->mii_model) {
280 case MII_MODEL_MARVELL_E3016:
281 reg &= ~E3000_SCR_EN_DETECT_MASK;
282 break;
283 case MII_MODEL_MARVELL_E1011:
284 case MII_MODEL_MARVELL_E1111:
285 case MII_MODEL_MARVELL_E1112:
286 case MII_MODEL_MARVELL_E1512:
287 case MII_MODEL_MARVELL_PHYG65G:
288 reg &= ~E1000_SCR_EN_DETECT_MASK;
289 break;
290 }
291
292 /* Enable scrambler if necessary. */
293 if (sc->mii_model == MII_MODEL_MARVELL_E3016)
294 reg &= ~E3000_SCR_SCRAMBLER_DISABLE;
295
296 /*
297 * Store next page in the Link Partner Next Page register for
298 * compatibility with 802.3ab.
299 */
300 if (sc->mii_model == MII_MODEL_MARVELL_E3016)
301 reg |= E3000_SCR_REG8_NEXT_PAGE;
302
303 PHY_WRITE(sc, E1000_SCR, reg);
304
305 if (sc->mii_model != MII_MODEL_MARVELL_E1512 &&
306 sc->mii_model != MII_MODEL_MARVELL_E1545) {
307 /* 25 MHz TX_CLK should always work. */
308 reg = PHY_READ(sc, E1000_ESCR);
309 reg |= E1000_ESCR_TX_CLK_25;
310 PHY_WRITE(sc, E1000_ESCR, reg);
311 }
312
313 /* Configure LEDs if they were left unconfigured. */
314 if (sc->mii_model == MII_MODEL_MARVELL_E3016 &&
315 PHY_READ(sc, 0x16) == 0) {
316 reg = (0x0b << 8) | (0x05 << 4) | 0x04; /* XXX */
317 PHY_WRITE(sc, 0x16, reg);
318 }
319
320 /*
321 * Do a software reset for these settings to take effect.
322 */
323 reg = PHY_READ(sc, E1000_CR);
324 PHY_WRITE(sc, E1000_CR, reg | E1000_CR_RESET);
325 }
326
327 int
eephy_service(struct mii_softc * sc,struct mii_data * mii,int cmd)328 eephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
329 {
330 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
331 int bmcr;
332
333 if ((sc->mii_dev.dv_flags & DVF_ACTIVE) == 0)
334 return (ENXIO);
335
336 switch (cmd) {
337 case MII_POLLSTAT:
338 /*
339 * If we're not polling our PHY instance, just return.
340 */
341 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
342 return (0);
343 break;
344
345 case MII_MEDIACHG:
346 /*
347 * If the media indicates a different PHY instance,
348 * isolate ourselves.
349 */
350 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
351 bmcr = PHY_READ(sc, E1000_CR);
352 PHY_WRITE(sc, E1000_CR, bmcr | E1000_CR_ISOLATE);
353 return (0);
354 }
355
356 /*
357 * If the interface is not up, don't do anything.
358 */
359 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
360 break;
361
362 mii_phy_setmedia(sc);
363
364 /*
365 * If autonegotiation is not enabled, we need a
366 * software reset for the settings to take effect.
367 */
368 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
369 bmcr = PHY_READ(sc, E1000_CR);
370 PHY_WRITE(sc, E1000_CR, bmcr | E1000_CR_RESET);
371 }
372 break;
373
374 case MII_TICK:
375 /*
376 * If we're not currently selected, just return.
377 */
378 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
379 return (0);
380
381 if (mii_phy_tick(sc) == EJUSTRETURN)
382 return (0);
383 break;
384
385 case MII_DOWN:
386 mii_phy_down(sc);
387 return (0);
388 }
389
390 /* Update the media status. */
391 mii_phy_status(sc);
392
393 /* Callback if something changed. */
394 mii_phy_update(sc, cmd);
395 return (0);
396 }
397
398 void
eephy_status(struct mii_softc * sc)399 eephy_status(struct mii_softc *sc)
400 {
401 struct mii_data *mii = sc->mii_pdata;
402 int bmcr, gsr, ssr;
403
404 mii->mii_media_status = IFM_AVALID;
405 mii->mii_media_active = IFM_ETHER;
406
407 bmcr = PHY_READ(sc, E1000_CR);
408 ssr = PHY_READ(sc, E1000_SSR);
409
410 if (ssr & E1000_SSR_LINK)
411 mii->mii_media_status |= IFM_ACTIVE;
412
413 if (bmcr & E1000_CR_LOOPBACK)
414 mii->mii_media_active |= IFM_LOOP;
415
416 if (!(ssr & E1000_SSR_SPD_DPLX_RESOLVED)) {
417 /* Erg, still trying, I guess... */
418 mii->mii_media_active |= IFM_NONE;
419 return;
420 }
421
422 if (sc->mii_flags & MIIF_IS_1000X) {
423 mii->mii_media_active |= IFM_1000_SX;
424 } else {
425 if (ssr & E1000_SSR_1000MBS)
426 mii->mii_media_active |= IFM_1000_T;
427 else if (ssr & E1000_SSR_100MBS)
428 mii->mii_media_active |= IFM_100_TX;
429 else
430 mii->mii_media_active |= IFM_10_T;
431 }
432
433 if (ssr & E1000_SSR_DUPLEX)
434 mii->mii_media_active |= mii_phy_flowstatus(sc) | IFM_FDX;
435 else
436 mii->mii_media_active |= IFM_HDX;
437
438 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
439 gsr = PHY_READ(sc, E1000_1GSR) | PHY_READ(sc, E1000_1GSR);
440 if (gsr & E1000_1GSR_MS_CONFIG_RES)
441 mii->mii_media_active |= IFM_ETH_MASTER;
442 }
443 }
444
445 #ifdef __HAVE_FDT
446 void
eephy_fdt_reg_init(struct mii_softc * sc)447 eephy_fdt_reg_init(struct mii_softc *sc)
448 {
449 uint32_t *prop, opage;
450 int i, len;
451
452 if (!sc->mii_pdata->mii_node)
453 return;
454
455 len = OF_getproplen(sc->mii_pdata->mii_node, "marvell,reg-init");
456 if (len <= 0 || len % (4 * sizeof(uint32_t)) != 0)
457 return;
458
459 opage = PHY_READ(sc, E1000_EADR);
460 prop = malloc(len, M_TEMP, M_WAITOK);
461 OF_getpropintarray(sc->mii_pdata->mii_node, "marvell,reg-init",
462 prop, len);
463 for (i = 0; i < len; i += 4) {
464 uint32_t page = prop[i + 0];
465 uint32_t reg = prop[i + 1];
466 uint32_t keep = prop[i + 2];
467 uint32_t set = prop[i + 3];
468 uint32_t val = 0;
469
470 PHY_WRITE(sc, E1000_EADR, page);
471 if (keep) {
472 val = PHY_READ(sc, reg);
473 val &= keep;
474 }
475 val |= set;
476 PHY_WRITE(sc, reg, val);
477 }
478 free(prop, M_TEMP, len);
479 PHY_WRITE(sc, E1000_EADR, opage);
480 }
481 #endif
482