1 /* $OpenBSD: rgephy.c,v 1.43 2023/04/05 10:45:07 kettenis Exp $ */
2 /*
3 * Copyright (c) 2003
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * $FreeBSD: rgephy.c,v 1.5 2004/05/30 17:57:40 phk Exp $
34 */
35
36 /*
37 * Driver for the Realtek 8169S/8110S internal 10/100/1000 PHY.
38 */
39
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/device.h>
44 #include <sys/socket.h>
45 #include <sys/errno.h>
46
47 #include <machine/bus.h>
48
49 #include <net/if.h>
50 #include <net/if_media.h>
51
52 #include <netinet/in.h>
53 #include <netinet/if_ether.h>
54
55 #include <dev/mii/mii.h>
56 #include <dev/mii/miivar.h>
57 #include <dev/mii/miidevs.h>
58
59 #include <dev/mii/rgephyreg.h>
60
61 #include <dev/ic/rtl81x9reg.h>
62
63 int rgephymatch(struct device *, void *, void *);
64 void rgephyattach(struct device *, struct device *, void *);
65
66 const struct cfattach rgephy_ca = { sizeof(struct mii_softc),
67 rgephymatch, rgephyattach, mii_phy_detach,
68 };
69
70 struct cfdriver rgephy_cd = {
71 NULL, "rgephy", DV_DULL
72 };
73
74 int rgephy_service(struct mii_softc *, struct mii_data *, int);
75 void rgephy_status(struct mii_softc *);
76 int rgephy_mii_phy_auto(struct mii_softc *);
77 void rgephy_reset(struct mii_softc *);
78 void rgephy_loop(struct mii_softc *);
79 void rgephy_init_rtl8211f(struct mii_softc *);
80 void rgephy_load_dspcode(struct mii_softc *);
81
82 const struct mii_phy_funcs rgephy_funcs = {
83 rgephy_service, rgephy_status, rgephy_reset,
84 };
85
86 static const struct mii_phydesc rgephys[] = {
87 { MII_OUI_REALTEK2, MII_MODEL_xxREALTEK_RTL8169S,
88 MII_STR_xxREALTEK_RTL8169S },
89 { MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8169S,
90 MII_STR_xxREALTEK_RTL8169S },
91 { MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8251,
92 MII_STR_xxREALTEK_RTL8251 },
93 { MII_OUI_xxREALTEK, MII_MODEL_xxREALTEK_RTL8211FVD,
94 MII_STR_xxREALTEK_RTL8211FVD },
95
96 { 0, 0,
97 NULL },
98 };
99
100 int
rgephymatch(struct device * parent,void * match,void * aux)101 rgephymatch(struct device *parent, void *match, void *aux)
102 {
103 struct mii_attach_args *ma = aux;
104
105 if (mii_phy_match(ma, rgephys) != NULL)
106 return (10);
107
108 return (0);
109 }
110
111 void
rgephyattach(struct device * parent,struct device * self,void * aux)112 rgephyattach(struct device *parent, struct device *self, void *aux)
113 {
114 struct mii_softc *sc = (struct mii_softc *)self;
115 struct mii_attach_args *ma = aux;
116 struct mii_data *mii = ma->mii_data;
117 const struct mii_phydesc *mpd;
118
119 mpd = mii_phy_match(ma, rgephys);
120 printf(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
121
122 sc->mii_inst = mii->mii_instance;
123 sc->mii_phy = ma->mii_phyno;
124 sc->mii_funcs = &rgephy_funcs;
125 sc->mii_model = MII_MODEL(ma->mii_id2);
126 sc->mii_rev = MII_REV(ma->mii_id2);
127 sc->mii_pdata = mii;
128 sc->mii_flags = ma->mii_flags;
129 sc->mii_anegticks = MII_ANEGTICKS_GIGE;
130
131 sc->mii_flags |= MIIF_NOISOLATE;
132
133 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
134
135 if (sc->mii_capabilities & BMSR_EXTSTAT)
136 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
137 if ((sc->mii_capabilities & BMSR_MEDIAMASK) ||
138 (sc->mii_extcapabilities & EXTSR_MEDIAMASK))
139 mii_phy_add_media(sc);
140
141 if (sc->mii_model == MII_MODEL_xxREALTEK_RTL8211FVD ||
142 (sc->mii_model == MII_MODEL_xxREALTEK_RTL8169S &&
143 sc->mii_rev == RGEPHY_8211F))
144 rgephy_init_rtl8211f(sc);
145
146 PHY_RESET(sc);
147 }
148
149 int
rgephy_service(struct mii_softc * sc,struct mii_data * mii,int cmd)150 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
151 {
152 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
153 int anar, reg, speed, gig = 0;
154 char *devname;
155
156 devname = sc->mii_dev.dv_parent->dv_cfdata->cf_driver->cd_name;
157
158 switch (cmd) {
159 case MII_POLLSTAT:
160 /*
161 * If we're not polling our PHY instance, just return.
162 */
163 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
164 return (0);
165 break;
166
167 case MII_MEDIACHG:
168 /*
169 * If the media indicates a different PHY instance,
170 * isolate ourselves.
171 */
172 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
173 reg = PHY_READ(sc, MII_BMCR);
174 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
175 return (0);
176 }
177
178 /*
179 * If the interface is not up, don't do anything.
180 */
181 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
182 break;
183
184 PHY_RESET(sc); /* XXX hardware bug work-around */
185
186 anar = PHY_READ(sc, MII_ANAR);
187 anar &= ~(ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10);
188
189 switch (IFM_SUBTYPE(ife->ifm_media)) {
190 case IFM_AUTO:
191 (void) rgephy_mii_phy_auto(sc);
192 break;
193 case IFM_1000_T:
194 speed = BMCR_S1000;
195 goto setit;
196 case IFM_100_TX:
197 speed = BMCR_S100;
198 anar |= ANAR_TX_FD | ANAR_TX;
199 goto setit;
200 case IFM_10_T:
201 speed = BMCR_S10;
202 anar |= ANAR_10_FD | ANAR_10;
203 setit:
204 rgephy_loop(sc);
205 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
206 speed |= BMCR_FDX;
207 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T)
208 gig = GTCR_ADV_1000TFDX;
209 anar &= ~(ANAR_TX | ANAR_10);
210 } else {
211 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T)
212 gig = GTCR_ADV_1000THDX;
213 anar &=
214 ~(ANAR_TX_FD | ANAR_10_FD);
215 }
216
217 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T &&
218 mii->mii_media.ifm_media & IFM_ETH_MASTER)
219 gig |= GTCR_MAN_MS|GTCR_ADV_MS;
220
221 PHY_WRITE(sc, MII_100T2CR, gig);
222 PHY_WRITE(sc, MII_BMCR, speed | BMCR_AUTOEN |
223 BMCR_STARTNEG);
224 PHY_WRITE(sc, MII_ANAR, anar);
225 break;
226 #if 0
227 case IFM_NONE:
228 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
229 break;
230 #endif
231 default:
232 return (EINVAL);
233 }
234 break;
235
236 case MII_TICK:
237 /*
238 * If we're not currently selected, just return.
239 */
240 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
241 return (0);
242
243 /*
244 * Is the interface even up?
245 */
246 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
247 return (0);
248
249 /*
250 * Only used for autonegotiation.
251 */
252 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
253 break;
254
255 /*
256 * Check to see if we have link. If we do, we don't
257 * need to restart the autonegotiation process. Read
258 * the BMSR twice in case it's latched.
259 */
260 if (strcmp(devname, "re") == 0 || strcmp(devname, "ure") == 0) {
261 reg = PHY_READ(sc, RL_GMEDIASTAT);
262 if (reg & RL_GMEDIASTAT_LINK) {
263 sc->mii_ticks = 0;
264 break;
265 }
266 } else if (sc->mii_model == MII_MODEL_xxREALTEK_RTL8211FVD ||
267 (sc->mii_model == MII_MODEL_xxREALTEK_RTL8169S &&
268 sc->mii_rev == RGEPHY_8211F)) {
269 reg = PHY_READ(sc, RGEPHY_F_SR);
270 if (reg & RGEPHY_F_SR_LINK) {
271 sc->mii_ticks = 0;
272 }
273 } else {
274 reg = PHY_READ(sc, RGEPHY_SR);
275 if (reg & RGEPHY_SR_LINK) {
276 sc->mii_ticks = 0;
277 break;
278 }
279 }
280
281 /*
282 * Only retry autonegotiation every mii_anegticks seconds.
283 */
284 if (++sc->mii_ticks <= sc->mii_anegticks)
285 break;
286
287 sc->mii_ticks = 0;
288 rgephy_mii_phy_auto(sc);
289 break;
290 }
291
292 /* Update the media status. */
293 mii_phy_status(sc);
294
295 /*
296 * Callback if something changed. Note that we need to poke
297 * the DSP on the Realtek PHYs if the media changes.
298 *
299 */
300 if (sc->mii_media_active != mii->mii_media_active ||
301 sc->mii_media_status != mii->mii_media_status ||
302 cmd == MII_MEDIACHG)
303 rgephy_load_dspcode(sc);
304
305 /* Callback if something changed. */
306 mii_phy_update(sc, cmd);
307
308 return (0);
309 }
310
311 void
rgephy_status(struct mii_softc * sc)312 rgephy_status(struct mii_softc *sc)
313 {
314 struct mii_data *mii = sc->mii_pdata;
315 int bmsr, bmcr, gtsr;
316 char *devname;
317
318 devname = sc->mii_dev.dv_parent->dv_cfdata->cf_driver->cd_name;
319
320 mii->mii_media_status = IFM_AVALID;
321 mii->mii_media_active = IFM_ETHER;
322
323 if (strcmp(devname, "re") == 0 || strcmp(devname, "ure") == 0) {
324 bmsr = PHY_READ(sc, RL_GMEDIASTAT);
325 if (bmsr & RL_GMEDIASTAT_LINK)
326 mii->mii_media_status |= IFM_ACTIVE;
327 } else if (sc->mii_model == MII_MODEL_xxREALTEK_RTL8211FVD ||
328 (sc->mii_model == MII_MODEL_xxREALTEK_RTL8169S &&
329 sc->mii_rev == RGEPHY_8211F)) {
330 bmsr = PHY_READ(sc, RGEPHY_F_SR);
331 if (bmsr & RGEPHY_F_SR_LINK)
332 mii->mii_media_status |= IFM_ACTIVE;
333 } else {
334 bmsr = PHY_READ(sc, RGEPHY_SR);
335 if (bmsr & RGEPHY_SR_LINK)
336 mii->mii_media_status |= IFM_ACTIVE;
337 }
338
339 bmsr = PHY_READ(sc, MII_BMSR);
340
341 bmcr = PHY_READ(sc, MII_BMCR);
342
343 if (bmcr & BMCR_LOOP)
344 mii->mii_media_active |= IFM_LOOP;
345
346 if (bmcr & BMCR_AUTOEN) {
347 if ((bmsr & BMSR_ACOMP) == 0) {
348 /* Erg, still trying, I guess... */
349 mii->mii_media_active |= IFM_NONE;
350 return;
351 }
352 }
353
354 if (strcmp(devname, "re") == 0 || strcmp(devname, "ure") == 0) {
355 bmsr = PHY_READ(sc, RL_GMEDIASTAT);
356 if (bmsr & RL_GMEDIASTAT_1000MBPS)
357 mii->mii_media_active |= IFM_1000_T;
358 else if (bmsr & RL_GMEDIASTAT_100MBPS)
359 mii->mii_media_active |= IFM_100_TX;
360 else if (bmsr & RL_GMEDIASTAT_10MBPS)
361 mii->mii_media_active |= IFM_10_T;
362
363 if (bmsr & RL_GMEDIASTAT_FDX)
364 mii->mii_media_active |= mii_phy_flowstatus(sc) |
365 IFM_FDX;
366 else
367 mii->mii_media_active |= IFM_HDX;
368 } else if (sc->mii_model == MII_MODEL_xxREALTEK_RTL8211FVD ||
369 (sc->mii_model == MII_MODEL_xxREALTEK_RTL8169S &&
370 sc->mii_rev == RGEPHY_8211F)) {
371 bmsr = PHY_READ(sc, RGEPHY_F_SR);
372 if (RGEPHY_F_SR_SPEED(bmsr) == RGEPHY_F_SR_SPEED_1000MBPS)
373 mii->mii_media_active |= IFM_1000_T;
374 else if (RGEPHY_F_SR_SPEED(bmsr) == RGEPHY_F_SR_SPEED_100MBPS)
375 mii->mii_media_active |= IFM_100_TX;
376 else if (RGEPHY_F_SR_SPEED(bmsr) == RGEPHY_F_SR_SPEED_10MBPS)
377 mii->mii_media_active |= IFM_10_T;
378
379 if (bmsr & RGEPHY_F_SR_FDX)
380 mii->mii_media_active |= mii_phy_flowstatus(sc) |
381 IFM_FDX;
382 else
383 mii->mii_media_active |= IFM_HDX;
384 } else {
385 bmsr = PHY_READ(sc, RGEPHY_SR);
386 if (RGEPHY_SR_SPEED(bmsr) == RGEPHY_SR_SPEED_1000MBPS)
387 mii->mii_media_active |= IFM_1000_T;
388 else if (RGEPHY_SR_SPEED(bmsr) == RGEPHY_SR_SPEED_100MBPS)
389 mii->mii_media_active |= IFM_100_TX;
390 else if (RGEPHY_SR_SPEED(bmsr) == RGEPHY_SR_SPEED_10MBPS)
391 mii->mii_media_active |= IFM_10_T;
392
393 if (bmsr & RGEPHY_SR_FDX)
394 mii->mii_media_active |= mii_phy_flowstatus(sc) |
395 IFM_FDX;
396 else
397 mii->mii_media_active |= IFM_HDX;
398 }
399
400 gtsr = PHY_READ(sc, MII_100T2SR);
401 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) &&
402 gtsr & GTSR_MS_RES)
403 mii->mii_media_active |= IFM_ETH_MASTER;
404 }
405
406
407 int
rgephy_mii_phy_auto(struct mii_softc * sc)408 rgephy_mii_phy_auto(struct mii_softc *sc)
409 {
410 int anar;
411
412 rgephy_loop(sc);
413 PHY_RESET(sc);
414
415 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
416 if (sc->mii_flags & MIIF_DOPAUSE)
417 anar |= ANAR_FC | ANAR_X_PAUSE_ASYM;
418
419 PHY_WRITE(sc, MII_ANAR, anar);
420 DELAY(1000);
421 PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000THDX | GTCR_ADV_1000TFDX);
422 DELAY(1000);
423 PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
424 DELAY(100);
425
426 return (EJUSTRETURN);
427 }
428
429 void
rgephy_loop(struct mii_softc * sc)430 rgephy_loop(struct mii_softc *sc)
431 {
432 u_int32_t bmsr;
433 int i;
434
435 if (sc->mii_model == MII_MODEL_xxREALTEK_RTL8169S &&
436 sc->mii_rev < 2) {
437 PHY_WRITE(sc, MII_BMCR, BMCR_PDOWN);
438 DELAY(1000);
439 }
440
441 for (i = 0; i < 15000; i++) {
442 bmsr = PHY_READ(sc, MII_BMSR);
443 if (!(bmsr & BMSR_LINK))
444 break;
445 DELAY(10);
446 }
447 }
448
449 void
rgephy_init_rtl8211f(struct mii_softc * sc)450 rgephy_init_rtl8211f(struct mii_softc *sc)
451 {
452 if (sc->mii_flags & MIIF_SETDELAY) {
453 int page, val;
454
455 /* save page */
456 page = PHY_READ(sc, RGEPHY_PS);
457 PHY_WRITE(sc, RGEPHY_PS, RGEPHY_PS_PAGE_MII);
458
459 val = PHY_READ(sc, RGEPHY_MIICR1);
460 if (sc->mii_flags & MIIF_TXID)
461 val |= RGEPHY_MIICR1_TXDLY_EN;
462 else
463 val &= ~RGEPHY_MIICR1_TXDLY_EN;
464 PHY_WRITE(sc, RGEPHY_MIICR1, val);
465
466 val = PHY_READ(sc, RGEPHY_MIICR2);
467 if (sc->mii_flags & MIIF_RXID)
468 val |= RGEPHY_MIICR2_RXDLY_EN;
469 else
470 val &= ~RGEPHY_MIICR2_RXDLY_EN;
471 PHY_WRITE(sc, RGEPHY_MIICR2, val);
472
473 /* restore page */
474 PHY_WRITE(sc, RGEPHY_PS, page);
475 }
476 }
477
478 #define PHY_SETBIT(x, y, z) \
479 PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
480 #define PHY_CLRBIT(x, y, z) \
481 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
482
483 /*
484 * Initialize Realtek PHY per the datasheet. The DSP in the PHYs of
485 * existing revisions of the 8169S/8110S chips need to be tuned in
486 * order to reliably negotiate a 1000Mbps link. This is only needed
487 * for rev 0 and rev 1 of the PHY. Later versions work without
488 * any fixups.
489 */
490 void
rgephy_load_dspcode(struct mii_softc * sc)491 rgephy_load_dspcode(struct mii_softc *sc)
492 {
493 int val;
494
495 if (sc->mii_model != MII_MODEL_xxREALTEK_RTL8169S ||
496 sc->mii_rev > 1)
497 return;
498
499 PHY_WRITE(sc, 31, 0x0001);
500 PHY_WRITE(sc, 21, 0x1000);
501 PHY_WRITE(sc, 24, 0x65C7);
502 PHY_CLRBIT(sc, 4, 0x0800);
503 val = PHY_READ(sc, 4) & 0xFFF;
504 PHY_WRITE(sc, 4, val);
505 PHY_WRITE(sc, 3, 0x00A1);
506 PHY_WRITE(sc, 2, 0x0008);
507 PHY_WRITE(sc, 1, 0x1020);
508 PHY_WRITE(sc, 0, 0x1000);
509 PHY_SETBIT(sc, 4, 0x0800);
510 PHY_CLRBIT(sc, 4, 0x0800);
511 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000;
512 PHY_WRITE(sc, 4, val);
513 PHY_WRITE(sc, 3, 0xFF41);
514 PHY_WRITE(sc, 2, 0xDE60);
515 PHY_WRITE(sc, 1, 0x0140);
516 PHY_WRITE(sc, 0, 0x0077);
517 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000;
518 PHY_WRITE(sc, 4, val);
519 PHY_WRITE(sc, 3, 0xDF01);
520 PHY_WRITE(sc, 2, 0xDF20);
521 PHY_WRITE(sc, 1, 0xFF95);
522 PHY_WRITE(sc, 0, 0xFA00);
523 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000;
524 PHY_WRITE(sc, 4, val);
525 PHY_WRITE(sc, 3, 0xFF41);
526 PHY_WRITE(sc, 2, 0xDE20);
527 PHY_WRITE(sc, 1, 0x0140);
528 PHY_WRITE(sc, 0, 0x00BB);
529 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000;
530 PHY_WRITE(sc, 4, val);
531 PHY_WRITE(sc, 3, 0xDF01);
532 PHY_WRITE(sc, 2, 0xDF20);
533 PHY_WRITE(sc, 1, 0xFF95);
534 PHY_WRITE(sc, 0, 0xBF00);
535 PHY_SETBIT(sc, 4, 0x0800);
536 PHY_CLRBIT(sc, 4, 0x0800);
537 PHY_WRITE(sc, 31, 0x0000);
538
539 DELAY(40);
540 }
541
542 void
rgephy_reset(struct mii_softc * sc)543 rgephy_reset(struct mii_softc *sc)
544 {
545 mii_phy_reset(sc);
546 DELAY(1000);
547 rgephy_load_dspcode(sc);
548 }
549