1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2023 Intel Corporation
4  */
5 
6 #include <drm/i915_pciids.h>
7 #include <drm/drm_color_mgmt.h>
8 #include <linux/pci.h>
9 
10 #include "i915_drv.h"
11 #include "i915_reg.h"
12 #include "intel_de.h"
13 #include "intel_display.h"
14 #include "intel_display_device.h"
15 #include "intel_display_power.h"
16 #include "intel_display_reg_defs.h"
17 #include "intel_fbc.h"
18 
19 static const struct intel_display_device_info no_display = {};
20 
21 #define PIPE_A_OFFSET		0x70000
22 #define PIPE_B_OFFSET		0x71000
23 #define PIPE_C_OFFSET		0x72000
24 #define PIPE_D_OFFSET		0x73000
25 #define CHV_PIPE_C_OFFSET	0x74000
26 /*
27  * There's actually no pipe EDP. Some pipe registers have
28  * simply shifted from the pipe to the transcoder, while
29  * keeping their original offset. Thus we need PIPE_EDP_OFFSET
30  * to access such registers in transcoder EDP.
31  */
32 #define PIPE_EDP_OFFSET	0x7f000
33 
34 /* ICL DSI 0 and 1 */
35 #define PIPE_DSI0_OFFSET	0x7b000
36 #define PIPE_DSI1_OFFSET	0x7b800
37 
38 #define TRANSCODER_A_OFFSET 0x60000
39 #define TRANSCODER_B_OFFSET 0x61000
40 #define TRANSCODER_C_OFFSET 0x62000
41 #define CHV_TRANSCODER_C_OFFSET 0x63000
42 #define TRANSCODER_D_OFFSET 0x63000
43 #define TRANSCODER_EDP_OFFSET 0x6f000
44 #define TRANSCODER_DSI0_OFFSET	0x6b000
45 #define TRANSCODER_DSI1_OFFSET	0x6b800
46 
47 #define CURSOR_A_OFFSET 0x70080
48 #define CURSOR_B_OFFSET 0x700c0
49 #define CHV_CURSOR_C_OFFSET 0x700e0
50 #define IVB_CURSOR_B_OFFSET 0x71080
51 #define IVB_CURSOR_C_OFFSET 0x72080
52 #define TGL_CURSOR_D_OFFSET 0x73080
53 
54 #define I845_PIPE_OFFSETS \
55 	.pipe_offsets = { \
56 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
57 	}, \
58 	.trans_offsets = { \
59 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
60 	}
61 
62 #define I9XX_PIPE_OFFSETS \
63 	.pipe_offsets = { \
64 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
65 		[TRANSCODER_B] = PIPE_B_OFFSET, \
66 	}, \
67 	.trans_offsets = { \
68 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
69 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
70 	}
71 
72 #define IVB_PIPE_OFFSETS \
73 	.pipe_offsets = { \
74 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
75 		[TRANSCODER_B] = PIPE_B_OFFSET, \
76 		[TRANSCODER_C] = PIPE_C_OFFSET, \
77 	}, \
78 	.trans_offsets = { \
79 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
80 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
81 		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
82 	}
83 
84 #define HSW_PIPE_OFFSETS \
85 	.pipe_offsets = { \
86 		[TRANSCODER_A] = PIPE_A_OFFSET,	\
87 		[TRANSCODER_B] = PIPE_B_OFFSET, \
88 		[TRANSCODER_C] = PIPE_C_OFFSET, \
89 		[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
90 	}, \
91 	.trans_offsets = { \
92 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
93 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
94 		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
95 		[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
96 	}
97 
98 #define CHV_PIPE_OFFSETS \
99 	.pipe_offsets = { \
100 		[TRANSCODER_A] = PIPE_A_OFFSET, \
101 		[TRANSCODER_B] = PIPE_B_OFFSET, \
102 		[TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
103 	}, \
104 	.trans_offsets = { \
105 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
106 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
107 		[TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
108 	}
109 
110 #define I845_CURSOR_OFFSETS \
111 	.cursor_offsets = { \
112 		[PIPE_A] = CURSOR_A_OFFSET, \
113 	}
114 
115 #define I9XX_CURSOR_OFFSETS \
116 	.cursor_offsets = { \
117 		[PIPE_A] = CURSOR_A_OFFSET, \
118 		[PIPE_B] = CURSOR_B_OFFSET, \
119 	}
120 
121 #define CHV_CURSOR_OFFSETS \
122 	.cursor_offsets = { \
123 		[PIPE_A] = CURSOR_A_OFFSET, \
124 		[PIPE_B] = CURSOR_B_OFFSET, \
125 		[PIPE_C] = CHV_CURSOR_C_OFFSET, \
126 	}
127 
128 #define IVB_CURSOR_OFFSETS \
129 	.cursor_offsets = { \
130 		[PIPE_A] = CURSOR_A_OFFSET, \
131 		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
132 		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
133 	}
134 
135 #define TGL_CURSOR_OFFSETS \
136 	.cursor_offsets = { \
137 		[PIPE_A] = CURSOR_A_OFFSET, \
138 		[PIPE_B] = IVB_CURSOR_B_OFFSET, \
139 		[PIPE_C] = IVB_CURSOR_C_OFFSET, \
140 		[PIPE_D] = TGL_CURSOR_D_OFFSET, \
141 	}
142 
143 #define I845_COLORS \
144 	.color = { .gamma_lut_size = 256 }
145 #define I9XX_COLORS \
146 	.color = { .gamma_lut_size = 129, \
147 		   .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
148 	}
149 #define ILK_COLORS \
150 	.color = { .gamma_lut_size = 1024 }
151 #define IVB_COLORS \
152 	.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
153 #define CHV_COLORS \
154 	.color = { \
155 		.degamma_lut_size = 65, .gamma_lut_size = 257, \
156 		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
157 		.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
158 	}
159 #define GLK_COLORS \
160 	.color = { \
161 		.degamma_lut_size = 33, .gamma_lut_size = 1024, \
162 		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
163 				     DRM_COLOR_LUT_EQUAL_CHANNELS, \
164 	}
165 #define ICL_COLORS \
166 	.color = { \
167 		.degamma_lut_size = 33, .gamma_lut_size = 262145, \
168 		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
169 				     DRM_COLOR_LUT_EQUAL_CHANNELS, \
170 		.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
171 	}
172 
173 #define I830_DISPLAY \
174 	.has_overlay = 1, \
175 	.cursor_needs_physical = 1, \
176 	.overlay_needs_physical = 1, \
177 	.has_gmch = 1, \
178 	I9XX_PIPE_OFFSETS, \
179 	I9XX_CURSOR_OFFSETS, \
180 	I9XX_COLORS, \
181 	\
182 	.__runtime_defaults.ip.ver = 2, \
183 	.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
184 	.__runtime_defaults.cpu_transcoder_mask = \
185 		BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
186 
187 #define I845_DISPLAY \
188 	.has_overlay = 1, \
189 	.overlay_needs_physical = 1, \
190 	.has_gmch = 1, \
191 	I845_PIPE_OFFSETS, \
192 	I845_CURSOR_OFFSETS, \
193 	I845_COLORS, \
194 	\
195 	.__runtime_defaults.ip.ver = 2, \
196 	.__runtime_defaults.pipe_mask = BIT(PIPE_A), \
197 	.__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A)
198 
199 static const struct intel_display_device_info i830_display = {
200 	I830_DISPLAY,
201 
202 	.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C), /* DVO A/B/C */
203 };
204 
205 static const struct intel_display_device_info i845_display = {
206 	I845_DISPLAY,
207 
208 	.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
209 };
210 
211 static const struct intel_display_device_info i85x_display = {
212 	I830_DISPLAY,
213 
214 	.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
215 	.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
216 };
217 
218 static const struct intel_display_device_info i865g_display = {
219 	I845_DISPLAY,
220 
221 	.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
222 	.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
223 };
224 
225 #define GEN3_DISPLAY \
226 	.has_gmch = 1, \
227 	.has_overlay = 1, \
228 	I9XX_PIPE_OFFSETS, \
229 	I9XX_CURSOR_OFFSETS, \
230 	\
231 	.__runtime_defaults.ip.ver = 3, \
232 	.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
233 	.__runtime_defaults.cpu_transcoder_mask = \
234 		BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
235 	.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) /* SDVO B/C */
236 
237 static const struct intel_display_device_info i915g_display = {
238 	GEN3_DISPLAY,
239 	I845_COLORS,
240 	.cursor_needs_physical = 1,
241 	.overlay_needs_physical = 1,
242 };
243 
244 static const struct intel_display_device_info i915gm_display = {
245 	GEN3_DISPLAY,
246 	I9XX_COLORS,
247 	.cursor_needs_physical = 1,
248 	.overlay_needs_physical = 1,
249 	.supports_tv = 1,
250 
251 	.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
252 };
253 
254 static const struct intel_display_device_info i945g_display = {
255 	GEN3_DISPLAY,
256 	I845_COLORS,
257 	.has_hotplug = 1,
258 	.cursor_needs_physical = 1,
259 	.overlay_needs_physical = 1,
260 };
261 
262 static const struct intel_display_device_info i945gm_display = {
263 	GEN3_DISPLAY,
264 	I9XX_COLORS,
265 	.has_hotplug = 1,
266 	.cursor_needs_physical = 1,
267 	.overlay_needs_physical = 1,
268 	.supports_tv = 1,
269 
270 	.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
271 };
272 
273 static const struct intel_display_device_info g33_display = {
274 	GEN3_DISPLAY,
275 	I845_COLORS,
276 	.has_hotplug = 1,
277 };
278 
279 static const struct intel_display_device_info pnv_display = {
280 	GEN3_DISPLAY,
281 	I9XX_COLORS,
282 	.has_hotplug = 1,
283 };
284 
285 #define GEN4_DISPLAY \
286 	.has_hotplug = 1, \
287 	.has_gmch = 1, \
288 	I9XX_PIPE_OFFSETS, \
289 	I9XX_CURSOR_OFFSETS, \
290 	I9XX_COLORS, \
291 	\
292 	.__runtime_defaults.ip.ver = 4, \
293 	.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
294 	.__runtime_defaults.cpu_transcoder_mask = \
295 		BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
296 
297 static const struct intel_display_device_info i965g_display = {
298 	GEN4_DISPLAY,
299 	.has_overlay = 1,
300 
301 	.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */
302 };
303 
304 static const struct intel_display_device_info i965gm_display = {
305 	GEN4_DISPLAY,
306 	.has_overlay = 1,
307 	.supports_tv = 1,
308 
309 	.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */
310 	.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
311 };
312 
313 static const struct intel_display_device_info g45_display = {
314 	GEN4_DISPLAY,
315 
316 	.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */
317 };
318 
319 static const struct intel_display_device_info gm45_display = {
320 	GEN4_DISPLAY,
321 	.supports_tv = 1,
322 
323 	.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */
324 	.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
325 };
326 
327 #define ILK_DISPLAY \
328 	.has_hotplug = 1, \
329 	I9XX_PIPE_OFFSETS, \
330 	I9XX_CURSOR_OFFSETS, \
331 	ILK_COLORS, \
332 	\
333 	.__runtime_defaults.ip.ver = 5, \
334 	.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
335 	.__runtime_defaults.cpu_transcoder_mask = \
336 		BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
337 	.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */
338 
339 static const struct intel_display_device_info ilk_d_display = {
340 	ILK_DISPLAY,
341 };
342 
343 static const struct intel_display_device_info ilk_m_display = {
344 	ILK_DISPLAY,
345 
346 	.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
347 };
348 
349 static const struct intel_display_device_info snb_display = {
350 	.has_hotplug = 1,
351 	I9XX_PIPE_OFFSETS,
352 	I9XX_CURSOR_OFFSETS,
353 	ILK_COLORS,
354 
355 	.__runtime_defaults.ip.ver = 6,
356 	.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
357 	.__runtime_defaults.cpu_transcoder_mask =
358 		BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
359 	.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */
360 	.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
361 };
362 
363 static const struct intel_display_device_info ivb_display = {
364 	.has_hotplug = 1,
365 	IVB_PIPE_OFFSETS,
366 	IVB_CURSOR_OFFSETS,
367 	IVB_COLORS,
368 
369 	.__runtime_defaults.ip.ver = 7,
370 	.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
371 	.__runtime_defaults.cpu_transcoder_mask =
372 		BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
373 	.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */
374 	.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
375 };
376 
377 static const struct intel_display_device_info vlv_display = {
378 	.has_gmch = 1,
379 	.has_hotplug = 1,
380 	.mmio_offset = VLV_DISPLAY_BASE,
381 	I9XX_PIPE_OFFSETS,
382 	I9XX_CURSOR_OFFSETS,
383 	I9XX_COLORS,
384 
385 	.__runtime_defaults.ip.ver = 7,
386 	.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
387 	.__runtime_defaults.cpu_transcoder_mask =
388 		BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
389 	.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* HDMI/DP B/C */
390 };
391 
392 static const struct intel_display_device_info hsw_display = {
393 	.has_ddi = 1,
394 	.has_dp_mst = 1,
395 	.has_fpga_dbg = 1,
396 	.has_hotplug = 1,
397 	.has_psr = 1,
398 	.has_psr_hw_tracking = 1,
399 	HSW_PIPE_OFFSETS,
400 	IVB_CURSOR_OFFSETS,
401 	IVB_COLORS,
402 
403 	.__runtime_defaults.ip.ver = 7,
404 	.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
405 	.__runtime_defaults.cpu_transcoder_mask =
406 		BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
407 		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
408 	.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
409 	.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
410 };
411 
412 static const struct intel_display_device_info bdw_display = {
413 	.has_ddi = 1,
414 	.has_dp_mst = 1,
415 	.has_fpga_dbg = 1,
416 	.has_hotplug = 1,
417 	.has_psr = 1,
418 	.has_psr_hw_tracking = 1,
419 	HSW_PIPE_OFFSETS,
420 	IVB_CURSOR_OFFSETS,
421 	IVB_COLORS,
422 
423 	.__runtime_defaults.ip.ver = 8,
424 	.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
425 	.__runtime_defaults.cpu_transcoder_mask =
426 		BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
427 		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
428 	.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
429 	.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
430 };
431 
432 static const struct intel_display_device_info chv_display = {
433 	.has_hotplug = 1,
434 	.has_gmch = 1,
435 	.mmio_offset = VLV_DISPLAY_BASE,
436 	CHV_PIPE_OFFSETS,
437 	CHV_CURSOR_OFFSETS,
438 	CHV_COLORS,
439 
440 	.__runtime_defaults.ip.ver = 8,
441 	.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
442 	.__runtime_defaults.cpu_transcoder_mask =
443 		BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
444 	.__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* HDMI/DP B/C/D */
445 };
446 
447 static const struct intel_display_device_info skl_display = {
448 	.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */
449 	.dbuf.slice_mask = BIT(DBUF_S1),
450 	.has_ddi = 1,
451 	.has_dp_mst = 1,
452 	.has_fpga_dbg = 1,
453 	.has_hotplug = 1,
454 	.has_ipc = 1,
455 	.has_psr = 1,
456 	.has_psr_hw_tracking = 1,
457 	HSW_PIPE_OFFSETS,
458 	IVB_CURSOR_OFFSETS,
459 	IVB_COLORS,
460 
461 	.__runtime_defaults.ip.ver = 9,
462 	.__runtime_defaults.has_dmc = 1,
463 	.__runtime_defaults.has_hdcp = 1,
464 	.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
465 	.__runtime_defaults.cpu_transcoder_mask =
466 		BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
467 		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
468 	.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
469 	.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
470 };
471 
472 #define GEN9_LP_DISPLAY \
473 	.dbuf.slice_mask = BIT(DBUF_S1), \
474 	.has_dp_mst = 1, \
475 	.has_ddi = 1, \
476 	.has_fpga_dbg = 1, \
477 	.has_hotplug = 1, \
478 	.has_ipc = 1, \
479 	.has_psr = 1, \
480 	.has_psr_hw_tracking = 1, \
481 	HSW_PIPE_OFFSETS, \
482 	IVB_CURSOR_OFFSETS, \
483 	IVB_COLORS, \
484 	\
485 	.__runtime_defaults.has_dmc = 1, \
486 	.__runtime_defaults.has_hdcp = 1, \
487 	.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \
488 	.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
489 	.__runtime_defaults.cpu_transcoder_mask = \
490 		BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
491 		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
492 		BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
493 	.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C)
494 
495 static const struct intel_display_device_info bxt_display = {
496 	GEN9_LP_DISPLAY,
497 	.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
498 
499 	.__runtime_defaults.ip.ver = 9,
500 };
501 
502 static const struct intel_display_device_info glk_display = {
503 	GEN9_LP_DISPLAY,
504 	.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
505 	GLK_COLORS,
506 
507 	.__runtime_defaults.ip.ver = 10,
508 };
509 
510 #define ICL_DISPLAY \
511 	.abox_mask = BIT(0), \
512 	.dbuf.size = 2048, \
513 	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
514 	.has_ddi = 1, \
515 	.has_dp_mst = 1, \
516 	.has_fpga_dbg = 1, \
517 	.has_hotplug = 1, \
518 	.has_ipc = 1, \
519 	.has_psr = 1, \
520 	.has_psr_hw_tracking = 1, \
521 	.pipe_offsets = { \
522 		[TRANSCODER_A] = PIPE_A_OFFSET, \
523 		[TRANSCODER_B] = PIPE_B_OFFSET, \
524 		[TRANSCODER_C] = PIPE_C_OFFSET, \
525 		[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
526 		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
527 		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
528 	}, \
529 	.trans_offsets = { \
530 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
531 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
532 		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
533 		[TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
534 		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
535 		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
536 	}, \
537 	IVB_CURSOR_OFFSETS, \
538 	ICL_COLORS, \
539 	\
540 	.__runtime_defaults.ip.ver = 11, \
541 	.__runtime_defaults.has_dmc = 1, \
542 	.__runtime_defaults.has_dsc = 1, \
543 	.__runtime_defaults.has_hdcp = 1, \
544 	.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
545 	.__runtime_defaults.cpu_transcoder_mask = \
546 		BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
547 		BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
548 		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
549 	.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A)
550 
551 static const struct intel_display_device_info icl_display = {
552 	ICL_DISPLAY,
553 
554 	.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
555 };
556 
557 static const struct intel_display_device_info jsl_ehl_display = {
558 	ICL_DISPLAY,
559 
560 	.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D),
561 };
562 
563 #define XE_D_DISPLAY \
564 	.abox_mask = GENMASK(2, 1), \
565 	.dbuf.size = 2048, \
566 	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
567 	.has_ddi = 1, \
568 	.has_dp_mst = 1, \
569 	.has_dsb = 1, \
570 	.has_fpga_dbg = 1, \
571 	.has_hotplug = 1, \
572 	.has_ipc = 1, \
573 	.has_psr = 1, \
574 	.has_psr_hw_tracking = 1, \
575 	.pipe_offsets = { \
576 		[TRANSCODER_A] = PIPE_A_OFFSET, \
577 		[TRANSCODER_B] = PIPE_B_OFFSET, \
578 		[TRANSCODER_C] = PIPE_C_OFFSET, \
579 		[TRANSCODER_D] = PIPE_D_OFFSET, \
580 		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
581 		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
582 	}, \
583 	.trans_offsets = { \
584 		[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
585 		[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
586 		[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
587 		[TRANSCODER_D] = TRANSCODER_D_OFFSET, \
588 		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
589 		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
590 	}, \
591 	TGL_CURSOR_OFFSETS, \
592 	ICL_COLORS, \
593 	\
594 	.__runtime_defaults.ip.ver = 12, \
595 	.__runtime_defaults.has_dmc = 1, \
596 	.__runtime_defaults.has_dsc = 1, \
597 	.__runtime_defaults.has_hdcp = 1, \
598 	.__runtime_defaults.pipe_mask = \
599 		BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
600 	.__runtime_defaults.cpu_transcoder_mask = \
601 		BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
602 		BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
603 		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
604 	.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A)
605 
606 static const struct intel_display_device_info tgl_display = {
607 	XE_D_DISPLAY,
608 
609 	/*
610 	 * FIXME DDI C/combo PHY C missing due to combo PHY
611 	 * code making a mess on SKUs where the PHY is missing.
612 	 */
613 	.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
614 		BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4) | BIT(PORT_TC5) | BIT(PORT_TC6),
615 };
616 
617 static const struct intel_display_device_info dg1_display = {
618 	XE_D_DISPLAY,
619 
620 	.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
621 		BIT(PORT_TC1) | BIT(PORT_TC2),
622 };
623 
624 static const struct intel_display_device_info rkl_display = {
625 	XE_D_DISPLAY,
626 	.abox_mask = BIT(0),
627 	.has_hti = 1,
628 	.has_psr_hw_tracking = 0,
629 
630 	.__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
631 	.__runtime_defaults.cpu_transcoder_mask =
632 		BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
633 	.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
634 		BIT(PORT_TC1) | BIT(PORT_TC2),
635 };
636 
637 static const struct intel_display_device_info adl_s_display = {
638 	XE_D_DISPLAY,
639 	.has_hti = 1,
640 	.has_psr_hw_tracking = 0,
641 
642 	.__runtime_defaults.port_mask = BIT(PORT_A) |
643 		BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
644 };
645 
646 #define XE_LPD_FEATURES \
647 	.abox_mask = GENMASK(1, 0),						\
648 	.color = {								\
649 		.degamma_lut_size = 129, .gamma_lut_size = 1024,		\
650 		.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING |		\
651 		DRM_COLOR_LUT_EQUAL_CHANNELS,					\
652 	},									\
653 	.dbuf.size = 4096,							\
654 	.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) |		\
655 		BIT(DBUF_S4),							\
656 	.has_ddi = 1,								\
657 	.has_dp_mst = 1,							\
658 	.has_dsb = 1,								\
659 	.has_fpga_dbg = 1,							\
660 	.has_hotplug = 1,							\
661 	.has_ipc = 1,								\
662 	.has_psr = 1,								\
663 	.pipe_offsets = {							\
664 		[TRANSCODER_A] = PIPE_A_OFFSET,					\
665 		[TRANSCODER_B] = PIPE_B_OFFSET,					\
666 		[TRANSCODER_C] = PIPE_C_OFFSET,					\
667 		[TRANSCODER_D] = PIPE_D_OFFSET,					\
668 		[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET,				\
669 		[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET,				\
670 	},									\
671 	.trans_offsets = {							\
672 		[TRANSCODER_A] = TRANSCODER_A_OFFSET,				\
673 		[TRANSCODER_B] = TRANSCODER_B_OFFSET,				\
674 		[TRANSCODER_C] = TRANSCODER_C_OFFSET,				\
675 		[TRANSCODER_D] = TRANSCODER_D_OFFSET,				\
676 		[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET,			\
677 		[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET,			\
678 	},									\
679 	TGL_CURSOR_OFFSETS,							\
680 										\
681 	.__runtime_defaults.ip.ver = 13,					\
682 	.__runtime_defaults.has_dmc = 1,					\
683 	.__runtime_defaults.has_dsc = 1,					\
684 	.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),			\
685 	.__runtime_defaults.has_hdcp = 1,					\
686 	.__runtime_defaults.pipe_mask =						\
687 		BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
688 
689 static const struct intel_display_device_info xe_lpd_display = {
690 	XE_LPD_FEATURES,
691 	.has_cdclk_crawl = 1,
692 	.has_psr_hw_tracking = 0,
693 
694 	.__runtime_defaults.cpu_transcoder_mask =
695 		BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
696 		BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
697 		BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
698 	.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
699 		BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
700 };
701 
702 static const struct intel_display_device_info xe_hpd_display = {
703 	XE_LPD_FEATURES,
704 	.has_cdclk_squash = 1,
705 
706 	.__runtime_defaults.cpu_transcoder_mask =
707 		BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
708 		BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
709 	.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D_XELPD) |
710 		BIT(PORT_TC1),
711 };
712 
713 static const struct intel_display_device_info xe_lpdp_display = {
714 	XE_LPD_FEATURES,
715 	.has_cdclk_crawl = 1,
716 	.has_cdclk_squash = 1,
717 
718 	.__runtime_defaults.ip.ver = 14,
719 	.__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
720 	.__runtime_defaults.cpu_transcoder_mask =
721 		BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
722 		BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
723 	.__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
724 		BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
725 };
726 
727 /*
728  * Separate detection for no display cases to keep the display id array simple.
729  *
730  * IVB Q requires subvendor and subdevice matching to differentiate from IVB D
731  * GT2 server.
732  */
has_no_display(struct pci_dev * pdev)733 static bool has_no_display(struct pci_dev *pdev)
734 {
735 	static const struct pci_device_id ids[] = {
736 		INTEL_IVB_Q_IDS(0),
737 		{}
738 	};
739 
740 	return pci_match_id(ids, pdev);
741 }
742 
743 #undef INTEL_VGA_DEVICE
744 #define INTEL_VGA_DEVICE(id, info) { id, info }
745 
746 static const struct {
747 	u32 devid;
748 	const struct intel_display_device_info *info;
749 } intel_display_ids[] = {
750 	INTEL_I830_IDS(&i830_display),
751 	INTEL_I845G_IDS(&i845_display),
752 	INTEL_I85X_IDS(&i85x_display),
753 	INTEL_I865G_IDS(&i865g_display),
754 	INTEL_I915G_IDS(&i915g_display),
755 	INTEL_I915GM_IDS(&i915gm_display),
756 	INTEL_I945G_IDS(&i945g_display),
757 	INTEL_I945GM_IDS(&i945gm_display),
758 	INTEL_I965G_IDS(&i965g_display),
759 	INTEL_G33_IDS(&g33_display),
760 	INTEL_I965GM_IDS(&i965gm_display),
761 	INTEL_GM45_IDS(&gm45_display),
762 	INTEL_G45_IDS(&g45_display),
763 	INTEL_PINEVIEW_G_IDS(&pnv_display),
764 	INTEL_PINEVIEW_M_IDS(&pnv_display),
765 	INTEL_IRONLAKE_D_IDS(&ilk_d_display),
766 	INTEL_IRONLAKE_M_IDS(&ilk_m_display),
767 	INTEL_SNB_D_IDS(&snb_display),
768 	INTEL_SNB_M_IDS(&snb_display),
769 	INTEL_IVB_M_IDS(&ivb_display),
770 	INTEL_IVB_D_IDS(&ivb_display),
771 	INTEL_HSW_IDS(&hsw_display),
772 	INTEL_VLV_IDS(&vlv_display),
773 	INTEL_BDW_IDS(&bdw_display),
774 	INTEL_CHV_IDS(&chv_display),
775 	INTEL_SKL_IDS(&skl_display),
776 	INTEL_BXT_IDS(&bxt_display),
777 	INTEL_GLK_IDS(&glk_display),
778 	INTEL_KBL_IDS(&skl_display),
779 	INTEL_CFL_IDS(&skl_display),
780 	INTEL_ICL_11_IDS(&icl_display),
781 	INTEL_EHL_IDS(&jsl_ehl_display),
782 	INTEL_JSL_IDS(&jsl_ehl_display),
783 	INTEL_TGL_12_IDS(&tgl_display),
784 	INTEL_DG1_IDS(&dg1_display),
785 	INTEL_RKL_IDS(&rkl_display),
786 	INTEL_ADLS_IDS(&adl_s_display),
787 	INTEL_RPLS_IDS(&adl_s_display),
788 	INTEL_ADLP_IDS(&xe_lpd_display),
789 	INTEL_ADLN_IDS(&xe_lpd_display),
790 	INTEL_RPLP_IDS(&xe_lpd_display),
791 	INTEL_DG2_IDS(&xe_hpd_display),
792 
793 	/*
794 	 * Do not add any GMD_ID-based platforms to this list.  They will
795 	 * be probed automatically based on the IP version reported by
796 	 * the hardware.
797 	 */
798 };
799 
800 static const struct {
801 	u16 ver;
802 	u16 rel;
803 	const struct intel_display_device_info *display;
804 } gmdid_display_map[] = {
805 	{ 14,  0, &xe_lpdp_display },
806 };
807 
808 static const struct intel_display_device_info *
probe_gmdid_display(struct drm_i915_private * i915,u16 * ver,u16 * rel,u16 * step)809 probe_gmdid_display(struct drm_i915_private *i915, u16 *ver, u16 *rel, u16 *step)
810 {
811 	struct pci_dev *pdev = i915->drm.pdev;
812 	void __iomem *addr;
813 	u32 val;
814 	int i;
815 	int mmio_bar, mmio_size, mmio_type;
816 	bus_space_tag_t bst;
817 	bus_space_handle_t bsh;
818 	bus_size_t memsize;
819 
820 	/* The caller expects to ver, rel and step to be initialized
821 	 * here, and there's no good way to check when there was a
822 	 * failure and no_display was returned.  So initialize all these
823 	 * values here zero, to be sure.
824 	 */
825 	*ver = 0;
826 	*rel = 0;
827 	*step = 0;
828 
829 #ifdef __linux__
830 	addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY), sizeof(u32));
831 	if (!addr) {
832 		drm_err(&i915->drm, "Cannot map MMIO BAR to read display GMD_ID\n");
833 		return &no_display;
834 	}
835 
836 	val = ioread32(addr);
837 	pci_iounmap(pdev, addr);
838 #else
839 	mmio_bar = 0x10;
840 	mmio_type = pci_mapreg_type(i915->pc, i915->tag, mmio_bar);
841 	if (pci_mapreg_map(i915->pa, mmio_bar, mmio_type, 0,
842 	    &bst, &bsh, NULL, &memsize, 0)) {
843 		drm_err(&i915->drm, "Cannot map MMIO BAR to read display GMD_ID\n");
844 		return &no_display;
845 	}
846 
847 	val = bus_space_read_4(bst, bsh, i915_mmio_reg_offset(GMD_ID_DISPLAY));
848 
849 	bus_space_unmap(bst, bsh, memsize);
850 #endif
851 
852 	if (val == 0) {
853 		drm_dbg_kms(&i915->drm, "Device doesn't have display\n");
854 		return &no_display;
855 	}
856 
857 	*ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
858 	*rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
859 	*step = REG_FIELD_GET(GMD_ID_STEP, val);
860 
861 	for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++)
862 		if (*ver == gmdid_display_map[i].ver &&
863 		    *rel == gmdid_display_map[i].rel)
864 			return gmdid_display_map[i].display;
865 
866 	drm_err(&i915->drm, "Unrecognized display IP version %d.%02d; disabling display.\n",
867 		*ver, *rel);
868 	return &no_display;
869 }
870 
871 const struct intel_display_device_info *
intel_display_device_probe(struct drm_i915_private * i915,bool has_gmdid,u16 * gmdid_ver,u16 * gmdid_rel,u16 * gmdid_step)872 intel_display_device_probe(struct drm_i915_private *i915, bool has_gmdid,
873 			   u16 *gmdid_ver, u16 *gmdid_rel, u16 *gmdid_step)
874 {
875 	struct pci_dev *pdev = i915->drm.pdev;
876 	int i;
877 
878 	if (has_gmdid)
879 		return probe_gmdid_display(i915, gmdid_ver, gmdid_rel, gmdid_step);
880 
881 	if (has_no_display(pdev)) {
882 		drm_dbg_kms(&i915->drm, "Device doesn't have display\n");
883 		return &no_display;
884 	}
885 
886 	for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) {
887 		if (intel_display_ids[i].devid == pdev->device)
888 			return intel_display_ids[i].info;
889 	}
890 
891 	drm_dbg(&i915->drm, "No display ID found for device ID %04x; disabling display.\n",
892 		pdev->device);
893 
894 	return &no_display;
895 }
896 
intel_display_device_info_runtime_init(struct drm_i915_private * i915)897 void intel_display_device_info_runtime_init(struct drm_i915_private *i915)
898 {
899 	struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(i915);
900 	enum pipe pipe;
901 
902 	BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->pipe_mask) < I915_MAX_PIPES);
903 	BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->cpu_transcoder_mask) < I915_MAX_TRANSCODERS);
904 	BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->port_mask) < I915_MAX_PORTS);
905 
906 	/* Wa_14011765242: adl-s A0,A1 */
907 	if (IS_ALDERLAKE_S(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_A2))
908 		for_each_pipe(i915, pipe)
909 			display_runtime->num_scalers[pipe] = 0;
910 	else if (DISPLAY_VER(i915) >= 11) {
911 		for_each_pipe(i915, pipe)
912 			display_runtime->num_scalers[pipe] = 2;
913 	} else if (DISPLAY_VER(i915) >= 9) {
914 		display_runtime->num_scalers[PIPE_A] = 2;
915 		display_runtime->num_scalers[PIPE_B] = 2;
916 		display_runtime->num_scalers[PIPE_C] = 1;
917 	}
918 
919 	if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915))
920 		for_each_pipe(i915, pipe)
921 			display_runtime->num_sprites[pipe] = 4;
922 	else if (DISPLAY_VER(i915) >= 11)
923 		for_each_pipe(i915, pipe)
924 			display_runtime->num_sprites[pipe] = 6;
925 	else if (DISPLAY_VER(i915) == 10)
926 		for_each_pipe(i915, pipe)
927 			display_runtime->num_sprites[pipe] = 3;
928 	else if (IS_BROXTON(i915)) {
929 		/*
930 		 * Skylake and Broxton currently don't expose the topmost plane as its
931 		 * use is exclusive with the legacy cursor and we only want to expose
932 		 * one of those, not both. Until we can safely expose the topmost plane
933 		 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
934 		 * we don't expose the topmost plane at all to prevent ABI breakage
935 		 * down the line.
936 		 */
937 
938 		display_runtime->num_sprites[PIPE_A] = 2;
939 		display_runtime->num_sprites[PIPE_B] = 2;
940 		display_runtime->num_sprites[PIPE_C] = 1;
941 	} else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
942 		for_each_pipe(i915, pipe)
943 			display_runtime->num_sprites[pipe] = 2;
944 	} else if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915)) {
945 		for_each_pipe(i915, pipe)
946 			display_runtime->num_sprites[pipe] = 1;
947 	}
948 
949 	if ((IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) &&
950 	    !(intel_de_read(i915, GU_CNTL_PROTECTED) & DEPRESENT)) {
951 		drm_info(&i915->drm, "Display not present, disabling\n");
952 		goto display_fused_off;
953 	}
954 
955 	if (IS_GRAPHICS_VER(i915, 7, 8) && HAS_PCH_SPLIT(i915)) {
956 		u32 fuse_strap = intel_de_read(i915, FUSE_STRAP);
957 		u32 sfuse_strap = intel_de_read(i915, SFUSE_STRAP);
958 
959 		/*
960 		 * SFUSE_STRAP is supposed to have a bit signalling the display
961 		 * is fused off. Unfortunately it seems that, at least in
962 		 * certain cases, fused off display means that PCH display
963 		 * reads don't land anywhere. In that case, we read 0s.
964 		 *
965 		 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
966 		 * should be set when taking over after the firmware.
967 		 */
968 		if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
969 		    sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
970 		    (HAS_PCH_CPT(i915) &&
971 		     !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
972 			drm_info(&i915->drm,
973 				 "Display fused off, disabling\n");
974 			goto display_fused_off;
975 		} else if (fuse_strap & IVB_PIPE_C_DISABLE) {
976 			drm_info(&i915->drm, "PipeC fused off\n");
977 			display_runtime->pipe_mask &= ~BIT(PIPE_C);
978 			display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
979 		}
980 	} else if (DISPLAY_VER(i915) >= 9) {
981 		u32 dfsm = intel_de_read(i915, SKL_DFSM);
982 
983 		if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
984 			display_runtime->pipe_mask &= ~BIT(PIPE_A);
985 			display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
986 			display_runtime->fbc_mask &= ~BIT(INTEL_FBC_A);
987 		}
988 		if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
989 			display_runtime->pipe_mask &= ~BIT(PIPE_B);
990 			display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
991 		}
992 		if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
993 			display_runtime->pipe_mask &= ~BIT(PIPE_C);
994 			display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
995 		}
996 
997 		if (DISPLAY_VER(i915) >= 12 &&
998 		    (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
999 			display_runtime->pipe_mask &= ~BIT(PIPE_D);
1000 			display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
1001 		}
1002 
1003 		if (!display_runtime->pipe_mask)
1004 			goto display_fused_off;
1005 
1006 		if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
1007 			display_runtime->has_hdcp = 0;
1008 
1009 		if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
1010 			display_runtime->fbc_mask = 0;
1011 
1012 		if (DISPLAY_VER(i915) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
1013 			display_runtime->has_dmc = 0;
1014 
1015 		if (IS_DISPLAY_VER(i915, 10, 12) &&
1016 		    (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE))
1017 			display_runtime->has_dsc = 0;
1018 	}
1019 
1020 	return;
1021 
1022 display_fused_off:
1023 	memset(display_runtime, 0, sizeof(*display_runtime));
1024 }
1025 
intel_display_device_info_print(const struct intel_display_device_info * info,const struct intel_display_runtime_info * runtime,struct drm_printer * p)1026 void intel_display_device_info_print(const struct intel_display_device_info *info,
1027 				     const struct intel_display_runtime_info *runtime,
1028 				     struct drm_printer *p)
1029 {
1030 	if (runtime->ip.rel)
1031 		drm_printf(p, "display version: %u.%02u\n",
1032 			   runtime->ip.ver,
1033 			   runtime->ip.rel);
1034 	else
1035 		drm_printf(p, "display version: %u\n",
1036 			   runtime->ip.ver);
1037 
1038 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name))
1039 	DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
1040 #undef PRINT_FLAG
1041 
1042 	drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp));
1043 	drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc));
1044 	drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc));
1045 }
1046