1 /* $OpenBSD: if_etreg.h,v 1.7 2024/10/23 01:35:43 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 5 * 6 * This code is derived from software contributed to The DragonFly Project 7 * by Sepherosa Ziehau <sepherosa@gmail.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in 17 * the documentation and/or other materials provided with the 18 * distribution. 19 * 3. Neither the name of The DragonFly Project nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific, prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 26 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 27 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 29 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 31 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 33 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * $DragonFly: src/sys/dev/netif/et/if_etreg.h,v 1.1 2007/10/12 14:12:42 sephe Exp $ 37 */ 38 39 #ifndef _IF_ETREG_H 40 #define _IF_ETREG_H 41 42 #define ET_INTERN_MEM_SIZE 0x400 43 #define ET_INTERN_MEM_END (ET_INTERN_MEM_SIZE - 1) 44 45 /* 46 * PCI registers 47 * 48 * ET_PCIV_ACK_LATENCY_{128,256} are from 49 * PCI EXPRESS BASE SPECIFICATION, REV. 1.0a, Table 3-5 50 * 51 * ET_PCIV_REPLAY_TIMER_{128,256} are from 52 * PCI EXPRESS BASE SPECIFICATION, REV. 1.0a, Table 3-4 53 */ 54 #define ET_PCIR_BAR 0x10 55 56 #define ET_PCIR_DEVICE_CAPS 0x4c 57 #define ET_PCIM_DEVICE_CAPS_MAX_PLSZ 0x7 /* Max playload size */ 58 #define ET_PCIV_DEVICE_CAPS_PLSZ_128 0x0 59 #define ET_PCIV_DEVICE_CAPS_PLSZ_256 0x1 60 61 #define ET_PCIR_DEVICE_CTRL 0x50 62 #define ET_PCIM_DEVICE_CTRL_MAX_RRSZ 0x7000 /* Max read request size */ 63 #define ET_PCIV_DEVICE_CTRL_RRSZ_2K 0x4000 64 65 #define ET_PCIR_MACADDR_LO 0xa4 66 #define ET_PCIR_MACADDR_HI 0xa8 67 68 #define ET_PCIR_EEPROM_MISC 0xb0 69 #define ET_PCIR_EEPROM_STATUS_MASK 0x0000ff00 70 #define ET_PCIM_EEPROM_STATUS_ERROR 0x00004c00 71 72 #define ET_PCIR_ACK_LATENCY 0xc0 73 #define ET_PCIV_ACK_LATENCY_128 237 74 #define ET_PCIV_ACK_LATENCY_256 416 75 76 #define ET_PCIR_REPLAY_TIMER 0xc2 77 #define ET_REPLAY_TIMER_RX_L0S_ADJ 250 /* XXX inferred from default */ 78 #define ET_PCIV_REPLAY_TIMER_128 (711 + ET_REPLAY_TIMER_RX_L0S_ADJ) 79 #define ET_PCIV_REPLAY_TIMER_256 (1248 + ET_REPLAY_TIMER_RX_L0S_ADJ) 80 81 #define ET_PCIR_L0S_L1_LATENCY 0xcf 82 #define ET_PCIM_L0S_LATENCY (7 << 0) 83 #define ET_PCIM_L1_LATENCY (7 << 3) 84 85 /* 86 * CSR 87 */ 88 #define ET_TXQ_START 0x0000 89 #define ET_TXQ_END 0x0004 90 #define ET_RXQ_START 0x0008 91 #define ET_RXQ_END 0x000c 92 93 #define ET_PM 0x0010 94 #define ET_PM_SYSCLK_GATE (1 << 3) 95 #define ET_PM_TXCLK_GATE (1 << 4) 96 #define ET_PM_RXCLK_GATE (1 << 5) 97 98 #define ET_INTR_STATUS 0x0018 99 #define ET_INTR_MASK 0x001c 100 101 #define ET_SWRST 0x0028 102 #define ET_SWRST_TXDMA (1U << 0) 103 #define ET_SWRST_RXDMA (1U << 1) 104 #define ET_SWRST_TXMAC (1U << 2) 105 #define ET_SWRST_RXMAC (1U << 3) 106 #define ET_SWRST_MAC (1U << 4) 107 #define ET_SWRST_MAC_STAT (1U << 5) 108 #define ET_SWRST_MMC (1U << 6) 109 #define ET_SWRST_SELFCLR_DISABLE (1U << 31) 110 111 #define ET_MSI_CFG 0x0030 112 113 #define ET_LOOPBACK 0x0034 114 115 #define ET_TIMER 0x0038 116 117 #define ET_TXDMA_CTRL 0x1000 118 #define ET_TXDMA_CTRL_HALT (1 << 0) 119 #define ET_TXDMA_CTRL_CACHE_THR 0xf0 120 #define ET_TXDMA_CTRL_SINGLE_EPKT (1 << 8) 121 122 #define ET_TX_RING_HI 0x1004 123 #define ET_TX_RING_LO 0x1008 124 #define ET_TX_RING_CNT 0x100c 125 126 #define ET_TX_STATUS_HI 0x101c 127 #define ET_TX_STATUS_LO 0x1020 128 129 #define ET_TX_READY_POS 0x1024 130 #define ET_TX_READY_POS_INDEX 0x03ff 131 #define ET_TX_READY_POS_WRAP (1 << 10) 132 133 #define ET_TX_DONE_POS 0x1060 134 #define ET_TX_DONE_POS_INDEX 0x03ff 135 #define ET_TX_DONE_POS_WRAP (1 << 10) 136 137 #define ET_RXDMA_CTRL 0x2000 138 #define ET_RXDMA_CTRL_HALT (1 << 0) 139 #define ET_RXDMA_CTRL_RING0_SIZE (3 << 8) 140 #define ET_RXDMA_CTRL_RING0_ENABLE (1 << 10) 141 #define ET_RXDMA_CTRL_RING1_SIZE (3 << 11) 142 #define ET_RXDMA_CTRL_RING1_ENABLE (1 << 13) 143 #define ET_RXDMA_CTRL_HALTED (1 << 17) 144 145 #define ET_RX_STATUS_LO 0x2004 146 #define ET_RX_STATUS_HI 0x2008 147 148 #define ET_RX_INTR_NPKTS 0x200c 149 #define ET_RX_INTR_DELAY 0x2010 150 151 #define ET_RXSTAT_LO 0x2020 152 #define ET_RXSTAT_HI 0x2024 153 #define ET_RXSTAT_CNT 0x2028 154 155 #define ET_RXSTAT_POS 0x2030 156 #define ET_RXSTAT_POS_INDEX 0x0fff 157 #define ET_RXSTAT_POS_WRAP (1 << 12) 158 159 #define ET_RXSTAT_MINCNT 0x2038 160 161 #define ET_RX_RING0_LO 0x203c 162 #define ET_RX_RING0_HI 0x2040 163 #define ET_RX_RING0_CNT 0x2044 164 165 #define ET_RX_RING0_POS 0x204c 166 #define ET_RX_RING0_POS_INDEX 0x03ff 167 #define ET_RX_RING0_POS_WRAP (1 << 10) 168 169 #define ET_RX_RING0_MINCNT 0x2054 170 171 #define ET_RX_RING1_LO 0x2058 172 #define ET_RX_RING1_HI 0x205c 173 #define ET_RX_RING1_CNT 0x2060 174 175 #define ET_RX_RING1_POS 0x2068 176 #define ET_RX_RING1_POS_INDEX 0x03ff 177 #define ET_RX_RING1_POS_WRAP (1 << 10) 178 179 #define ET_RX_RING1_MINCNT 0x2070 180 181 #define ET_TXMAC_CTRL 0x3000 182 #define ET_TXMAC_CTRL_ENABLE (1 << 0) 183 #define ET_TXMAC_CTRL_FC_DISABLE (1 << 3) 184 185 #define ET_TXMAC_FLOWCTRL 0x3010 186 187 #define ET_RXMAC_CTRL 0x4000 188 #define ET_RXMAC_CTRL_ENABLE (1 << 0) 189 #define ET_RXMAC_CTRL_NO_PKTFILT (1 << 2) 190 #define ET_RXMAC_CTRL_WOL_DISABLE (1 << 3) 191 192 #define ET_WOL_CRC 0x4004 193 #define ET_WOL_SA_LO 0x4010 194 #define ET_WOL_SA_HI 0x4014 195 #define ET_WOL_MASK 0x4018 196 197 #define ET_UCAST_FILTADDR1 0x4068 198 #define ET_UCAST_FILTADDR2 0x406c 199 #define ET_UCAST_FILTADDR3 0x4070 200 201 #define ET_MULTI_HASH 0x4074 202 203 #define ET_PKTFILT 0x4084 204 #define ET_PKTFILT_BCAST (1 << 0) 205 #define ET_PKTFILT_MCAST (1 << 1) 206 #define ET_PKTFILT_UCAST (1 << 2) 207 #define ET_PKTFILT_FRAG (1 << 3) 208 #define ET_PKTFILT_MINLEN 0x7f0000 209 210 #define ET_RXMAC_MC_SEGSZ 0x4088 211 #define ET_RXMAC_MC_SEGSZ_ENABLE (1 << 0) 212 #define ET_RXMAC_MC_SEGSZ_FC (1 << 1) 213 #define ET_RXMAC_MC_SEGSZ_MAX 0x03fc 214 215 #define ET_RXMAC_MC_WATERMARK 0x408c 216 #define ET_RXMAC_SPACE_AVL 0x4094 217 218 #define ET_RXMAC_MGT 0x4098 219 #define ET_RXMAC_MGT_PASS_ECRC (1 << 4) 220 #define ET_RXMAC_MGT_PASS_ELEN (1 << 5) 221 #define ET_RXMAC_MGT_PASS_ETRUNC (1 << 16) 222 #define ET_RXMAC_MGT_CHECK_PKT (1 << 17) 223 224 #define ET_MAC_CFG1 0x5000 225 #define ET_MAC_CFG1_TXEN (1U << 0) 226 #define ET_MAC_CFG1_SYNC_TXEN (1U << 1) 227 #define ET_MAC_CFG1_RXEN (1U << 2) 228 #define ET_MAC_CFG1_SYNC_RXEN (1U << 3) 229 #define ET_MAC_CFG1_TXFLOW (1U << 4) 230 #define ET_MAC_CFG1_RXFLOW (1U << 5) 231 #define ET_MAC_CFG1_LOOPBACK (1U << 8) 232 #define ET_MAC_CFG1_RST_TXFUNC (1U << 16) 233 #define ET_MAC_CFG1_RST_RXFUNC (1U << 17) 234 #define ET_MAC_CFG1_RST_TXMC (1U << 18) 235 #define ET_MAC_CFG1_RST_RXMC (1U << 19) 236 #define ET_MAC_CFG1_SIM_RST (1U << 30) 237 #define ET_MAC_CFG1_SOFT_RST (1U << 31) 238 239 #define ET_MAC_CFG2 0x5004 240 #define ET_MAC_CFG2_FDX (1 << 0) 241 #define ET_MAC_CFG2_CRC (1 << 1) 242 #define ET_MAC_CFG2_PADCRC (1 << 2) 243 #define ET_MAC_CFG2_LENCHK (1 << 4) 244 #define ET_MAC_CFG2_BIGFRM (1 << 5) 245 #define ET_MAC_CFG2_MODE_MII (1 << 8) 246 #define ET_MAC_CFG2_MODE_GMII (1 << 9) 247 #define ET_MAC_CFG2_PREAMBLE_LEN 0xf000 248 249 #define ET_IPG 0x5008 250 #define ET_IPG_B2B 0x0000007f 251 #define ET_IPG_MINIFG 0x0000ff00 252 #define ET_IPG_NONB2B_2 0x007f0000 253 #define ET_IPG_NONB2B_1 0x7f000000 254 255 #define ET_MAC_HDX 0x500c 256 #define ET_MAC_HDX_COLLWIN 0x0003ff 257 #define ET_MAC_HDX_REXMIT_MAX 0x00f000 258 #define ET_MAC_HDX_EXC_DEFER (1 << 16) 259 #define ET_MAC_HDX_NOBACKOFF (1 << 17) 260 #define ET_MAC_HDX_BP_NOBACKOFF (1 << 18) 261 #define ET_MAC_HDX_ALT_BEB (1 << 19) 262 #define ET_MAC_HDX_ALT_BEB_TRUNC 0xf00000 263 264 #define ET_MAX_FRMLEN 0x5010 265 266 #define ET_MII_CFG 0x5020 267 #define ET_MII_CFG_CLKRST (7U << 0) 268 #define ET_MII_CFG_PREAMBLE_SUP (1U << 4) 269 #define ET_MII_CFG_SCAN_AUTOINC (1U << 5) 270 #define ET_MII_CFG_RST (1U << 31) 271 272 #define ET_MII_CMD 0x5024 273 #define ET_MII_CMD_READ (1 << 0) 274 275 #define ET_MII_ADDR 0x5028 276 #define ET_MII_ADDR_REG 0x001f 277 #define ET_MII_ADDR_PHY 0x1f00 278 #define ET_MII_ADDR_SHIFT 8 279 280 281 #define ET_MII_CTRL 0x502c 282 #define ET_MII_CTRL_VALUE 0xffff 283 284 #define ET_MII_STAT 0x5030 285 #define ET_MII_STAT_VALUE 0xffff 286 287 #define ET_MII_IND 0x5034 288 #define ET_MII_IND_BUSY (1 << 0) 289 #define ET_MII_IND_INVALID (1 << 2) 290 291 #define ET_MAC_CTRL 0x5038 292 #define ET_MAC_CTRL_MODE_MII (1 << 24) 293 #define ET_MAC_CTRL_LHDX (1 << 25) 294 #define ET_MAC_CTRL_GHDX (1 << 26) 295 296 #define ET_MAC_ADDR1 0x5040 297 #define ET_MAC_ADDR2 0x5044 298 299 #define ET_MMC_CTRL 0x7000 300 #define ET_MMC_CTRL_ENABLE (1 << 0) 301 #define ET_MMC_CTRL_ARB_DISABLE (1 << 1) 302 #define ET_MMC_CTRL_RXMAC_DISABLE (1 << 2) 303 #define ET_MMC_CTRL_TXMAC_DISABLE (1 << 3) 304 #define ET_MMC_CTRL_TXDMA_DISABLE (1 << 4) 305 #define ET_MMC_CTRL_RXDMA_DISABLE (1 << 5) 306 #define ET_MMC_CTRL_FORCE_CE (1 << 6) 307 308 /* 309 * Interrupts 310 */ 311 #define ET_INTR_TXEOF (1 << 3) 312 #define ET_INTR_TXDMA_ERROR (1 << 4) 313 #define ET_INTR_RXEOF (1 << 5) 314 #define ET_INTR_RXRING0_LOW (1 << 6) 315 #define ET_INTR_RXRING1_LOW (1 << 7) 316 #define ET_INTR_RXSTAT_LOW (1 << 8) 317 #define ET_INTR_RXDMA_ERROR (1 << 9) 318 #define ET_INTR_TIMER (1 << 10) 319 #define ET_INTR_WOL (1 << 15) 320 #define ET_INTR_PHY (1 << 16) 321 #define ET_INTR_TXMAC (1 << 17) 322 #define ET_INTR_RXMAC (1 << 18) 323 #define ET_INTR_MAC_STATS (1 << 19) 324 #define ET_INTR_SLAVE_TO (1 << 20) 325 326 #define ET_INTRS (ET_INTR_TXEOF | \ 327 ET_INTR_RXEOF | \ 328 ET_INTR_TIMER) 329 330 /* 331 * RX ring position uses same layout 332 */ 333 #define ET_RX_RING_POS_INDEX (0x03ff << 0) 334 #define ET_RX_RING_POS_WRAP (1 << 10) 335 336 337 /* $DragonFly: src/sys/dev/netif/et/if_etvar.h,v 1.1 2007/10/12 14:12:42 sephe Exp $ */ 338 339 #define ET_ALIGN 0x1000 340 #define ET_NSEG_MAX 32 /* XXX no limit actually */ 341 #define ET_NSEG_SPARE 5 342 343 #define ET_TX_NDESC 512 344 #define ET_RX_NDESC 512 345 #define ET_RX_NRING 2 346 #define ET_RX_NSTAT (ET_RX_NRING * ET_RX_NDESC) 347 348 #define ET_TX_RING_SIZE (ET_TX_NDESC * sizeof(struct et_txdesc)) 349 #define ET_RX_RING_SIZE (ET_RX_NDESC * sizeof(struct et_rxdesc)) 350 #define ET_RXSTAT_RING_SIZE (ET_RX_NSTAT * sizeof(struct et_rxstat)) 351 352 #define CSR_WRITE_4(sc, reg, val) \ 353 bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val)) 354 #define CSR_READ_4(sc, reg) \ 355 bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg)) 356 357 #define ET_ADDR_HI(addr) ((uint64_t) (addr) >> 32) 358 #define ET_ADDR_LO(addr) ((uint64_t) (addr) & 0xffffffff) 359 360 struct et_txdesc { 361 uint32_t td_addr_hi; 362 uint32_t td_addr_lo; 363 uint32_t td_ctrl1; /* ET_TDCTRL1_ */ 364 uint32_t td_ctrl2; /* ET_TDCTRL2_ */ 365 } __packed; 366 367 #define ET_TDCTRL1_LEN 0xffff 368 369 #define ET_TDCTRL2_LAST_FRAG (1 << 0) 370 #define ET_TDCTRL2_FIRST_FRAG (1 << 1) 371 #define ET_TDCTRL2_INTR (1 << 2) 372 373 struct et_rxdesc { 374 uint32_t rd_addr_lo; 375 uint32_t rd_addr_hi; 376 uint32_t rd_ctrl; /* ET_RDCTRL_ */ 377 } __packed; 378 379 #define ET_RDCTRL_BUFIDX 0x03ff 380 381 struct et_rxstat { 382 uint32_t rxst_info1; 383 uint32_t rxst_info2; /* ET_RXST_INFO2_ */ 384 } __packed; 385 386 #define ET_RXST_INFO2_LEN 0x000ffff 387 #define ET_RXST_INFO2_BUFIDX 0x3ff0000 388 #define ET_RXST_INFO2_RINGIDX (3 << 26) 389 390 struct et_rxstatus { 391 uint32_t rxs_ring; 392 uint32_t rxs_stat_ring; /* ET_RXS_STATRING_ */ 393 } __packed; 394 395 #define ET_RXS_STATRING_INDEX 0xfff0000 396 #define ET_RXS_STATRING_WRAP (1 << 28) 397 398 struct et_txbuf { 399 struct mbuf *tb_mbuf; 400 bus_dmamap_t tb_dmap; 401 bus_dma_segment_t tb_seg; 402 }; 403 404 struct et_rxbuf { 405 struct mbuf *rb_mbuf; 406 bus_dmamap_t rb_dmap; 407 bus_dma_segment_t rb_seg; 408 bus_addr_t rb_paddr; 409 }; 410 411 struct et_txstatus_data { 412 uint32_t *txsd_status; 413 bus_addr_t txsd_paddr; 414 bus_dma_tag_t txsd_dtag; 415 bus_dmamap_t txsd_dmap; 416 bus_dma_segment_t txsd_seg; 417 }; 418 419 struct et_rxstatus_data { 420 struct et_rxstatus *rxsd_status; 421 bus_addr_t rxsd_paddr; 422 bus_dma_tag_t rxsd_dtag; 423 bus_dmamap_t rxsd_dmap; 424 bus_dma_segment_t rxsd_seg; 425 }; 426 427 struct et_rxstat_ring { 428 struct et_rxstat *rsr_stat; 429 bus_addr_t rsr_paddr; 430 bus_dma_tag_t rsr_dtag; 431 bus_dmamap_t rsr_dmap; 432 bus_dma_segment_t rsr_seg; 433 434 int rsr_index; 435 int rsr_wrap; 436 }; 437 438 struct et_txdesc_ring { 439 struct et_txdesc *tr_desc; 440 bus_addr_t tr_paddr; 441 bus_dma_tag_t tr_dtag; 442 bus_dmamap_t tr_dmap; 443 bus_dma_segment_t tr_seg; 444 445 int tr_ready_index; 446 int tr_ready_wrap; 447 }; 448 449 struct et_rxdesc_ring { 450 struct et_rxdesc *rr_desc; 451 bus_addr_t rr_paddr; 452 bus_dma_tag_t rr_dtag; 453 bus_dmamap_t rr_dmap; 454 bus_dma_segment_t rr_seg; 455 456 uint32_t rr_posreg; 457 int rr_index; 458 int rr_wrap; 459 }; 460 461 struct et_txbuf_data { 462 struct et_txbuf tbd_buf[ET_TX_NDESC]; 463 464 int tbd_start_index; 465 int tbd_start_wrap; 466 int tbd_used; 467 }; 468 469 struct et_softc; 470 struct et_rxbuf_data; 471 typedef int (*et_newbuf_t)(struct et_rxbuf_data *, int, int); 472 473 struct et_rxbuf_data { 474 struct et_rxbuf rbd_buf[ET_RX_NDESC]; 475 476 struct et_softc *rbd_softc; 477 struct et_rxdesc_ring *rbd_ring; 478 479 int rbd_bufsize; 480 et_newbuf_t rbd_newbuf; 481 }; 482 483 struct et_softc { 484 struct device sc_dev; 485 struct arpcom sc_arpcom; 486 int sc_if_flags; 487 488 bus_space_tag_t sc_mem_bt; 489 bus_space_handle_t sc_mem_bh; 490 bus_size_t sc_mem_size; 491 bus_dma_tag_t sc_dmat; 492 pci_chipset_tag_t sc_pct; 493 pcitag_t sc_pcitag; 494 495 void *sc_irq_handle; 496 497 struct mii_data sc_miibus; 498 struct timeout sc_tick; 499 500 struct et_rxdesc_ring sc_rx_ring[ET_RX_NRING]; 501 struct et_rxstat_ring sc_rxstat_ring; 502 struct et_rxstatus_data sc_rx_status; 503 504 struct et_txdesc_ring sc_tx_ring; 505 struct et_txstatus_data sc_tx_status; 506 struct timeout sc_txtick; 507 508 bus_dmamap_t sc_mbuf_tmp_dmap; 509 struct et_rxbuf_data sc_rx_data[ET_RX_NRING]; 510 struct et_txbuf_data sc_tx_data; 511 512 uint32_t sc_tx; 513 uint32_t sc_tx_intr; 514 515 /* 516 * Sysctl variables 517 */ 518 int sc_rx_intr_npkts; 519 int sc_rx_intr_delay; 520 int sc_tx_intr_nsegs; 521 uint32_t sc_timer; 522 }; 523 524 #endif /* !_IF_ETREG_H */ 525