1 /* $OpenBSD: if_re_pci.c,v 1.59 2024/08/31 16:23:09 deraadt Exp $ */
2
3 /*
4 * Copyright (c) 2005 Peter Valchev <pvalchev@openbsd.org>
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19 /*
20 * PCI front-end for the Realtek 8169
21 */
22
23 #include <sys/param.h>
24 #include <sys/systm.h>
25 #include <sys/device.h>
26 #include <sys/timeout.h>
27
28 #include <net/if.h>
29 #include <net/if_media.h>
30
31 #include <netinet/in.h>
32 #include <netinet/if_ether.h>
33
34 #include <dev/mii/miivar.h>
35
36 #include <dev/pci/pcireg.h>
37 #include <dev/pci/pcivar.h>
38 #include <dev/pci/pcidevs.h>
39
40 #include <dev/ic/rtl81x9reg.h>
41 #include <dev/ic/revar.h>
42
43 struct re_pci_softc {
44 /* General */
45 struct rl_softc sc_rl;
46
47 /* PCI-specific data */
48 pci_chipset_tag_t sc_pc;
49 pcitag_t sc_pcitag;
50
51 bus_size_t sc_iosize;
52 };
53
54 const struct pci_matchid re_pci_devices[] = {
55 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CGLAPCIGT },
56 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T },
57 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T_C1 },
58 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_E2500V2 },
59 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_E2600 },
60 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E },
61 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168 },
62 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168_2 },
63 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169 },
64 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC },
65 { PCI_VENDOR_TTTECH, PCI_PRODUCT_TTTECH_MC322 },
66 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_USR997902 }
67 };
68
69 #define RE_LINKSYS_EG1032_SUBID 0x00241737
70
71 int re_pci_probe(struct device *, void *, void *);
72 void re_pci_attach(struct device *, struct device *, void *);
73 int re_pci_detach(struct device *, int);
74 int re_pci_activate(struct device *, int);
75
76 /*
77 * PCI autoconfig definitions
78 */
79 const struct cfattach re_pci_ca = {
80 sizeof(struct re_pci_softc),
81 re_pci_probe,
82 re_pci_attach,
83 re_pci_detach,
84 re_pci_activate
85 };
86
87 /*
88 * Probe for a Realtek 8169/8110 chip. Check the PCI vendor and device
89 * IDs against our list and return a device name if we find a match.
90 */
91 int
re_pci_probe(struct device * parent,void * match,void * aux)92 re_pci_probe(struct device *parent, void *match, void *aux)
93 {
94 struct pci_attach_args *pa = aux;
95 pci_chipset_tag_t pc = pa->pa_pc;
96 pcireg_t subid;
97
98 subid = pci_conf_read(pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
99
100 /* C+ mode 8139's */
101 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_REALTEK &&
102 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_REALTEK_RT8139 &&
103 PCI_REVISION(pa->pa_class) == 0x20)
104 return (1);
105
106 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS &&
107 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 &&
108 subid == RE_LINKSYS_EG1032_SUBID)
109 return (1);
110
111 return (pci_matchbyid((struct pci_attach_args *)aux, re_pci_devices,
112 nitems(re_pci_devices)));
113 }
114
115 /*
116 * PCI-specific attach routine
117 */
118 void
re_pci_attach(struct device * parent,struct device * self,void * aux)119 re_pci_attach(struct device *parent, struct device *self, void *aux)
120 {
121 struct re_pci_softc *psc = (struct re_pci_softc *)self;
122 struct rl_softc *sc = &psc->sc_rl;
123 struct pci_attach_args *pa = aux;
124 pci_chipset_tag_t pc = pa->pa_pc;
125 pci_intr_handle_t ih;
126 const char *intrstr = NULL;
127 pcireg_t reg;
128 int offset;
129
130 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0);
131
132 #ifndef SMALL_KERNEL
133 /* Enable power management for wake on lan. */
134 pci_conf_write(pc, pa->pa_tag, RL_PCI_PMCSR, RL_PME_EN);
135 #endif
136
137 /*
138 * Map control/status registers.
139 */
140 if (pci_mapreg_map(pa, RL_PCI_LOMEM64, PCI_MAPREG_TYPE_MEM |
141 PCI_MAPREG_MEM_TYPE_64BIT, 0, &sc->rl_btag, &sc->rl_bhandle,
142 NULL, &psc->sc_iosize, 0)) {
143 if (pci_mapreg_map(pa, RL_PCI_LOMEM, PCI_MAPREG_TYPE_MEM |
144 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->rl_btag, &sc->rl_bhandle,
145 NULL, &psc->sc_iosize, 0)) {
146 if (pci_mapreg_map(pa, RL_PCI_LOIO, PCI_MAPREG_TYPE_IO,
147 0, &sc->rl_btag, &sc->rl_bhandle, NULL,
148 &psc->sc_iosize, 0)) {
149 printf(": can't map mem or i/o space\n");
150 return;
151 }
152 }
153 }
154
155 /* Allocate interrupt */
156 if (pci_intr_map_msi(pa, &ih) == 0)
157 sc->rl_flags |= RL_FLAG_MSI;
158 else if (pci_intr_map(pa, &ih) != 0) {
159 printf(": couldn't map interrupt\n");
160 return;
161 }
162 intrstr = pci_intr_string(pc, ih);
163 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET | IPL_MPSAFE, re_intr,
164 sc, sc->sc_dev.dv_xname);
165 if (sc->sc_ih == NULL) {
166 printf(": couldn't establish interrupt");
167 if (intrstr != NULL)
168 printf(" at %s", intrstr);
169 return;
170 }
171
172 sc->sc_dmat = pa->pa_dmat;
173 psc->sc_pc = pc;
174
175 /*
176 * PCI Express check.
177 */
178 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS,
179 &offset, NULL)) {
180 /* Disable PCIe ASPM and ECPM. */
181 reg = pci_conf_read(pc, pa->pa_tag, offset + PCI_PCIE_LCSR);
182 reg &= ~(PCI_PCIE_LCSR_ASPM_L0S | PCI_PCIE_LCSR_ASPM_L1 |
183 PCI_PCIE_LCSR_ECPM);
184 pci_conf_write(pc, pa->pa_tag, offset + PCI_PCIE_LCSR, reg);
185 sc->rl_flags |= RL_FLAG_PCIE;
186 }
187
188 if (!(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_REALTEK &&
189 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_REALTEK_RT8139)) {
190 u_int8_t cfg;
191
192 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
193 cfg = CSR_READ_1(sc, RL_CFG2);
194 if (sc->rl_flags & RL_FLAG_MSI) {
195 cfg |= RL_CFG2_MSI;
196 CSR_WRITE_1(sc, RL_CFG2, cfg);
197 } else {
198 if ((cfg & RL_CFG2_MSI) != 0) {
199 cfg &= ~RL_CFG2_MSI;
200 CSR_WRITE_1(sc, RL_CFG2, cfg);
201 }
202 }
203 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
204 }
205
206 sc->sc_product = PCI_PRODUCT(pa->pa_id);
207
208 /* Call bus-independent attach routine */
209 if (re_attach(sc, intrstr)) {
210 pci_intr_disestablish(pc, sc->sc_ih);
211 bus_space_unmap(sc->rl_btag, sc->rl_bhandle, psc->sc_iosize);
212 }
213 }
214
215 int
re_pci_detach(struct device * self,int flags)216 re_pci_detach(struct device *self, int flags)
217 {
218 struct re_pci_softc *psc = (struct re_pci_softc *)self;
219 struct rl_softc *sc = &psc->sc_rl;
220
221 re_detach(sc);
222
223 /* Disable interrupts */
224 if (sc->sc_ih != NULL)
225 pci_intr_disestablish(psc->sc_pc, sc->sc_ih);
226
227 /* Free pci resources */
228 bus_space_unmap(sc->rl_btag, sc->rl_bhandle, psc->sc_iosize);
229
230 return (0);
231 }
232
233 int
re_pci_activate(struct device * self,int act)234 re_pci_activate(struct device *self, int act)
235 {
236 struct re_pci_softc *psc = (struct re_pci_softc *)self;
237 struct rl_softc *sc = &psc->sc_rl;
238 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
239
240 switch (act) {
241 case DVACT_SUSPEND:
242 if (ifp->if_flags & IFF_RUNNING)
243 re_stop(ifp);
244 break;
245 case DVACT_RESUME:
246 if (ifp->if_flags & IFF_UP)
247 re_init(ifp);
248 break;
249 }
250 return (0);
251 }
252