1 /* $OpenBSD: if_re_pci.c,v 1.53 2020/06/17 10:48:44 claudio Exp $ */ 2 3 /* 4 * Copyright (c) 2005 Peter Valchev <pvalchev@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * PCI front-end for the Realtek 8169 21 */ 22 23 #include <sys/param.h> 24 #include <sys/endian.h> 25 #include <sys/systm.h> 26 #include <sys/sockio.h> 27 #include <sys/mbuf.h> 28 #include <sys/malloc.h> 29 #include <sys/kernel.h> 30 #include <sys/device.h> 31 #include <sys/timeout.h> 32 #include <sys/socket.h> 33 34 #include <net/if.h> 35 #include <net/if_media.h> 36 37 #include <netinet/in.h> 38 #include <netinet/if_ether.h> 39 40 #include <dev/mii/miivar.h> 41 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcidevs.h> 45 46 #include <dev/ic/rtl81x9reg.h> 47 #include <dev/ic/revar.h> 48 49 struct re_pci_softc { 50 /* General */ 51 struct rl_softc sc_rl; 52 53 /* PCI-specific data */ 54 pci_chipset_tag_t sc_pc; 55 pcitag_t sc_pcitag; 56 57 bus_size_t sc_iosize; 58 }; 59 60 const struct pci_matchid re_pci_devices[] = { 61 { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CGLAPCIGT }, 62 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T }, 63 { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE530T_C1 }, 64 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E }, 65 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168 }, 66 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169 }, 67 { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC }, 68 { PCI_VENDOR_TTTECH, PCI_PRODUCT_TTTECH_MC322 }, 69 { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_USR997902 } 70 }; 71 72 #define RE_LINKSYS_EG1032_SUBID 0x00241737 73 74 int re_pci_probe(struct device *, void *, void *); 75 void re_pci_attach(struct device *, struct device *, void *); 76 int re_pci_detach(struct device *, int); 77 int re_pci_activate(struct device *, int); 78 79 /* 80 * PCI autoconfig definitions 81 */ 82 struct cfattach re_pci_ca = { 83 sizeof(struct re_pci_softc), 84 re_pci_probe, 85 re_pci_attach, 86 re_pci_detach, 87 re_pci_activate 88 }; 89 90 /* 91 * Probe for a Realtek 8169/8110 chip. Check the PCI vendor and device 92 * IDs against our list and return a device name if we find a match. 93 */ 94 int 95 re_pci_probe(struct device *parent, void *match, void *aux) 96 { 97 struct pci_attach_args *pa = aux; 98 pci_chipset_tag_t pc = pa->pa_pc; 99 pcireg_t subid; 100 101 subid = pci_conf_read(pc, pa->pa_tag, PCI_SUBSYS_ID_REG); 102 103 /* C+ mode 8139's */ 104 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_REALTEK && 105 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_REALTEK_RT8139 && 106 PCI_REVISION(pa->pa_class) == 0x20) 107 return (1); 108 109 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_LINKSYS && 110 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_LINKSYS_EG1032 && 111 subid == RE_LINKSYS_EG1032_SUBID) 112 return (1); 113 114 return (pci_matchbyid((struct pci_attach_args *)aux, re_pci_devices, 115 nitems(re_pci_devices))); 116 } 117 118 /* 119 * PCI-specific attach routine 120 */ 121 void 122 re_pci_attach(struct device *parent, struct device *self, void *aux) 123 { 124 struct re_pci_softc *psc = (struct re_pci_softc *)self; 125 struct rl_softc *sc = &psc->sc_rl; 126 struct pci_attach_args *pa = aux; 127 pci_chipset_tag_t pc = pa->pa_pc; 128 pci_intr_handle_t ih; 129 const char *intrstr = NULL; 130 pcireg_t reg; 131 int offset; 132 133 pci_set_powerstate(pa->pa_pc, pa->pa_tag, PCI_PMCSR_STATE_D0); 134 135 #ifndef SMALL_KERNEL 136 /* Enable power management for wake on lan. */ 137 pci_conf_write(pc, pa->pa_tag, RL_PCI_PMCSR, RL_PME_EN); 138 #endif 139 140 /* 141 * Map control/status registers. 142 */ 143 if (pci_mapreg_map(pa, RL_PCI_LOMEM64, PCI_MAPREG_TYPE_MEM | 144 PCI_MAPREG_MEM_TYPE_64BIT, 0, &sc->rl_btag, &sc->rl_bhandle, 145 NULL, &psc->sc_iosize, 0)) { 146 if (pci_mapreg_map(pa, RL_PCI_LOMEM, PCI_MAPREG_TYPE_MEM | 147 PCI_MAPREG_MEM_TYPE_32BIT, 0, &sc->rl_btag, &sc->rl_bhandle, 148 NULL, &psc->sc_iosize, 0)) { 149 if (pci_mapreg_map(pa, RL_PCI_LOIO, PCI_MAPREG_TYPE_IO, 150 0, &sc->rl_btag, &sc->rl_bhandle, NULL, 151 &psc->sc_iosize, 0)) { 152 printf(": can't map mem or i/o space\n"); 153 return; 154 } 155 } 156 } 157 158 /* Allocate interrupt */ 159 if (pci_intr_map_msi(pa, &ih) == 0) 160 sc->rl_flags |= RL_FLAG_MSI; 161 else if (pci_intr_map(pa, &ih) != 0) { 162 printf(": couldn't map interrupt\n"); 163 return; 164 } 165 intrstr = pci_intr_string(pc, ih); 166 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET | IPL_MPSAFE, re_intr, 167 sc, sc->sc_dev.dv_xname); 168 if (sc->sc_ih == NULL) { 169 printf(": couldn't establish interrupt"); 170 if (intrstr != NULL) 171 printf(" at %s", intrstr); 172 return; 173 } 174 175 sc->sc_dmat = pa->pa_dmat; 176 psc->sc_pc = pc; 177 178 /* 179 * PCI Express check. 180 */ 181 if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, 182 &offset, NULL)) { 183 /* Disable PCIe ASPM and ECPM. */ 184 reg = pci_conf_read(pc, pa->pa_tag, offset + PCI_PCIE_LCSR); 185 reg &= ~(PCI_PCIE_LCSR_ASPM_L0S | PCI_PCIE_LCSR_ASPM_L1 | 186 PCI_PCIE_LCSR_ECPM); 187 pci_conf_write(pc, pa->pa_tag, offset + PCI_PCIE_LCSR, reg); 188 sc->rl_flags |= RL_FLAG_PCIE; 189 } 190 191 if (!(PCI_VENDOR(pa->pa_id) == PCI_VENDOR_REALTEK && 192 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_REALTEK_RT8139)) { 193 u_int8_t cfg; 194 195 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 196 cfg = CSR_READ_1(sc, RL_CFG2); 197 if (sc->rl_flags & RL_FLAG_MSI) { 198 cfg |= RL_CFG2_MSI; 199 CSR_WRITE_1(sc, RL_CFG2, cfg); 200 } else { 201 if ((cfg & RL_CFG2_MSI) != 0) { 202 cfg &= ~RL_CFG2_MSI; 203 CSR_WRITE_1(sc, RL_CFG2, cfg); 204 } 205 } 206 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 207 } 208 209 sc->sc_product = PCI_PRODUCT(pa->pa_id); 210 211 /* Call bus-independent attach routine */ 212 if (re_attach(sc, intrstr)) { 213 pci_intr_disestablish(pc, sc->sc_ih); 214 bus_space_unmap(sc->rl_btag, sc->rl_bhandle, psc->sc_iosize); 215 } 216 } 217 218 int 219 re_pci_detach(struct device *self, int flags) 220 { 221 struct re_pci_softc *psc = (struct re_pci_softc *)self; 222 struct rl_softc *sc = &psc->sc_rl; 223 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 224 225 /* Remove timeout handler */ 226 timeout_del(&sc->timer_handle); 227 228 /* Detach PHY */ 229 if (LIST_FIRST(&sc->sc_mii.mii_phys) != NULL) 230 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 231 232 /* Delete media stuff */ 233 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 234 ether_ifdetach(ifp); 235 if_detach(ifp); 236 237 /* Disable interrupts */ 238 if (sc->sc_ih != NULL) 239 pci_intr_disestablish(psc->sc_pc, sc->sc_ih); 240 241 /* Free pci resources */ 242 bus_space_unmap(sc->rl_btag, sc->rl_bhandle, psc->sc_iosize); 243 244 return (0); 245 } 246 247 int 248 re_pci_activate(struct device *self, int act) 249 { 250 struct re_pci_softc *psc = (struct re_pci_softc *)self; 251 struct rl_softc *sc = &psc->sc_rl; 252 struct ifnet *ifp = &sc->sc_arpcom.ac_if; 253 254 switch (act) { 255 case DVACT_SUSPEND: 256 if (ifp->if_flags & IFF_RUNNING) 257 re_stop(ifp); 258 break; 259 case DVACT_RESUME: 260 if (ifp->if_flags & IFF_UP) 261 re_init(ifp); 262 break; 263 } 264 265 return (0); 266 } 267