1 /*
2 * ARM kernel loader.
3 *
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
6 *
7 * This code is licensed under the GPL.
8 */
9
10 #include "qemu/osdep.h"
11 #include "qemu/datadir.h"
12 #include "qemu/error-report.h"
13 #include "qapi/error.h"
14 #include <libfdt.h>
15 #include "hw/arm/boot.h"
16 #include "hw/arm/linux-boot-if.h"
17 #include "sysemu/kvm.h"
18 #include "sysemu/tcg.h"
19 #include "sysemu/sysemu.h"
20 #include "sysemu/numa.h"
21 #include "hw/boards.h"
22 #include "sysemu/reset.h"
23 #include "hw/loader.h"
24 #include "elf.h"
25 #include "sysemu/device_tree.h"
26 #include "qemu/config-file.h"
27 #include "qemu/option.h"
28 #include "qemu/units.h"
29
30 /* Kernel boot protocol is specified in the kernel docs
31 * Documentation/arm/Booting and Documentation/arm64/booting.txt
32 * They have different preferred image load offsets from system RAM base.
33 */
34 #define KERNEL_ARGS_ADDR 0x100
35 #define KERNEL_NOLOAD_ADDR 0x02000000
36 #define KERNEL_LOAD_ADDR 0x00010000
37 #define KERNEL64_LOAD_ADDR 0x00080000
38
39 #define ARM64_TEXT_OFFSET_OFFSET 8
40 #define ARM64_MAGIC_OFFSET 56
41
42 #define BOOTLOADER_MAX_SIZE (4 * KiB)
43
arm_boot_address_space(ARMCPU * cpu,const struct arm_boot_info * info)44 AddressSpace *arm_boot_address_space(ARMCPU *cpu,
45 const struct arm_boot_info *info)
46 {
47 /* Return the address space to use for bootloader reads and writes.
48 * We prefer the secure address space if the CPU has it and we're
49 * going to boot the guest into it.
50 */
51 int asidx;
52 CPUState *cs = CPU(cpu);
53
54 if (arm_feature(&cpu->env, ARM_FEATURE_EL3) && info->secure_boot) {
55 asidx = ARMASIdx_S;
56 } else {
57 asidx = ARMASIdx_NS;
58 }
59
60 return cpu_get_address_space(cs, asidx);
61 }
62
63 static const ARMInsnFixup bootloader_aarch64[] = {
64 { 0x580000c0 }, /* ldr x0, arg ; Load the lower 32-bits of DTB */
65 { 0xaa1f03e1 }, /* mov x1, xzr */
66 { 0xaa1f03e2 }, /* mov x2, xzr */
67 { 0xaa1f03e3 }, /* mov x3, xzr */
68 { 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */
69 { 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */
70 { 0, FIXUP_ARGPTR_LO }, /* arg: .word @DTB Lower 32-bits */
71 { 0, FIXUP_ARGPTR_HI}, /* .word @DTB Higher 32-bits */
72 { 0, FIXUP_ENTRYPOINT_LO }, /* entry: .word @Kernel Entry Lower 32-bits */
73 { 0, FIXUP_ENTRYPOINT_HI }, /* .word @Kernel Entry Higher 32-bits */
74 { 0, FIXUP_TERMINATOR }
75 };
76
77 /* A very small bootloader: call the board-setup code (if needed),
78 * set r0-r2, then jump to the kernel.
79 * If we're not calling boot setup code then we don't copy across
80 * the first BOOTLOADER_NO_BOARD_SETUP_OFFSET insns in this array.
81 */
82
83 static const ARMInsnFixup bootloader[] = {
84 { 0xe28fe004 }, /* add lr, pc, #4 */
85 { 0xe51ff004 }, /* ldr pc, [pc, #-4] */
86 { 0, FIXUP_BOARD_SETUP },
87 #define BOOTLOADER_NO_BOARD_SETUP_OFFSET 3
88 { 0xe3a00000 }, /* mov r0, #0 */
89 { 0xe59f1004 }, /* ldr r1, [pc, #4] */
90 { 0xe59f2004 }, /* ldr r2, [pc, #4] */
91 { 0xe59ff004 }, /* ldr pc, [pc, #4] */
92 { 0, FIXUP_BOARDID },
93 { 0, FIXUP_ARGPTR_LO },
94 { 0, FIXUP_ENTRYPOINT_LO },
95 { 0, FIXUP_TERMINATOR }
96 };
97
98 /* Handling for secondary CPU boot in a multicore system.
99 * Unlike the uniprocessor/primary CPU boot, this is platform
100 * dependent. The default code here is based on the secondary
101 * CPU boot protocol used on realview/vexpress boards, with
102 * some parameterisation to increase its flexibility.
103 * QEMU platform models for which this code is not appropriate
104 * should override write_secondary_boot and secondary_cpu_reset_hook
105 * instead.
106 *
107 * This code enables the interrupt controllers for the secondary
108 * CPUs and then puts all the secondary CPUs into a loop waiting
109 * for an interprocessor interrupt and polling a configurable
110 * location for the kernel secondary CPU entry point.
111 */
112 #define DSB_INSN 0xf57ff04f
113 #define CP15_DSB_INSN 0xee070f9a /* mcr cp15, 0, r0, c7, c10, 4 */
114
115 static const ARMInsnFixup smpboot[] = {
116 { 0xe59f2028 }, /* ldr r2, gic_cpu_if */
117 { 0xe59f0028 }, /* ldr r0, bootreg_addr */
118 { 0xe3a01001 }, /* mov r1, #1 */
119 { 0xe5821000 }, /* str r1, [r2] - set GICC_CTLR.Enable */
120 { 0xe3a010ff }, /* mov r1, #0xff */
121 { 0xe5821004 }, /* str r1, [r2, 4] - set GIC_PMR.Priority to 0xff */
122 { 0, FIXUP_DSB }, /* dsb */
123 { 0xe320f003 }, /* wfi */
124 { 0xe5901000 }, /* ldr r1, [r0] */
125 { 0xe1110001 }, /* tst r1, r1 */
126 { 0x0afffffb }, /* beq <wfi> */
127 { 0xe12fff11 }, /* bx r1 */
128 { 0, FIXUP_GIC_CPU_IF }, /* gic_cpu_if: .word 0x.... */
129 { 0, FIXUP_BOOTREG }, /* bootreg_addr: .word 0x.... */
130 { 0, FIXUP_TERMINATOR }
131 };
132
arm_write_bootloader(const char * name,AddressSpace * as,hwaddr addr,const ARMInsnFixup * insns,const uint32_t * fixupcontext)133 void arm_write_bootloader(const char *name,
134 AddressSpace *as, hwaddr addr,
135 const ARMInsnFixup *insns,
136 const uint32_t *fixupcontext)
137 {
138 /* Fix up the specified bootloader fragment and write it into
139 * guest memory using rom_add_blob_fixed(). fixupcontext is
140 * an array giving the values to write in for the fixup types
141 * which write a value into the code array.
142 */
143 int i, len;
144 uint32_t *code;
145
146 len = 0;
147 while (insns[len].fixup != FIXUP_TERMINATOR) {
148 len++;
149 }
150
151 code = g_new0(uint32_t, len);
152
153 for (i = 0; i < len; i++) {
154 uint32_t insn = insns[i].insn;
155 FixupType fixup = insns[i].fixup;
156
157 switch (fixup) {
158 case FIXUP_NONE:
159 break;
160 case FIXUP_BOARDID:
161 case FIXUP_BOARD_SETUP:
162 case FIXUP_ARGPTR_LO:
163 case FIXUP_ARGPTR_HI:
164 case FIXUP_ENTRYPOINT_LO:
165 case FIXUP_ENTRYPOINT_HI:
166 case FIXUP_GIC_CPU_IF:
167 case FIXUP_BOOTREG:
168 case FIXUP_DSB:
169 insn = fixupcontext[fixup];
170 break;
171 default:
172 abort();
173 }
174 code[i] = tswap32(insn);
175 }
176
177 assert((len * sizeof(uint32_t)) < BOOTLOADER_MAX_SIZE);
178
179 rom_add_blob_fixed_as(name, code, len * sizeof(uint32_t), addr, as);
180
181 g_free(code);
182 }
183
default_write_secondary(ARMCPU * cpu,const struct arm_boot_info * info)184 static void default_write_secondary(ARMCPU *cpu,
185 const struct arm_boot_info *info)
186 {
187 uint32_t fixupcontext[FIXUP_MAX];
188 AddressSpace *as = arm_boot_address_space(cpu, info);
189
190 fixupcontext[FIXUP_GIC_CPU_IF] = info->gic_cpu_if_addr;
191 fixupcontext[FIXUP_BOOTREG] = info->smp_bootreg_addr;
192 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
193 fixupcontext[FIXUP_DSB] = DSB_INSN;
194 } else {
195 fixupcontext[FIXUP_DSB] = CP15_DSB_INSN;
196 }
197
198 arm_write_bootloader("smpboot", as, info->smp_loader_start,
199 smpboot, fixupcontext);
200 }
201
arm_write_secure_board_setup_dummy_smc(ARMCPU * cpu,const struct arm_boot_info * info,hwaddr mvbar_addr)202 void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
203 const struct arm_boot_info *info,
204 hwaddr mvbar_addr)
205 {
206 AddressSpace *as = arm_boot_address_space(cpu, info);
207 int n;
208 uint32_t mvbar_blob[] = {
209 /* mvbar_addr: secure monitor vectors
210 * Default unimplemented and unused vectors to spin. Makes it
211 * easier to debug (as opposed to the CPU running away).
212 */
213 0xeafffffe, /* (spin) */
214 0xeafffffe, /* (spin) */
215 0xe1b0f00e, /* movs pc, lr ;SMC exception return */
216 0xeafffffe, /* (spin) */
217 0xeafffffe, /* (spin) */
218 0xeafffffe, /* (spin) */
219 0xeafffffe, /* (spin) */
220 0xeafffffe, /* (spin) */
221 };
222 uint32_t board_setup_blob[] = {
223 /* board setup addr */
224 0xee110f51, /* mrc p15, 0, r0, c1, c1, 2 ;read NSACR */
225 0xe3800b03, /* orr r0, #0xc00 ;set CP11, CP10 */
226 0xee010f51, /* mcr p15, 0, r0, c1, c1, 2 ;write NSACR */
227 0xe3a00e00 + (mvbar_addr >> 4), /* mov r0, #mvbar_addr */
228 0xee0c0f30, /* mcr p15, 0, r0, c12, c0, 1 ;set MVBAR */
229 0xee110f11, /* mrc p15, 0, r0, c1 , c1, 0 ;read SCR */
230 0xe3800031, /* orr r0, #0x31 ;enable AW, FW, NS */
231 0xee010f11, /* mcr p15, 0, r0, c1, c1, 0 ;write SCR */
232 0xe1a0100e, /* mov r1, lr ;save LR across SMC */
233 0xe1600070, /* smc #0 ;call monitor to flush SCR */
234 0xe1a0f001, /* mov pc, r1 ;return */
235 };
236
237 /* check that mvbar_addr is correctly aligned and relocatable (using MOV) */
238 assert((mvbar_addr & 0x1f) == 0 && (mvbar_addr >> 4) < 0x100);
239
240 /* check that these blobs don't overlap */
241 assert((mvbar_addr + sizeof(mvbar_blob) <= info->board_setup_addr)
242 || (info->board_setup_addr + sizeof(board_setup_blob) <= mvbar_addr));
243
244 for (n = 0; n < ARRAY_SIZE(mvbar_blob); n++) {
245 mvbar_blob[n] = tswap32(mvbar_blob[n]);
246 }
247 rom_add_blob_fixed_as("board-setup-mvbar", mvbar_blob, sizeof(mvbar_blob),
248 mvbar_addr, as);
249
250 for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) {
251 board_setup_blob[n] = tswap32(board_setup_blob[n]);
252 }
253 rom_add_blob_fixed_as("board-setup", board_setup_blob,
254 sizeof(board_setup_blob), info->board_setup_addr, as);
255 }
256
default_reset_secondary(ARMCPU * cpu,const struct arm_boot_info * info)257 static void default_reset_secondary(ARMCPU *cpu,
258 const struct arm_boot_info *info)
259 {
260 AddressSpace *as = arm_boot_address_space(cpu, info);
261 CPUState *cs = CPU(cpu);
262
263 address_space_stl_notdirty(as, info->smp_bootreg_addr,
264 0, MEMTXATTRS_UNSPECIFIED, NULL);
265 cpu_set_pc(cs, info->smp_loader_start);
266 }
267
have_dtb(const struct arm_boot_info * info)268 static inline bool have_dtb(const struct arm_boot_info *info)
269 {
270 return info->dtb_filename || info->get_dtb;
271 }
272
273 #define WRITE_WORD(p, value) do { \
274 address_space_stl_notdirty(as, p, value, \
275 MEMTXATTRS_UNSPECIFIED, NULL); \
276 p += 4; \
277 } while (0)
278
set_kernel_args(const struct arm_boot_info * info,AddressSpace * as)279 static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as)
280 {
281 int initrd_size = info->initrd_size;
282 hwaddr base = info->loader_start;
283 hwaddr p;
284
285 p = base + KERNEL_ARGS_ADDR;
286 /* ATAG_CORE */
287 WRITE_WORD(p, 5);
288 WRITE_WORD(p, 0x54410001);
289 WRITE_WORD(p, 1);
290 WRITE_WORD(p, 0x1000);
291 WRITE_WORD(p, 0);
292 /* ATAG_MEM */
293 /* TODO: handle multiple chips on one ATAG list */
294 WRITE_WORD(p, 4);
295 WRITE_WORD(p, 0x54410002);
296 WRITE_WORD(p, info->ram_size);
297 WRITE_WORD(p, info->loader_start);
298 if (initrd_size) {
299 /* ATAG_INITRD2 */
300 WRITE_WORD(p, 4);
301 WRITE_WORD(p, 0x54420005);
302 WRITE_WORD(p, info->initrd_start);
303 WRITE_WORD(p, initrd_size);
304 }
305 if (info->kernel_cmdline && *info->kernel_cmdline) {
306 /* ATAG_CMDLINE */
307 int cmdline_size;
308
309 cmdline_size = strlen(info->kernel_cmdline);
310 address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED,
311 info->kernel_cmdline, cmdline_size + 1);
312 cmdline_size = (cmdline_size >> 2) + 1;
313 WRITE_WORD(p, cmdline_size + 2);
314 WRITE_WORD(p, 0x54410009);
315 p += cmdline_size * 4;
316 }
317 if (info->atag_board) {
318 /* ATAG_BOARD */
319 int atag_board_len;
320 uint8_t atag_board_buf[0x1000];
321
322 atag_board_len = (info->atag_board(info, atag_board_buf) + 3) & ~3;
323 WRITE_WORD(p, (atag_board_len + 8) >> 2);
324 WRITE_WORD(p, 0x414f4d50);
325 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED,
326 atag_board_buf, atag_board_len);
327 p += atag_board_len;
328 }
329 /* ATAG_END */
330 WRITE_WORD(p, 0);
331 WRITE_WORD(p, 0);
332 }
333
set_kernel_args_old(const struct arm_boot_info * info,AddressSpace * as)334 static void set_kernel_args_old(const struct arm_boot_info *info,
335 AddressSpace *as)
336 {
337 hwaddr p;
338 const char *s;
339 int initrd_size = info->initrd_size;
340 hwaddr base = info->loader_start;
341
342 /* see linux/include/asm-arm/setup.h */
343 p = base + KERNEL_ARGS_ADDR;
344 /* page_size */
345 WRITE_WORD(p, 4096);
346 /* nr_pages */
347 WRITE_WORD(p, info->ram_size / 4096);
348 /* ramdisk_size */
349 WRITE_WORD(p, 0);
350 #define FLAG_READONLY 1
351 #define FLAG_RDLOAD 4
352 #define FLAG_RDPROMPT 8
353 /* flags */
354 WRITE_WORD(p, FLAG_READONLY | FLAG_RDLOAD | FLAG_RDPROMPT);
355 /* rootdev */
356 WRITE_WORD(p, (31 << 8) | 0); /* /dev/mtdblock0 */
357 /* video_num_cols */
358 WRITE_WORD(p, 0);
359 /* video_num_rows */
360 WRITE_WORD(p, 0);
361 /* video_x */
362 WRITE_WORD(p, 0);
363 /* video_y */
364 WRITE_WORD(p, 0);
365 /* memc_control_reg */
366 WRITE_WORD(p, 0);
367 /* unsigned char sounddefault */
368 /* unsigned char adfsdrives */
369 /* unsigned char bytes_per_char_h */
370 /* unsigned char bytes_per_char_v */
371 WRITE_WORD(p, 0);
372 /* pages_in_bank[4] */
373 WRITE_WORD(p, 0);
374 WRITE_WORD(p, 0);
375 WRITE_WORD(p, 0);
376 WRITE_WORD(p, 0);
377 /* pages_in_vram */
378 WRITE_WORD(p, 0);
379 /* initrd_start */
380 if (initrd_size) {
381 WRITE_WORD(p, info->initrd_start);
382 } else {
383 WRITE_WORD(p, 0);
384 }
385 /* initrd_size */
386 WRITE_WORD(p, initrd_size);
387 /* rd_start */
388 WRITE_WORD(p, 0);
389 /* system_rev */
390 WRITE_WORD(p, 0);
391 /* system_serial_low */
392 WRITE_WORD(p, 0);
393 /* system_serial_high */
394 WRITE_WORD(p, 0);
395 /* mem_fclk_21285 */
396 WRITE_WORD(p, 0);
397 /* zero unused fields */
398 while (p < base + KERNEL_ARGS_ADDR + 256 + 1024) {
399 WRITE_WORD(p, 0);
400 }
401 s = info->kernel_cmdline;
402 if (s) {
403 address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, s, strlen(s) + 1);
404 } else {
405 WRITE_WORD(p, 0);
406 }
407 }
408
fdt_add_memory_node(void * fdt,uint32_t acells,hwaddr mem_base,uint32_t scells,hwaddr mem_len,int numa_node_id)409 static int fdt_add_memory_node(void *fdt, uint32_t acells, hwaddr mem_base,
410 uint32_t scells, hwaddr mem_len,
411 int numa_node_id)
412 {
413 char *nodename;
414 int ret;
415
416 nodename = g_strdup_printf("/memory@%" PRIx64, mem_base);
417 qemu_fdt_add_subnode(fdt, nodename);
418 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
419 ret = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", acells, mem_base,
420 scells, mem_len);
421 if (ret < 0) {
422 goto out;
423 }
424
425 /* only set the NUMA ID if it is specified */
426 if (numa_node_id >= 0) {
427 ret = qemu_fdt_setprop_cell(fdt, nodename,
428 "numa-node-id", numa_node_id);
429 }
430 out:
431 g_free(nodename);
432 return ret;
433 }
434
fdt_add_psci_node(void * fdt)435 static void fdt_add_psci_node(void *fdt)
436 {
437 uint32_t cpu_suspend_fn;
438 uint32_t cpu_off_fn;
439 uint32_t cpu_on_fn;
440 uint32_t migrate_fn;
441 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0));
442 const char *psci_method;
443 int64_t psci_conduit;
444 int rc;
445
446 psci_conduit = object_property_get_int(OBJECT(armcpu),
447 "psci-conduit",
448 &error_abort);
449 switch (psci_conduit) {
450 case QEMU_PSCI_CONDUIT_DISABLED:
451 return;
452 case QEMU_PSCI_CONDUIT_HVC:
453 psci_method = "hvc";
454 break;
455 case QEMU_PSCI_CONDUIT_SMC:
456 psci_method = "smc";
457 break;
458 default:
459 g_assert_not_reached();
460 }
461
462 /*
463 * A pre-existing /psci node might specify function ID values
464 * that don't match QEMU's PSCI implementation. Delete the whole
465 * node and put our own in instead.
466 */
467 rc = fdt_path_offset(fdt, "/psci");
468 if (rc >= 0) {
469 qemu_fdt_nop_node(fdt, "/psci");
470 }
471
472 qemu_fdt_add_subnode(fdt, "/psci");
473 if (armcpu->psci_version >= QEMU_PSCI_VERSION_0_2) {
474 if (armcpu->psci_version < QEMU_PSCI_VERSION_1_0) {
475 const char comp[] = "arm,psci-0.2\0arm,psci";
476 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp));
477 } else {
478 const char comp[] = "arm,psci-1.0\0arm,psci-0.2\0arm,psci";
479 qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp));
480 }
481
482 cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF;
483 if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) {
484 cpu_suspend_fn = QEMU_PSCI_0_2_FN64_CPU_SUSPEND;
485 cpu_on_fn = QEMU_PSCI_0_2_FN64_CPU_ON;
486 migrate_fn = QEMU_PSCI_0_2_FN64_MIGRATE;
487 } else {
488 cpu_suspend_fn = QEMU_PSCI_0_2_FN_CPU_SUSPEND;
489 cpu_on_fn = QEMU_PSCI_0_2_FN_CPU_ON;
490 migrate_fn = QEMU_PSCI_0_2_FN_MIGRATE;
491 }
492 } else {
493 qemu_fdt_setprop_string(fdt, "/psci", "compatible", "arm,psci");
494
495 cpu_suspend_fn = QEMU_PSCI_0_1_FN_CPU_SUSPEND;
496 cpu_off_fn = QEMU_PSCI_0_1_FN_CPU_OFF;
497 cpu_on_fn = QEMU_PSCI_0_1_FN_CPU_ON;
498 migrate_fn = QEMU_PSCI_0_1_FN_MIGRATE;
499 }
500
501 /* We adopt the PSCI spec's nomenclature, and use 'conduit' to refer
502 * to the instruction that should be used to invoke PSCI functions.
503 * However, the device tree binding uses 'method' instead, so that is
504 * what we should use here.
505 */
506 qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method);
507
508 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn);
509 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn);
510 qemu_fdt_setprop_cell(fdt, "/psci", "cpu_on", cpu_on_fn);
511 qemu_fdt_setprop_cell(fdt, "/psci", "migrate", migrate_fn);
512 }
513
arm_load_dtb(hwaddr addr,const struct arm_boot_info * binfo,hwaddr addr_limit,AddressSpace * as,MachineState * ms)514 int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
515 hwaddr addr_limit, AddressSpace *as, MachineState *ms)
516 {
517 void *fdt = NULL;
518 int size, rc, n = 0;
519 uint32_t acells, scells;
520 unsigned int i;
521 hwaddr mem_base, mem_len;
522 char **node_path;
523 Error *err = NULL;
524
525 if (binfo->dtb_filename) {
526 char *filename;
527 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, binfo->dtb_filename);
528 if (!filename) {
529 fprintf(stderr, "Couldn't open dtb file %s\n", binfo->dtb_filename);
530 goto fail;
531 }
532
533 fdt = load_device_tree(filename, &size);
534 if (!fdt) {
535 fprintf(stderr, "Couldn't open dtb file %s\n", filename);
536 g_free(filename);
537 goto fail;
538 }
539 g_free(filename);
540 } else {
541 fdt = binfo->get_dtb(binfo, &size);
542 if (!fdt) {
543 fprintf(stderr, "Board was unable to create a dtb blob\n");
544 goto fail;
545 }
546 }
547
548 if (addr_limit > addr && size > (addr_limit - addr)) {
549 /* Installing the device tree blob at addr would exceed addr_limit.
550 * Whether this constitutes failure is up to the caller to decide,
551 * so just return 0 as size, i.e., no error.
552 */
553 g_free(fdt);
554 return 0;
555 }
556
557 acells = qemu_fdt_getprop_cell(fdt, "/", "#address-cells",
558 NULL, &error_fatal);
559 scells = qemu_fdt_getprop_cell(fdt, "/", "#size-cells",
560 NULL, &error_fatal);
561 if (acells == 0 || scells == 0) {
562 fprintf(stderr, "dtb file invalid (#address-cells or #size-cells 0)\n");
563 goto fail;
564 }
565
566 if (scells < 2 && binfo->ram_size >= 4 * GiB) {
567 /* This is user error so deserves a friendlier error message
568 * than the failure of setprop_sized_cells would provide
569 */
570 fprintf(stderr, "qemu: dtb file not compatible with "
571 "RAM size > 4GB\n");
572 goto fail;
573 }
574
575 /* nop all root nodes matching /memory or /memory@unit-address */
576 node_path = qemu_fdt_node_unit_path(fdt, "memory", &err);
577 if (err) {
578 error_report_err(err);
579 goto fail;
580 }
581 while (node_path[n]) {
582 if (g_str_has_prefix(node_path[n], "/memory")) {
583 qemu_fdt_nop_node(fdt, node_path[n]);
584 }
585 n++;
586 }
587 g_strfreev(node_path);
588
589 /*
590 * We drop all the memory nodes which correspond to empty NUMA nodes
591 * from the device tree, because the Linux NUMA binding document
592 * states they should not be generated. Linux will get the NUMA node
593 * IDs of the empty NUMA nodes from the distance map if they are needed.
594 * This means QEMU users may be obliged to provide command lines which
595 * configure distance maps when the empty NUMA node IDs are needed and
596 * Linux's default distance map isn't sufficient.
597 */
598 if (ms->numa_state != NULL && ms->numa_state->num_nodes > 0) {
599 mem_base = binfo->loader_start;
600 for (i = 0; i < ms->numa_state->num_nodes; i++) {
601 mem_len = ms->numa_state->nodes[i].node_mem;
602 if (!mem_len) {
603 continue;
604 }
605
606 rc = fdt_add_memory_node(fdt, acells, mem_base,
607 scells, mem_len, i);
608 if (rc < 0) {
609 fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n",
610 mem_base);
611 goto fail;
612 }
613
614 mem_base += mem_len;
615 }
616 } else {
617 rc = fdt_add_memory_node(fdt, acells, binfo->loader_start,
618 scells, binfo->ram_size, -1);
619 if (rc < 0) {
620 fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n",
621 binfo->loader_start);
622 goto fail;
623 }
624 }
625
626 rc = fdt_path_offset(fdt, "/chosen");
627 if (rc < 0) {
628 qemu_fdt_add_subnode(fdt, "/chosen");
629 }
630
631 if (ms->kernel_cmdline && *ms->kernel_cmdline) {
632 rc = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
633 ms->kernel_cmdline);
634 if (rc < 0) {
635 fprintf(stderr, "couldn't set /chosen/bootargs\n");
636 goto fail;
637 }
638 }
639
640 if (binfo->initrd_size) {
641 rc = qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-start",
642 acells, binfo->initrd_start);
643 if (rc < 0) {
644 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
645 goto fail;
646 }
647
648 rc = qemu_fdt_setprop_sized_cells(fdt, "/chosen", "linux,initrd-end",
649 acells,
650 binfo->initrd_start +
651 binfo->initrd_size);
652 if (rc < 0) {
653 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
654 goto fail;
655 }
656 }
657
658 fdt_add_psci_node(fdt);
659
660 if (binfo->modify_dtb) {
661 binfo->modify_dtb(binfo, fdt);
662 }
663
664 qemu_fdt_dumpdtb(fdt, size);
665
666 /* Put the DTB into the memory map as a ROM image: this will ensure
667 * the DTB is copied again upon reset, even if addr points into RAM.
668 */
669 rom_add_blob_fixed_as("dtb", fdt, size, addr, as);
670 qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds,
671 rom_ptr_for_as(as, addr, size));
672
673 if (fdt != ms->fdt) {
674 g_free(ms->fdt);
675 ms->fdt = fdt;
676 }
677
678 return size;
679
680 fail:
681 g_free(fdt);
682 return -1;
683 }
684
do_cpu_reset(void * opaque)685 static void do_cpu_reset(void *opaque)
686 {
687 ARMCPU *cpu = opaque;
688 CPUState *cs = CPU(cpu);
689 CPUARMState *env = &cpu->env;
690 const struct arm_boot_info *info = env->boot_info;
691
692 cpu_reset(cs);
693 if (info) {
694 if (!info->is_linux) {
695 int i;
696 /* Jump to the entry point. */
697 uint64_t entry = info->entry;
698
699 switch (info->endianness) {
700 case ARM_ENDIANNESS_LE:
701 env->cp15.sctlr_el[1] &= ~SCTLR_E0E;
702 for (i = 1; i < 4; ++i) {
703 env->cp15.sctlr_el[i] &= ~SCTLR_EE;
704 }
705 env->uncached_cpsr &= ~CPSR_E;
706 break;
707 case ARM_ENDIANNESS_BE8:
708 env->cp15.sctlr_el[1] |= SCTLR_E0E;
709 for (i = 1; i < 4; ++i) {
710 env->cp15.sctlr_el[i] |= SCTLR_EE;
711 }
712 env->uncached_cpsr |= CPSR_E;
713 break;
714 case ARM_ENDIANNESS_BE32:
715 env->cp15.sctlr_el[1] |= SCTLR_B;
716 break;
717 case ARM_ENDIANNESS_UNKNOWN:
718 break; /* Board's decision */
719 default:
720 g_assert_not_reached();
721 }
722
723 cpu_set_pc(cs, entry);
724 } else {
725 /*
726 * If we are booting Linux then we might need to do so at:
727 * - AArch64 NS EL2 or NS EL1
728 * - AArch32 Secure SVC (EL3)
729 * - AArch32 NS Hyp (EL2)
730 * - AArch32 NS SVC (EL1)
731 * Configure the CPU in the way boot firmware would do to
732 * drop us down to the appropriate level.
733 */
734 int target_el = arm_feature(env, ARM_FEATURE_EL2) ? 2 : 1;
735
736 if (env->aarch64) {
737 /*
738 * AArch64 kernels never boot in secure mode, and we don't
739 * support the secure_board_setup hook for AArch64.
740 */
741 assert(!info->secure_boot);
742 assert(!info->secure_board_setup);
743 } else {
744 if (arm_feature(env, ARM_FEATURE_EL3) &&
745 (info->secure_boot ||
746 (info->secure_board_setup && cs == first_cpu))) {
747 /* Start this CPU in Secure SVC */
748 target_el = 3;
749 }
750 }
751
752 arm_emulate_firmware_reset(cs, target_el);
753
754 if (cs == first_cpu) {
755 AddressSpace *as = arm_boot_address_space(cpu, info);
756
757 cpu_set_pc(cs, info->loader_start);
758
759 if (!have_dtb(info)) {
760 if (old_param) {
761 set_kernel_args_old(info, as);
762 } else {
763 set_kernel_args(info, as);
764 }
765 }
766 } else if (info->secondary_cpu_reset_hook) {
767 info->secondary_cpu_reset_hook(cpu, info);
768 }
769 }
770
771 if (tcg_enabled()) {
772 arm_rebuild_hflags(env);
773 }
774 }
775 }
776
do_arm_linux_init(Object * obj,void * opaque)777 static int do_arm_linux_init(Object *obj, void *opaque)
778 {
779 if (object_dynamic_cast(obj, TYPE_ARM_LINUX_BOOT_IF)) {
780 ARMLinuxBootIf *albif = ARM_LINUX_BOOT_IF(obj);
781 ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_GET_CLASS(obj);
782 struct arm_boot_info *info = opaque;
783
784 if (albifc->arm_linux_init) {
785 albifc->arm_linux_init(albif, info->secure_boot);
786 }
787 }
788 return 0;
789 }
790
arm_load_elf(struct arm_boot_info * info,uint64_t * pentry,uint64_t * lowaddr,uint64_t * highaddr,int elf_machine,AddressSpace * as)791 static ssize_t arm_load_elf(struct arm_boot_info *info, uint64_t *pentry,
792 uint64_t *lowaddr, uint64_t *highaddr,
793 int elf_machine, AddressSpace *as)
794 {
795 bool elf_is64;
796 union {
797 Elf32_Ehdr h32;
798 Elf64_Ehdr h64;
799 } elf_header;
800 int data_swab = 0;
801 bool big_endian;
802 ssize_t ret;
803 Error *err = NULL;
804
805
806 load_elf_hdr(info->kernel_filename, &elf_header, &elf_is64, &err);
807 if (err) {
808 /*
809 * If the file is not an ELF file we silently return.
810 * The caller will fall back to try other formats.
811 */
812 error_free(err);
813 return -1;
814 }
815
816 if (elf_is64) {
817 big_endian = elf_header.h64.e_ident[EI_DATA] == ELFDATA2MSB;
818 info->endianness = big_endian ? ARM_ENDIANNESS_BE8
819 : ARM_ENDIANNESS_LE;
820 } else {
821 big_endian = elf_header.h32.e_ident[EI_DATA] == ELFDATA2MSB;
822 if (big_endian) {
823 if (bswap32(elf_header.h32.e_flags) & EF_ARM_BE8) {
824 info->endianness = ARM_ENDIANNESS_BE8;
825 } else {
826 info->endianness = ARM_ENDIANNESS_BE32;
827 /* In BE32, the CPU has a different view of the per-byte
828 * address map than the rest of the system. BE32 ELF files
829 * are organised such that they can be programmed through
830 * the CPU's per-word byte-reversed view of the world. QEMU
831 * however loads ELF files independently of the CPU. So
832 * tell the ELF loader to byte reverse the data for us.
833 */
834 data_swab = 2;
835 }
836 } else {
837 info->endianness = ARM_ENDIANNESS_LE;
838 }
839 }
840
841 ret = load_elf_as(info->kernel_filename, NULL, NULL, NULL,
842 pentry, lowaddr, highaddr, NULL, big_endian, elf_machine,
843 1, data_swab, as);
844 if (ret <= 0) {
845 /* The header loaded but the image didn't */
846 error_report("Couldn't load elf '%s': %s",
847 info->kernel_filename, load_elf_strerror(ret));
848 exit(1);
849 }
850
851 return ret;
852 }
853
load_aarch64_image(const char * filename,hwaddr mem_base,hwaddr * entry,AddressSpace * as)854 static uint64_t load_aarch64_image(const char *filename, hwaddr mem_base,
855 hwaddr *entry, AddressSpace *as)
856 {
857 hwaddr kernel_load_offset = KERNEL64_LOAD_ADDR;
858 uint64_t kernel_size = 0;
859 uint8_t *buffer;
860 int size;
861
862 /* On aarch64, it's the bootloader's job to uncompress the kernel. */
863 size = load_image_gzipped_buffer(filename, LOAD_IMAGE_MAX_GUNZIP_BYTES,
864 &buffer);
865
866 if (size < 0) {
867 gsize len;
868
869 /* Load as raw file otherwise */
870 if (!g_file_get_contents(filename, (char **)&buffer, &len, NULL)) {
871 return -1;
872 }
873 size = len;
874
875 /* Unpack the image if it is a EFI zboot image */
876 if (unpack_efi_zboot_image(&buffer, &size) < 0) {
877 g_free(buffer);
878 return -1;
879 }
880 }
881
882 /* check the arm64 magic header value -- very old kernels may not have it */
883 if (size > ARM64_MAGIC_OFFSET + 4 &&
884 memcmp(buffer + ARM64_MAGIC_OFFSET, "ARM\x64", 4) == 0) {
885 uint64_t hdrvals[2];
886
887 /* The arm64 Image header has text_offset and image_size fields at 8 and
888 * 16 bytes into the Image header, respectively. The text_offset field
889 * is only valid if the image_size is non-zero.
890 */
891 memcpy(&hdrvals, buffer + ARM64_TEXT_OFFSET_OFFSET, sizeof(hdrvals));
892
893 kernel_size = le64_to_cpu(hdrvals[1]);
894
895 if (kernel_size != 0) {
896 kernel_load_offset = le64_to_cpu(hdrvals[0]);
897
898 /*
899 * We write our startup "bootloader" at the very bottom of RAM,
900 * so that bit can't be used for the image. Luckily the Image
901 * format specification is that the image requests only an offset
902 * from a 2MB boundary, not an absolute load address. So if the
903 * image requests an offset that might mean it overlaps with the
904 * bootloader, we can just load it starting at 2MB+offset rather
905 * than 0MB + offset.
906 */
907 if (kernel_load_offset < BOOTLOADER_MAX_SIZE) {
908 kernel_load_offset += 2 * MiB;
909 }
910 }
911 }
912
913 /*
914 * Kernels before v3.17 don't populate the image_size field, and
915 * raw images have no header. For those our best guess at the size
916 * is the size of the Image file itself.
917 */
918 if (kernel_size == 0) {
919 kernel_size = size;
920 }
921
922 *entry = mem_base + kernel_load_offset;
923 rom_add_blob_fixed_as(filename, buffer, size, *entry, as);
924
925 g_free(buffer);
926
927 return kernel_size;
928 }
929
arm_setup_direct_kernel_boot(ARMCPU * cpu,struct arm_boot_info * info)930 static void arm_setup_direct_kernel_boot(ARMCPU *cpu,
931 struct arm_boot_info *info)
932 {
933 /* Set up for a direct boot of a kernel image file. */
934 CPUState *cs;
935 AddressSpace *as = arm_boot_address_space(cpu, info);
936 ssize_t kernel_size;
937 int initrd_size;
938 int is_linux = 0;
939 uint64_t elf_entry;
940 /* Addresses of first byte used and first byte not used by the image */
941 uint64_t image_low_addr = 0, image_high_addr = 0;
942 int elf_machine;
943 hwaddr entry;
944 static const ARMInsnFixup *primary_loader;
945 uint64_t ram_end = info->loader_start + info->ram_size;
946
947 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
948 primary_loader = bootloader_aarch64;
949 elf_machine = EM_AARCH64;
950 } else {
951 primary_loader = bootloader;
952 if (!info->write_board_setup) {
953 primary_loader += BOOTLOADER_NO_BOARD_SETUP_OFFSET;
954 }
955 elf_machine = EM_ARM;
956 }
957
958 /* Assume that raw images are linux kernels, and ELF images are not. */
959 kernel_size = arm_load_elf(info, &elf_entry, &image_low_addr,
960 &image_high_addr, elf_machine, as);
961 if (kernel_size > 0 && have_dtb(info)) {
962 /*
963 * If there is still some room left at the base of RAM, try and put
964 * the DTB there like we do for images loaded with -bios or -pflash.
965 */
966 if (image_low_addr > info->loader_start
967 || image_high_addr < info->loader_start) {
968 /*
969 * Set image_low_addr as address limit for arm_load_dtb if it may be
970 * pointing into RAM, otherwise pass '0' (no limit)
971 */
972 if (image_low_addr < info->loader_start) {
973 image_low_addr = 0;
974 }
975 info->dtb_start = info->loader_start;
976 info->dtb_limit = image_low_addr;
977 }
978 }
979 entry = elf_entry;
980 if (kernel_size < 0) {
981 uint64_t loadaddr = info->loader_start + KERNEL_NOLOAD_ADDR;
982 kernel_size = load_uimage_as(info->kernel_filename, &entry, &loadaddr,
983 &is_linux, NULL, NULL, as);
984 if (kernel_size >= 0) {
985 image_low_addr = loadaddr;
986 image_high_addr = image_low_addr + kernel_size;
987 }
988 }
989 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) {
990 kernel_size = load_aarch64_image(info->kernel_filename,
991 info->loader_start, &entry, as);
992 is_linux = 1;
993 if (kernel_size >= 0) {
994 image_low_addr = entry;
995 image_high_addr = image_low_addr + kernel_size;
996 }
997 } else if (kernel_size < 0) {
998 /* 32-bit ARM */
999 entry = info->loader_start + KERNEL_LOAD_ADDR;
1000 kernel_size = load_image_targphys_as(info->kernel_filename, entry,
1001 ram_end - KERNEL_LOAD_ADDR, as);
1002 is_linux = 1;
1003 if (kernel_size >= 0) {
1004 image_low_addr = entry;
1005 image_high_addr = image_low_addr + kernel_size;
1006 }
1007 }
1008 if (kernel_size < 0) {
1009 error_report("could not load kernel '%s'", info->kernel_filename);
1010 exit(1);
1011 }
1012
1013 if (kernel_size > info->ram_size) {
1014 error_report("kernel '%s' is too large to fit in RAM "
1015 "(kernel size %zd, RAM size %" PRId64 ")",
1016 info->kernel_filename, kernel_size, info->ram_size);
1017 exit(1);
1018 }
1019
1020 info->entry = entry;
1021
1022 /*
1023 * We want to put the initrd far enough into RAM that when the
1024 * kernel is uncompressed it will not clobber the initrd. However
1025 * on boards without much RAM we must ensure that we still leave
1026 * enough room for a decent sized initrd, and on boards with large
1027 * amounts of RAM we must avoid the initrd being so far up in RAM
1028 * that it is outside lowmem and inaccessible to the kernel.
1029 * So for boards with less than 256MB of RAM we put the initrd
1030 * halfway into RAM, and for boards with 256MB of RAM or more we put
1031 * the initrd at 128MB.
1032 * We also refuse to put the initrd somewhere that will definitely
1033 * overlay the kernel we just loaded, though for kernel formats which
1034 * don't tell us their exact size (eg self-decompressing 32-bit kernels)
1035 * we might still make a bad choice here.
1036 */
1037 info->initrd_start = info->loader_start +
1038 MIN(info->ram_size / 2, 128 * MiB);
1039 if (image_high_addr) {
1040 info->initrd_start = MAX(info->initrd_start, image_high_addr);
1041 }
1042 info->initrd_start = TARGET_PAGE_ALIGN(info->initrd_start);
1043
1044 if (is_linux) {
1045 uint32_t fixupcontext[FIXUP_MAX];
1046
1047 if (info->initrd_filename) {
1048
1049 if (info->initrd_start >= ram_end) {
1050 error_report("not enough space after kernel to load initrd");
1051 exit(1);
1052 }
1053
1054 initrd_size = load_ramdisk_as(info->initrd_filename,
1055 info->initrd_start,
1056 ram_end - info->initrd_start, as);
1057 if (initrd_size < 0) {
1058 initrd_size = load_image_targphys_as(info->initrd_filename,
1059 info->initrd_start,
1060 ram_end -
1061 info->initrd_start,
1062 as);
1063 }
1064 if (initrd_size < 0) {
1065 error_report("could not load initrd '%s'",
1066 info->initrd_filename);
1067 exit(1);
1068 }
1069 if (info->initrd_start + initrd_size > ram_end) {
1070 error_report("could not load initrd '%s': "
1071 "too big to fit into RAM after the kernel",
1072 info->initrd_filename);
1073 exit(1);
1074 }
1075 } else {
1076 initrd_size = 0;
1077 }
1078 info->initrd_size = initrd_size;
1079
1080 fixupcontext[FIXUP_BOARDID] = info->board_id;
1081 fixupcontext[FIXUP_BOARD_SETUP] = info->board_setup_addr;
1082
1083 /*
1084 * for device tree boot, we pass the DTB directly in r2. Otherwise
1085 * we point to the kernel args.
1086 */
1087 if (have_dtb(info)) {
1088 hwaddr align;
1089
1090 if (elf_machine == EM_AARCH64) {
1091 /*
1092 * Some AArch64 kernels on early bootup map the fdt region as
1093 *
1094 * [ ALIGN_DOWN(fdt, 2MB) ... ALIGN_DOWN(fdt, 2MB) + 2MB ]
1095 *
1096 * Let's play safe and prealign it to 2MB to give us some space.
1097 */
1098 align = 2 * MiB;
1099 } else {
1100 /*
1101 * Some 32bit kernels will trash anything in the 4K page the
1102 * initrd ends in, so make sure the DTB isn't caught up in that.
1103 */
1104 align = 4 * KiB;
1105 }
1106
1107 /* Place the DTB after the initrd in memory with alignment. */
1108 info->dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size,
1109 align);
1110 if (info->dtb_start >= ram_end) {
1111 error_report("Not enough space for DTB after kernel/initrd");
1112 exit(1);
1113 }
1114 fixupcontext[FIXUP_ARGPTR_LO] = info->dtb_start;
1115 fixupcontext[FIXUP_ARGPTR_HI] = info->dtb_start >> 32;
1116 } else {
1117 fixupcontext[FIXUP_ARGPTR_LO] =
1118 info->loader_start + KERNEL_ARGS_ADDR;
1119 fixupcontext[FIXUP_ARGPTR_HI] =
1120 (info->loader_start + KERNEL_ARGS_ADDR) >> 32;
1121 if (info->ram_size >= 4 * GiB) {
1122 error_report("RAM size must be less than 4GB to boot"
1123 " Linux kernel using ATAGS (try passing a device tree"
1124 " using -dtb)");
1125 exit(1);
1126 }
1127 }
1128 fixupcontext[FIXUP_ENTRYPOINT_LO] = entry;
1129 fixupcontext[FIXUP_ENTRYPOINT_HI] = entry >> 32;
1130
1131 arm_write_bootloader("bootloader", as, info->loader_start,
1132 primary_loader, fixupcontext);
1133
1134 if (info->write_board_setup) {
1135 info->write_board_setup(cpu, info);
1136 }
1137
1138 /*
1139 * Notify devices which need to fake up firmware initialization
1140 * that we're doing a direct kernel boot.
1141 */
1142 object_child_foreach_recursive(object_get_root(),
1143 do_arm_linux_init, info);
1144 }
1145 info->is_linux = is_linux;
1146
1147 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
1148 ARM_CPU(cs)->env.boot_info = info;
1149 }
1150 }
1151
arm_setup_firmware_boot(ARMCPU * cpu,struct arm_boot_info * info)1152 static void arm_setup_firmware_boot(ARMCPU *cpu, struct arm_boot_info *info)
1153 {
1154 /* Set up for booting firmware (which might load a kernel via fw_cfg) */
1155
1156 if (have_dtb(info)) {
1157 /*
1158 * If we have a device tree blob, but no kernel to supply it to (or
1159 * the kernel is supposed to be loaded by the bootloader), copy the
1160 * DTB to the base of RAM for the bootloader to pick up.
1161 */
1162 info->dtb_start = info->loader_start;
1163 }
1164
1165 if (info->kernel_filename) {
1166 FWCfgState *fw_cfg;
1167 bool try_decompressing_kernel;
1168
1169 fw_cfg = fw_cfg_find();
1170
1171 if (!fw_cfg) {
1172 error_report("This machine type does not support loading both "
1173 "a guest firmware/BIOS image and a guest kernel at "
1174 "the same time. You should change your QEMU command "
1175 "line to specify one or the other, but not both.");
1176 exit(1);
1177 }
1178
1179 try_decompressing_kernel = arm_feature(&cpu->env,
1180 ARM_FEATURE_AARCH64);
1181
1182 /*
1183 * Expose the kernel, the command line, and the initrd in fw_cfg.
1184 * We don't process them here at all, it's all left to the
1185 * firmware.
1186 */
1187 load_image_to_fw_cfg(fw_cfg,
1188 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA,
1189 info->kernel_filename,
1190 try_decompressing_kernel);
1191 load_image_to_fw_cfg(fw_cfg,
1192 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA,
1193 info->initrd_filename, false);
1194
1195 if (info->kernel_cmdline) {
1196 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1197 strlen(info->kernel_cmdline) + 1);
1198 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
1199 info->kernel_cmdline);
1200 }
1201 }
1202
1203 /*
1204 * We will start from address 0 (typically a boot ROM image) in the
1205 * same way as hardware. Leave env->boot_info NULL, so that
1206 * do_cpu_reset() knows it does not need to alter the PC on reset.
1207 */
1208 }
1209
arm_load_kernel(ARMCPU * cpu,MachineState * ms,struct arm_boot_info * info)1210 void arm_load_kernel(ARMCPU *cpu, MachineState *ms, struct arm_boot_info *info)
1211 {
1212 CPUState *cs;
1213 AddressSpace *as = arm_boot_address_space(cpu, info);
1214 int boot_el;
1215 CPUARMState *env = &cpu->env;
1216 int nb_cpus = 0;
1217
1218 /*
1219 * CPU objects (unlike devices) are not automatically reset on system
1220 * reset, so we must always register a handler to do so. If we're
1221 * actually loading a kernel, the handler is also responsible for
1222 * arranging that we start it correctly.
1223 */
1224 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
1225 qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
1226 nb_cpus++;
1227 }
1228
1229 /*
1230 * The board code is not supposed to set secure_board_setup unless
1231 * running its code in secure mode is actually possible, and KVM
1232 * doesn't support secure.
1233 */
1234 assert(!(info->secure_board_setup && kvm_enabled()));
1235 info->kernel_filename = ms->kernel_filename;
1236 info->kernel_cmdline = ms->kernel_cmdline;
1237 info->initrd_filename = ms->initrd_filename;
1238 info->dtb_filename = ms->dtb;
1239 info->dtb_limit = 0;
1240
1241 /* Load the kernel. */
1242 if (!info->kernel_filename || info->firmware_loaded) {
1243 arm_setup_firmware_boot(cpu, info);
1244 } else {
1245 arm_setup_direct_kernel_boot(cpu, info);
1246 }
1247
1248 /*
1249 * Disable the PSCI conduit if it is set up to target the same
1250 * or a lower EL than the one we're going to start the guest code in.
1251 * This logic needs to agree with the code in do_cpu_reset() which
1252 * decides whether we're going to boot the guest in the highest
1253 * supported exception level or in a lower one.
1254 */
1255
1256 /*
1257 * If PSCI is enabled, then SMC calls all go to the PSCI handler and
1258 * are never emulated to trap into guest code. It therefore does not
1259 * make sense for the board to have a setup code fragment that runs
1260 * in Secure, because this will probably need to itself issue an SMC of some
1261 * kind as part of its operation.
1262 */
1263 assert(info->psci_conduit == QEMU_PSCI_CONDUIT_DISABLED ||
1264 !info->secure_board_setup);
1265
1266 /* Boot into highest supported EL ... */
1267 if (arm_feature(env, ARM_FEATURE_EL3)) {
1268 boot_el = 3;
1269 } else if (arm_feature(env, ARM_FEATURE_EL2)) {
1270 boot_el = 2;
1271 } else {
1272 boot_el = 1;
1273 }
1274 /* ...except that if we're booting Linux we adjust the EL we boot into */
1275 if (info->is_linux && !info->secure_boot) {
1276 boot_el = arm_feature(env, ARM_FEATURE_EL2) ? 2 : 1;
1277 }
1278
1279 if ((info->psci_conduit == QEMU_PSCI_CONDUIT_HVC && boot_el >= 2) ||
1280 (info->psci_conduit == QEMU_PSCI_CONDUIT_SMC && boot_el == 3)) {
1281 info->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
1282 }
1283
1284 if (info->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
1285 for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
1286 Object *cpuobj = OBJECT(cs);
1287
1288 object_property_set_int(cpuobj, "psci-conduit", info->psci_conduit,
1289 &error_abort);
1290 /*
1291 * Secondary CPUs start in PSCI powered-down state. Like the
1292 * code in do_cpu_reset(), we assume first_cpu is the primary
1293 * CPU.
1294 */
1295 if (cs != first_cpu) {
1296 object_property_set_bool(cpuobj, "start-powered-off", true,
1297 &error_abort);
1298 }
1299 }
1300 }
1301
1302 if (info->psci_conduit == QEMU_PSCI_CONDUIT_DISABLED &&
1303 info->is_linux && nb_cpus > 1) {
1304 /*
1305 * We're booting Linux but not using PSCI, so for SMP we need
1306 * to write a custom secondary CPU boot loader stub, and arrange
1307 * for the secondary CPU reset to make the accompanying initialization.
1308 */
1309 if (!info->secondary_cpu_reset_hook) {
1310 info->secondary_cpu_reset_hook = default_reset_secondary;
1311 }
1312 if (!info->write_secondary_boot) {
1313 info->write_secondary_boot = default_write_secondary;
1314 }
1315 info->write_secondary_boot(cpu, info);
1316 } else {
1317 /*
1318 * No secondary boot stub; don't use the reset hook that would
1319 * have set the CPU up to call it
1320 */
1321 info->write_secondary_boot = NULL;
1322 info->secondary_cpu_reset_hook = NULL;
1323 }
1324
1325 /*
1326 * arm_load_dtb() may add a PSCI node so it must be called after we have
1327 * decided whether to enable PSCI and set the psci-conduit CPU properties.
1328 */
1329 if (!info->skip_dtb_autoload && have_dtb(info)) {
1330 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) {
1331 exit(1);
1332 }
1333 }
1334 }
1335
1336 static const TypeInfo arm_linux_boot_if_info = {
1337 .name = TYPE_ARM_LINUX_BOOT_IF,
1338 .parent = TYPE_INTERFACE,
1339 .class_size = sizeof(ARMLinuxBootIfClass),
1340 };
1341
arm_linux_boot_register_types(void)1342 static void arm_linux_boot_register_types(void)
1343 {
1344 type_register_static(&arm_linux_boot_if_info);
1345 }
1346
1347 type_init(arm_linux_boot_register_types)
1348