1 /*
2 * Arm MPS3 board emulation for Cortex-R-based FPGA images.
3 * (For M-profile images see mps2.c and mps2tz.c.)
4 *
5 * Copyright (c) 2017 Linaro Limited
6 * Written by Peter Maydell
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 or
10 * (at your option) any later version.
11 */
12
13 /*
14 * The MPS3 is an FPGA based dev board. This file handles FPGA images
15 * which use the Cortex-R CPUs. We model these separately from the
16 * M-profile images, because on M-profile the FPGA image is based on
17 * a "Subsystem for Embedded" which is similar to an SoC, whereas
18 * the R-profile FPGA images don't have that abstraction layer.
19 *
20 * We model the following FPGA images here:
21 * "mps3-an536" -- dual Cortex-R52 as documented in Arm Application Note AN536
22 *
23 * Application Note AN536:
24 * https://developer.arm.com/documentation/dai0536/latest/
25 */
26
27 #include "qemu/osdep.h"
28 #include "qemu/units.h"
29 #include "qapi/error.h"
30 #include "qapi/qmp/qlist.h"
31 #include "exec/address-spaces.h"
32 #include "cpu.h"
33 #include "sysemu/sysemu.h"
34 #include "hw/boards.h"
35 #include "hw/or-irq.h"
36 #include "hw/qdev-clock.h"
37 #include "hw/qdev-properties.h"
38 #include "hw/arm/boot.h"
39 #include "hw/arm/bsa.h"
40 #include "hw/char/cmsdk-apb-uart.h"
41 #include "hw/i2c/arm_sbcon_i2c.h"
42 #include "hw/intc/arm_gicv3.h"
43 #include "hw/misc/mps2-scc.h"
44 #include "hw/misc/mps2-fpgaio.h"
45 #include "hw/misc/unimp.h"
46 #include "hw/net/lan9118.h"
47 #include "hw/rtc/pl031.h"
48 #include "hw/ssi/pl022.h"
49 #include "hw/timer/cmsdk-apb-dualtimer.h"
50 #include "hw/watchdog/cmsdk-apb-watchdog.h"
51
52 /* Define the layout of RAM and ROM in a board */
53 typedef struct RAMInfo {
54 const char *name;
55 hwaddr base;
56 hwaddr size;
57 int mrindex; /* index into rams[]; -1 for the system RAM block */
58 int flags;
59 } RAMInfo;
60
61 /*
62 * The MPS3 DDR is 3GiB, but on a 32-bit host QEMU doesn't permit
63 * emulation of that much guest RAM, so artificially make it smaller.
64 */
65 #if HOST_LONG_BITS == 32
66 #define MPS3_DDR_SIZE (1 * GiB)
67 #else
68 #define MPS3_DDR_SIZE (3 * GiB)
69 #endif
70
71 /*
72 * Flag values:
73 * IS_MAIN: this is the main machine RAM
74 * IS_ROM: this area is read-only
75 */
76 #define IS_MAIN 1
77 #define IS_ROM 2
78
79 #define MPS3R_RAM_MAX 9
80 #define MPS3R_CPU_MAX 2
81 #define MPS3R_UART_MAX 4 /* shared UART count */
82
83 #define PERIPHBASE 0xf0000000
84 #define NUM_SPIS 96
85
86 typedef enum MPS3RFPGAType {
87 FPGA_AN536,
88 } MPS3RFPGAType;
89
90 struct MPS3RMachineClass {
91 MachineClass parent;
92 MPS3RFPGAType fpga_type;
93 const RAMInfo *raminfo;
94 hwaddr loader_start;
95 };
96
97 struct MPS3RMachineState {
98 MachineState parent;
99 struct arm_boot_info bootinfo;
100 MemoryRegion ram[MPS3R_RAM_MAX];
101 Object *cpu[MPS3R_CPU_MAX];
102 MemoryRegion cpu_sysmem[MPS3R_CPU_MAX];
103 MemoryRegion sysmem_alias[MPS3R_CPU_MAX];
104 MemoryRegion cpu_ram[MPS3R_CPU_MAX];
105 GICv3State gic;
106 /* per-CPU UARTs followed by the shared UARTs */
107 CMSDKAPBUART uart[MPS3R_CPU_MAX + MPS3R_UART_MAX];
108 OrIRQState cpu_uart_oflow[MPS3R_CPU_MAX];
109 OrIRQState uart_oflow;
110 CMSDKAPBWatchdog watchdog;
111 CMSDKAPBDualTimer dualtimer;
112 ArmSbconI2CState i2c[5];
113 PL022State spi[3];
114 MPS2SCC scc;
115 MPS2FPGAIO fpgaio;
116 UnimplementedDeviceState i2s_audio;
117 PL031State rtc;
118 Clock *clk;
119 };
120
121 #define TYPE_MPS3R_MACHINE "mps3r"
122 #define TYPE_MPS3R_AN536_MACHINE MACHINE_TYPE_NAME("mps3-an536")
123
124 OBJECT_DECLARE_TYPE(MPS3RMachineState, MPS3RMachineClass, MPS3R_MACHINE)
125
126 /*
127 * Main clock frequency CLK in Hz (50MHz). In the image there are also
128 * ACLK, MCLK, GPUCLK and PERIPHCLK at the same frequency; for our
129 * model we just roll them all into one.
130 */
131 #define CLK_FRQ 50000000
132
133 static const RAMInfo an536_raminfo[] = {
134 {
135 .name = "ATCM",
136 .base = 0x00000000,
137 .size = 0x00008000,
138 .mrindex = 0,
139 }, {
140 /* We model the QSPI flash as simple ROM for now */
141 .name = "QSPI",
142 .base = 0x08000000,
143 .size = 0x00800000,
144 .flags = IS_ROM,
145 .mrindex = 1,
146 }, {
147 .name = "BRAM",
148 .base = 0x10000000,
149 .size = 0x00080000,
150 .mrindex = 2,
151 }, {
152 .name = "DDR",
153 .base = 0x20000000,
154 .size = MPS3_DDR_SIZE,
155 .mrindex = -1,
156 }, {
157 .name = "ATCM0",
158 .base = 0xee000000,
159 .size = 0x00008000,
160 .mrindex = 3,
161 }, {
162 .name = "BTCM0",
163 .base = 0xee100000,
164 .size = 0x00008000,
165 .mrindex = 4,
166 }, {
167 .name = "CTCM0",
168 .base = 0xee200000,
169 .size = 0x00008000,
170 .mrindex = 5,
171 }, {
172 .name = "ATCM1",
173 .base = 0xee400000,
174 .size = 0x00008000,
175 .mrindex = 6,
176 }, {
177 .name = "BTCM1",
178 .base = 0xee500000,
179 .size = 0x00008000,
180 .mrindex = 7,
181 }, {
182 .name = "CTCM1",
183 .base = 0xee600000,
184 .size = 0x00008000,
185 .mrindex = 8,
186 }, {
187 .name = NULL,
188 }
189 };
190
191 static const int an536_oscclk[] = {
192 24000000, /* 24MHz reference for RTC and timers */
193 50000000, /* 50MHz ACLK */
194 50000000, /* 50MHz MCLK */
195 50000000, /* 50MHz GPUCLK */
196 24576000, /* 24.576MHz AUDCLK */
197 23750000, /* 23.75MHz HDLCDCLK */
198 100000000, /* 100MHz DDR4_REF_CLK */
199 };
200
mr_for_raminfo(MPS3RMachineState * mms,const RAMInfo * raminfo)201 static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms,
202 const RAMInfo *raminfo)
203 {
204 /* Return an initialized MemoryRegion for the RAMInfo. */
205 MemoryRegion *ram;
206
207 if (raminfo->mrindex < 0) {
208 /* Means this RAMInfo is for QEMU's "system memory" */
209 MachineState *machine = MACHINE(mms);
210 assert(!(raminfo->flags & IS_ROM));
211 return machine->ram;
212 }
213
214 assert(raminfo->mrindex < MPS3R_RAM_MAX);
215 ram = &mms->ram[raminfo->mrindex];
216
217 memory_region_init_ram(ram, NULL, raminfo->name,
218 raminfo->size, &error_fatal);
219 if (raminfo->flags & IS_ROM) {
220 memory_region_set_readonly(ram, true);
221 }
222 return ram;
223 }
224
225 /*
226 * There is no defined secondary boot protocol for Linux for the AN536,
227 * because real hardware has a restriction that atomic operations between
228 * the two CPUs do not function correctly, and so true SMP is not
229 * possible. Therefore for cases where the user is directly booting
230 * a kernel, we treat the system as essentially uniprocessor, and
231 * put the secondary CPU into power-off state (as if the user on the
232 * real hardware had configured the secondary to be halted via the
233 * SCC config registers).
234 *
235 * Note that the default secondary boot code would not work here anyway
236 * as it assumes a GICv2, and we have a GICv3.
237 */
mps3r_write_secondary_boot(ARMCPU * cpu,const struct arm_boot_info * info)238 static void mps3r_write_secondary_boot(ARMCPU *cpu,
239 const struct arm_boot_info *info)
240 {
241 /*
242 * Power the secondary CPU off. This means we don't need to write any
243 * boot code into guest memory. Note that the 'cpu' argument to this
244 * function is the primary CPU we passed to arm_load_kernel(), not
245 * the secondary. Loop around all the other CPUs, as the boot.c
246 * code does for the "disable secondaries if PSCI is enabled" case.
247 */
248 for (CPUState *cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
249 if (cs != first_cpu) {
250 object_property_set_bool(OBJECT(cs), "start-powered-off", true,
251 &error_abort);
252 }
253 }
254 }
255
mps3r_secondary_cpu_reset(ARMCPU * cpu,const struct arm_boot_info * info)256 static void mps3r_secondary_cpu_reset(ARMCPU *cpu,
257 const struct arm_boot_info *info)
258 {
259 /* We don't need to do anything here because the CPU will be off */
260 }
261
create_gic(MPS3RMachineState * mms,MemoryRegion * sysmem)262 static void create_gic(MPS3RMachineState *mms, MemoryRegion *sysmem)
263 {
264 MachineState *machine = MACHINE(mms);
265 DeviceState *gicdev;
266 QList *redist_region_count;
267
268 object_initialize_child(OBJECT(mms), "gic", &mms->gic, TYPE_ARM_GICV3);
269 gicdev = DEVICE(&mms->gic);
270 qdev_prop_set_uint32(gicdev, "num-cpu", machine->smp.cpus);
271 qdev_prop_set_uint32(gicdev, "num-irq", NUM_SPIS + GIC_INTERNAL);
272 redist_region_count = qlist_new();
273 qlist_append_int(redist_region_count, machine->smp.cpus);
274 qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count);
275 object_property_set_link(OBJECT(&mms->gic), "sysmem",
276 OBJECT(sysmem), &error_fatal);
277 sysbus_realize(SYS_BUS_DEVICE(&mms->gic), &error_fatal);
278 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 0, PERIPHBASE);
279 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 1, PERIPHBASE + 0x100000);
280 /*
281 * Wire the outputs from each CPU's generic timer and the GICv3
282 * maintenance interrupt signal to the appropriate GIC PPI inputs,
283 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
284 */
285 for (int i = 0; i < machine->smp.cpus; i++) {
286 DeviceState *cpudev = DEVICE(mms->cpu[i]);
287 SysBusDevice *gicsbd = SYS_BUS_DEVICE(&mms->gic);
288 int intidbase = NUM_SPIS + i * GIC_INTERNAL;
289 int irq;
290 /*
291 * Mapping from the output timer irq lines from the CPU to the
292 * GIC PPI inputs used for this board. This isn't a BSA board,
293 * but it uses the standard convention for the PPI numbers.
294 */
295 const int timer_irq[] = {
296 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
297 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
298 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
299 };
300
301 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
302 qdev_connect_gpio_out(cpudev, irq,
303 qdev_get_gpio_in(gicdev,
304 intidbase + timer_irq[irq]));
305 }
306
307 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
308 qdev_get_gpio_in(gicdev,
309 intidbase + ARCH_GIC_MAINT_IRQ));
310
311 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
312 qdev_get_gpio_in(gicdev,
313 intidbase + VIRTUAL_PMU_IRQ));
314
315 sysbus_connect_irq(gicsbd, i,
316 qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
317 sysbus_connect_irq(gicsbd, i + machine->smp.cpus,
318 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
319 sysbus_connect_irq(gicsbd, i + 2 * machine->smp.cpus,
320 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
321 sysbus_connect_irq(gicsbd, i + 3 * machine->smp.cpus,
322 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
323 }
324 }
325
326 /*
327 * Create UART uartno, and map it into the MemoryRegion mem at address baseaddr.
328 * The qemu_irq arguments are where we connect the various IRQs from the UART.
329 */
create_uart(MPS3RMachineState * mms,int uartno,MemoryRegion * mem,hwaddr baseaddr,qemu_irq txirq,qemu_irq rxirq,qemu_irq txoverirq,qemu_irq rxoverirq,qemu_irq combirq)330 static void create_uart(MPS3RMachineState *mms, int uartno, MemoryRegion *mem,
331 hwaddr baseaddr, qemu_irq txirq, qemu_irq rxirq,
332 qemu_irq txoverirq, qemu_irq rxoverirq,
333 qemu_irq combirq)
334 {
335 g_autofree char *s = g_strdup_printf("uart%d", uartno);
336 SysBusDevice *sbd;
337
338 assert(uartno < ARRAY_SIZE(mms->uart));
339 object_initialize_child(OBJECT(mms), s, &mms->uart[uartno],
340 TYPE_CMSDK_APB_UART);
341 qdev_prop_set_uint32(DEVICE(&mms->uart[uartno]), "pclk-frq", CLK_FRQ);
342 qdev_prop_set_chr(DEVICE(&mms->uart[uartno]), "chardev", serial_hd(uartno));
343 sbd = SYS_BUS_DEVICE(&mms->uart[uartno]);
344 sysbus_realize(sbd, &error_fatal);
345 memory_region_add_subregion(mem, baseaddr,
346 sysbus_mmio_get_region(sbd, 0));
347 sysbus_connect_irq(sbd, 0, txirq);
348 sysbus_connect_irq(sbd, 1, rxirq);
349 sysbus_connect_irq(sbd, 2, txoverirq);
350 sysbus_connect_irq(sbd, 3, rxoverirq);
351 sysbus_connect_irq(sbd, 4, combirq);
352 }
353
mps3r_common_init(MachineState * machine)354 static void mps3r_common_init(MachineState *machine)
355 {
356 MPS3RMachineState *mms = MPS3R_MACHINE(machine);
357 MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms);
358 MemoryRegion *sysmem = get_system_memory();
359 DeviceState *gicdev;
360 QList *oscclk;
361
362 mms->clk = clock_new(OBJECT(machine), "CLK");
363 clock_set_hz(mms->clk, CLK_FRQ);
364
365 for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) {
366 MemoryRegion *mr = mr_for_raminfo(mms, ri);
367 memory_region_add_subregion(sysmem, ri->base, mr);
368 }
369
370 assert(machine->smp.cpus <= MPS3R_CPU_MAX);
371 for (int i = 0; i < machine->smp.cpus; i++) {
372 g_autofree char *sysmem_name = g_strdup_printf("cpu-%d-memory", i);
373 g_autofree char *ramname = g_strdup_printf("cpu-%d-memory", i);
374 g_autofree char *alias_name = g_strdup_printf("sysmem-alias-%d", i);
375
376 /*
377 * Each CPU has some private RAM/peripherals, so create the container
378 * which will house those, with the whole-machine system memory being
379 * used where there's no CPU-specific device. Note that we need the
380 * sysmem_alias aliases because we can't put one MR (the original
381 * 'sysmem') into more than one other MR.
382 */
383 memory_region_init(&mms->cpu_sysmem[i], OBJECT(machine),
384 sysmem_name, UINT64_MAX);
385 memory_region_init_alias(&mms->sysmem_alias[i], OBJECT(machine),
386 alias_name, sysmem, 0, UINT64_MAX);
387 memory_region_add_subregion_overlap(&mms->cpu_sysmem[i], 0,
388 &mms->sysmem_alias[i], -1);
389
390 mms->cpu[i] = object_new(machine->cpu_type);
391 object_property_set_link(mms->cpu[i], "memory",
392 OBJECT(&mms->cpu_sysmem[i]), &error_abort);
393 object_property_set_int(mms->cpu[i], "reset-cbar",
394 PERIPHBASE, &error_abort);
395 qdev_realize(DEVICE(mms->cpu[i]), NULL, &error_fatal);
396 object_unref(mms->cpu[i]);
397
398 /* Per-CPU RAM */
399 memory_region_init_ram(&mms->cpu_ram[i], NULL, ramname,
400 0x1000, &error_fatal);
401 memory_region_add_subregion(&mms->cpu_sysmem[i], 0xe7c01000,
402 &mms->cpu_ram[i]);
403 }
404
405 create_gic(mms, sysmem);
406 gicdev = DEVICE(&mms->gic);
407
408 /*
409 * UARTs 0 and 1 are per-CPU; their interrupts are wired to
410 * the relevant CPU's PPI 0..3, aka INTID 16..19
411 */
412 for (int i = 0; i < machine->smp.cpus; i++) {
413 int intidbase = NUM_SPIS + i * GIC_INTERNAL;
414 g_autofree char *s = g_strdup_printf("cpu-uart-oflow-orgate%d", i);
415 DeviceState *orgate;
416
417 /* The two overflow IRQs from the UART are ORed together into PPI 3 */
418 object_initialize_child(OBJECT(mms), s, &mms->cpu_uart_oflow[i],
419 TYPE_OR_IRQ);
420 orgate = DEVICE(&mms->cpu_uart_oflow[i]);
421 qdev_prop_set_uint32(orgate, "num-lines", 2);
422 qdev_realize(orgate, NULL, &error_fatal);
423 qdev_connect_gpio_out(orgate, 0,
424 qdev_get_gpio_in(gicdev, intidbase + 19));
425
426 create_uart(mms, i, &mms->cpu_sysmem[i], 0xe7c00000,
427 qdev_get_gpio_in(gicdev, intidbase + 17), /* tx */
428 qdev_get_gpio_in(gicdev, intidbase + 16), /* rx */
429 qdev_get_gpio_in(orgate, 0), /* txover */
430 qdev_get_gpio_in(orgate, 1), /* rxover */
431 qdev_get_gpio_in(gicdev, intidbase + 18) /* combined */);
432 }
433 /*
434 * UARTs 2 to 5 are whole-system; all overflow IRQs are ORed
435 * together into IRQ 17
436 */
437 object_initialize_child(OBJECT(mms), "uart-oflow-orgate",
438 &mms->uart_oflow, TYPE_OR_IRQ);
439 qdev_prop_set_uint32(DEVICE(&mms->uart_oflow), "num-lines",
440 MPS3R_UART_MAX * 2);
441 qdev_realize(DEVICE(&mms->uart_oflow), NULL, &error_fatal);
442 qdev_connect_gpio_out(DEVICE(&mms->uart_oflow), 0,
443 qdev_get_gpio_in(gicdev, 17));
444
445 for (int i = 0; i < MPS3R_UART_MAX; i++) {
446 hwaddr baseaddr = 0xe0205000 + i * 0x1000;
447 int rxirq = 5 + i * 2, txirq = 6 + i * 2, combirq = 13 + i;
448
449 create_uart(mms, i + MPS3R_CPU_MAX, sysmem, baseaddr,
450 qdev_get_gpio_in(gicdev, txirq),
451 qdev_get_gpio_in(gicdev, rxirq),
452 qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2),
453 qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2 + 1),
454 qdev_get_gpio_in(gicdev, combirq));
455 }
456
457 for (int i = 0; i < 4; i++) {
458 /* CMSDK GPIO controllers */
459 g_autofree char *s = g_strdup_printf("gpio%d", i);
460 create_unimplemented_device(s, 0xe0000000 + i * 0x1000, 0x1000);
461 }
462
463 object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog,
464 TYPE_CMSDK_APB_WATCHDOG);
465 qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->clk);
466 sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal);
467 sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0,
468 qdev_get_gpio_in(gicdev, 0));
469 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0xe0100000);
470
471 object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer,
472 TYPE_CMSDK_APB_DUALTIMER);
473 qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->clk);
474 sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal);
475 sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0,
476 qdev_get_gpio_in(gicdev, 3));
477 sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 1,
478 qdev_get_gpio_in(gicdev, 1));
479 sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 2,
480 qdev_get_gpio_in(gicdev, 2));
481 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0xe0101000);
482
483 for (int i = 0; i < ARRAY_SIZE(mms->i2c); i++) {
484 static const hwaddr i2cbase[] = {0xe0102000, /* Touch */
485 0xe0103000, /* Audio */
486 0xe0107000, /* Shield0 */
487 0xe0108000, /* Shield1 */
488 0xe0109000}; /* DDR4 EEPROM */
489 g_autofree char *s = g_strdup_printf("i2c%d", i);
490
491 object_initialize_child(OBJECT(mms), s, &mms->i2c[i],
492 TYPE_ARM_SBCON_I2C);
493 sysbus_realize(SYS_BUS_DEVICE(&mms->i2c[i]), &error_fatal);
494 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->i2c[i]), 0, i2cbase[i]);
495 if (i != 2 && i != 3) {
496 /*
497 * internal-only bus: mark it full to avoid user-created
498 * i2c devices being plugged into it.
499 */
500 qbus_mark_full(qdev_get_child_bus(DEVICE(&mms->i2c[i]), "i2c"));
501 }
502 }
503
504 for (int i = 0; i < ARRAY_SIZE(mms->spi); i++) {
505 g_autofree char *s = g_strdup_printf("spi%d", i);
506 hwaddr baseaddr = 0xe0104000 + i * 0x1000;
507
508 object_initialize_child(OBJECT(mms), s, &mms->spi[i], TYPE_PL022);
509 sysbus_realize(SYS_BUS_DEVICE(&mms->spi[i]), &error_fatal);
510 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->spi[i]), 0, baseaddr);
511 sysbus_connect_irq(SYS_BUS_DEVICE(&mms->spi[i]), 0,
512 qdev_get_gpio_in(gicdev, 22 + i));
513 }
514
515 object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC);
516 qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg0", 0);
517 qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg4", 0x2);
518 qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-aid", 0x00200008);
519 qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-id", 0x41055360);
520 oscclk = qlist_new();
521 for (int i = 0; i < ARRAY_SIZE(an536_oscclk); i++) {
522 qlist_append_int(oscclk, an536_oscclk[i]);
523 }
524 qdev_prop_set_array(DEVICE(&mms->scc), "oscclk", oscclk);
525 sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal);
526 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->scc), 0, 0xe0200000);
527
528 create_unimplemented_device("i2s-audio", 0xe0201000, 0x1000);
529
530 object_initialize_child(OBJECT(mms), "fpgaio", &mms->fpgaio,
531 TYPE_MPS2_FPGAIO);
532 qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", an536_oscclk[1]);
533 qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "num-leds", 10);
534 qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-switches", true);
535 qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-dbgctrl", false);
536 sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal);
537 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0xe0202000);
538
539 create_unimplemented_device("clcd", 0xe0209000, 0x1000);
540
541 object_initialize_child(OBJECT(mms), "rtc", &mms->rtc, TYPE_PL031);
542 sysbus_realize(SYS_BUS_DEVICE(&mms->rtc), &error_fatal);
543 sysbus_mmio_map(SYS_BUS_DEVICE(&mms->rtc), 0, 0xe020a000);
544 sysbus_connect_irq(SYS_BUS_DEVICE(&mms->rtc), 0,
545 qdev_get_gpio_in(gicdev, 4));
546
547 /*
548 * In hardware this is a LAN9220; the LAN9118 is software compatible
549 * except that it doesn't support the checksum-offload feature.
550 */
551 lan9118_init(0xe0300000,
552 qdev_get_gpio_in(gicdev, 18));
553
554 create_unimplemented_device("usb", 0xe0301000, 0x1000);
555 create_unimplemented_device("qspi-write-config", 0xe0600000, 0x1000);
556
557 mms->bootinfo.ram_size = machine->ram_size;
558 mms->bootinfo.board_id = -1;
559 mms->bootinfo.loader_start = mmc->loader_start;
560 mms->bootinfo.write_secondary_boot = mps3r_write_secondary_boot;
561 mms->bootinfo.secondary_cpu_reset_hook = mps3r_secondary_cpu_reset;
562 arm_load_kernel(ARM_CPU(mms->cpu[0]), machine, &mms->bootinfo);
563 }
564
mps3r_set_default_ram_info(MPS3RMachineClass * mmc)565 static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc)
566 {
567 /*
568 * Set mc->default_ram_size and default_ram_id from the
569 * information in mmc->raminfo.
570 */
571 MachineClass *mc = MACHINE_CLASS(mmc);
572 const RAMInfo *p;
573
574 for (p = mmc->raminfo; p->name; p++) {
575 if (p->mrindex < 0) {
576 /* Found the entry for "system memory" */
577 mc->default_ram_size = p->size;
578 mc->default_ram_id = p->name;
579 mmc->loader_start = p->base;
580 return;
581 }
582 }
583 g_assert_not_reached();
584 }
585
mps3r_class_init(ObjectClass * oc,void * data)586 static void mps3r_class_init(ObjectClass *oc, void *data)
587 {
588 MachineClass *mc = MACHINE_CLASS(oc);
589
590 mc->init = mps3r_common_init;
591 }
592
mps3r_an536_class_init(ObjectClass * oc,void * data)593 static void mps3r_an536_class_init(ObjectClass *oc, void *data)
594 {
595 MachineClass *mc = MACHINE_CLASS(oc);
596 MPS3RMachineClass *mmc = MPS3R_MACHINE_CLASS(oc);
597 static const char * const valid_cpu_types[] = {
598 ARM_CPU_TYPE_NAME("cortex-r52"),
599 NULL
600 };
601
602 mc->desc = "ARM MPS3 with AN536 FPGA image for Cortex-R52";
603 /*
604 * In the real FPGA image there are always two cores, but the standard
605 * initial setting for the SCC SYSCON 0x000 register is 0x21, meaning
606 * that the second core is held in reset and halted. Many images built for
607 * the board do not expect the second core to run at startup (especially
608 * since on the real FPGA image it is not possible to use LDREX/STREX
609 * in RAM between the two cores, so a true SMP setup isn't supported).
610 *
611 * As QEMU's equivalent of this, we support both -smp 1 and -smp 2,
612 * with the default being -smp 1. This seems a more intuitive UI for
613 * QEMU users than, for instance, having a machine property to allow
614 * the user to set the initial value of the SYSCON 0x000 register.
615 */
616 mc->default_cpus = 1;
617 mc->min_cpus = 1;
618 mc->max_cpus = 2;
619 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-r52");
620 mc->valid_cpu_types = valid_cpu_types;
621 mmc->raminfo = an536_raminfo;
622 mps3r_set_default_ram_info(mmc);
623 }
624
625 static const TypeInfo mps3r_machine_types[] = {
626 {
627 .name = TYPE_MPS3R_MACHINE,
628 .parent = TYPE_MACHINE,
629 .abstract = true,
630 .instance_size = sizeof(MPS3RMachineState),
631 .class_size = sizeof(MPS3RMachineClass),
632 .class_init = mps3r_class_init,
633 }, {
634 .name = TYPE_MPS3R_AN536_MACHINE,
635 .parent = TYPE_MPS3R_MACHINE,
636 .class_init = mps3r_an536_class_init,
637 },
638 };
639
640 DEFINE_TYPES(mps3r_machine_types);
641