1 /*
2 * QEMU RX CPU
3 *
4 * Copyright (c) 2019 Yoshinori Sato
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #include "qemu/osdep.h"
20 #include "qemu/qemu-print.h"
21 #include "qapi/error.h"
22 #include "cpu.h"
23 #include "migration/vmstate.h"
24 #include "exec/exec-all.h"
25 #include "exec/page-protection.h"
26 #include "hw/loader.h"
27 #include "fpu/softfloat.h"
28 #include "tcg/debug-assert.h"
29
rx_cpu_set_pc(CPUState * cs,vaddr value)30 static void rx_cpu_set_pc(CPUState *cs, vaddr value)
31 {
32 RXCPU *cpu = RX_CPU(cs);
33
34 cpu->env.pc = value;
35 }
36
rx_cpu_get_pc(CPUState * cs)37 static vaddr rx_cpu_get_pc(CPUState *cs)
38 {
39 RXCPU *cpu = RX_CPU(cs);
40
41 return cpu->env.pc;
42 }
43
rx_cpu_synchronize_from_tb(CPUState * cs,const TranslationBlock * tb)44 static void rx_cpu_synchronize_from_tb(CPUState *cs,
45 const TranslationBlock *tb)
46 {
47 RXCPU *cpu = RX_CPU(cs);
48
49 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
50 cpu->env.pc = tb->pc;
51 }
52
rx_restore_state_to_opc(CPUState * cs,const TranslationBlock * tb,const uint64_t * data)53 static void rx_restore_state_to_opc(CPUState *cs,
54 const TranslationBlock *tb,
55 const uint64_t *data)
56 {
57 RXCPU *cpu = RX_CPU(cs);
58
59 cpu->env.pc = data[0];
60 }
61
rx_cpu_has_work(CPUState * cs)62 static bool rx_cpu_has_work(CPUState *cs)
63 {
64 return cs->interrupt_request &
65 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR);
66 }
67
riscv_cpu_mmu_index(CPUState * cs,bool ifunc)68 static int riscv_cpu_mmu_index(CPUState *cs, bool ifunc)
69 {
70 return 0;
71 }
72
rx_cpu_reset_hold(Object * obj,ResetType type)73 static void rx_cpu_reset_hold(Object *obj, ResetType type)
74 {
75 CPUState *cs = CPU(obj);
76 RXCPUClass *rcc = RX_CPU_GET_CLASS(obj);
77 CPURXState *env = cpu_env(cs);
78 uint32_t *resetvec;
79
80 if (rcc->parent_phases.hold) {
81 rcc->parent_phases.hold(obj, type);
82 }
83
84 memset(env, 0, offsetof(CPURXState, end_reset_fields));
85
86 resetvec = rom_ptr(0xfffffffc, 4);
87 if (resetvec) {
88 /* In the case of kernel, it is ignored because it is not set. */
89 env->pc = ldl_p(resetvec);
90 }
91 rx_cpu_unpack_psw(env, 0, 1);
92 env->regs[0] = env->isp = env->usp = 0;
93 env->fpsw = 0;
94 set_flush_to_zero(1, &env->fp_status);
95 set_flush_inputs_to_zero(1, &env->fp_status);
96 /*
97 * TODO: this is not the correct NaN propagation rule for this
98 * architecture. The "RX Family User's Manual: Software" table 1.6
99 * defines the propagation rules as "prefer SNaN over QNaN;
100 * then prefer dest over source", which is float_2nan_prop_s_ab.
101 */
102 set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
103 }
104
rx_cpu_class_by_name(const char * cpu_model)105 static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)
106 {
107 ObjectClass *oc;
108 char *typename;
109
110 oc = object_class_by_name(cpu_model);
111 if (oc != NULL && object_class_dynamic_cast(oc, TYPE_RX_CPU) != NULL) {
112 return oc;
113 }
114 typename = g_strdup_printf(RX_CPU_TYPE_NAME("%s"), cpu_model);
115 oc = object_class_by_name(typename);
116 g_free(typename);
117
118 return oc;
119 }
120
rx_cpu_realize(DeviceState * dev,Error ** errp)121 static void rx_cpu_realize(DeviceState *dev, Error **errp)
122 {
123 CPUState *cs = CPU(dev);
124 RXCPUClass *rcc = RX_CPU_GET_CLASS(dev);
125 Error *local_err = NULL;
126
127 cpu_exec_realizefn(cs, &local_err);
128 if (local_err != NULL) {
129 error_propagate(errp, local_err);
130 return;
131 }
132
133 qemu_init_vcpu(cs);
134 cpu_reset(cs);
135
136 rcc->parent_realize(dev, errp);
137 }
138
rx_cpu_set_irq(void * opaque,int no,int request)139 static void rx_cpu_set_irq(void *opaque, int no, int request)
140 {
141 RXCPU *cpu = opaque;
142 CPUState *cs = CPU(cpu);
143 int irq = request & 0xff;
144
145 static const int mask[] = {
146 [RX_CPU_IRQ] = CPU_INTERRUPT_HARD,
147 [RX_CPU_FIR] = CPU_INTERRUPT_FIR,
148 };
149 if (irq) {
150 cpu->env.req_irq = irq;
151 cpu->env.req_ipl = (request >> 8) & 0x0f;
152 cpu_interrupt(cs, mask[no]);
153 } else {
154 cpu_reset_interrupt(cs, mask[no]);
155 }
156 }
157
rx_cpu_disas_set_info(CPUState * cpu,disassemble_info * info)158 static void rx_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
159 {
160 info->mach = bfd_mach_rx;
161 info->print_insn = print_insn_rx;
162 }
163
rx_cpu_tlb_fill(CPUState * cs,vaddr addr,int size,MMUAccessType access_type,int mmu_idx,bool probe,uintptr_t retaddr)164 static bool rx_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
165 MMUAccessType access_type, int mmu_idx,
166 bool probe, uintptr_t retaddr)
167 {
168 uint32_t address, physical, prot;
169
170 /* Linear mapping */
171 address = physical = addr & TARGET_PAGE_MASK;
172 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
173 tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
174 return true;
175 }
176
rx_cpu_init(Object * obj)177 static void rx_cpu_init(Object *obj)
178 {
179 RXCPU *cpu = RX_CPU(obj);
180
181 qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2);
182 }
183
184 #ifndef CONFIG_USER_ONLY
185 #include "hw/core/sysemu-cpu-ops.h"
186
187 static const struct SysemuCPUOps rx_sysemu_ops = {
188 .get_phys_page_debug = rx_cpu_get_phys_page_debug,
189 };
190 #endif
191
192 #include "hw/core/tcg-cpu-ops.h"
193
194 static const TCGCPUOps rx_tcg_ops = {
195 .initialize = rx_translate_init,
196 .synchronize_from_tb = rx_cpu_synchronize_from_tb,
197 .restore_state_to_opc = rx_restore_state_to_opc,
198 .tlb_fill = rx_cpu_tlb_fill,
199
200 #ifndef CONFIG_USER_ONLY
201 .cpu_exec_interrupt = rx_cpu_exec_interrupt,
202 .cpu_exec_halt = rx_cpu_has_work,
203 .do_interrupt = rx_cpu_do_interrupt,
204 #endif /* !CONFIG_USER_ONLY */
205 };
206
rx_cpu_class_init(ObjectClass * klass,void * data)207 static void rx_cpu_class_init(ObjectClass *klass, void *data)
208 {
209 DeviceClass *dc = DEVICE_CLASS(klass);
210 CPUClass *cc = CPU_CLASS(klass);
211 RXCPUClass *rcc = RX_CPU_CLASS(klass);
212 ResettableClass *rc = RESETTABLE_CLASS(klass);
213
214 device_class_set_parent_realize(dc, rx_cpu_realize,
215 &rcc->parent_realize);
216 resettable_class_set_parent_phases(rc, NULL, rx_cpu_reset_hold, NULL,
217 &rcc->parent_phases);
218
219 cc->class_by_name = rx_cpu_class_by_name;
220 cc->has_work = rx_cpu_has_work;
221 cc->mmu_index = riscv_cpu_mmu_index;
222 cc->dump_state = rx_cpu_dump_state;
223 cc->set_pc = rx_cpu_set_pc;
224 cc->get_pc = rx_cpu_get_pc;
225
226 #ifndef CONFIG_USER_ONLY
227 cc->sysemu_ops = &rx_sysemu_ops;
228 #endif
229 cc->gdb_read_register = rx_cpu_gdb_read_register;
230 cc->gdb_write_register = rx_cpu_gdb_write_register;
231 cc->disas_set_info = rx_cpu_disas_set_info;
232
233 cc->gdb_core_xml_file = "rx-core.xml";
234 cc->tcg_ops = &rx_tcg_ops;
235 }
236
237 static const TypeInfo rx_cpu_info = {
238 .name = TYPE_RX_CPU,
239 .parent = TYPE_CPU,
240 .instance_size = sizeof(RXCPU),
241 .instance_align = __alignof(RXCPU),
242 .instance_init = rx_cpu_init,
243 .abstract = true,
244 .class_size = sizeof(RXCPUClass),
245 .class_init = rx_cpu_class_init,
246 };
247
248 static const TypeInfo rx62n_rx_cpu_info = {
249 .name = TYPE_RX62N_CPU,
250 .parent = TYPE_RX_CPU,
251 };
252
rx_cpu_register_types(void)253 static void rx_cpu_register_types(void)
254 {
255 type_register_static(&rx_cpu_info);
256 type_register_static(&rx62n_rx_cpu_info);
257 }
258
259 type_init(rx_cpu_register_types)
260