1 /*
2 Sega/Yamaha AICA emulation
3 By ElSemi, kingshriek, and R. Belmont
4
5 This is effectively a 64-voice SCSP, with the following differences:
6 - No FM mode
7 - A third sample format (ADPCM) has been added
8 - Some minor other tweeks
9 */
10
11 #include <math.h>
12 #include <string.h>
13 #include "ao.h"
14 #include "cpuintrf.h"
15 #include "aica.h"
16 #include "aicadsp.h"
17 #include "dc_hw.h"
18
19 #define ICLIP16(x) (x<-32768)?-32768:((x>32767)?32767:x)
20
21 #define SHIFT 12
22 #define FIX(v) ((UINT32) ((float) (1<<SHIFT)*(v)))
23
24
25 #define EG_SHIFT 16
26
27 #define USEDSP
28
29 // include the LFO handling code
30 #include "aicalfo.c"
31
32 /*
33 AICA features 64 programmable slots
34 that can generate PCM and ADPCM (from ROM/RAM) sound
35 */
36
37 //SLOT PARAMETERS
38 #define KEYONEX(slot) ((slot->udata.data[0x0]>>0x0)&0x8000)
39 #define KEYONB(slot) ((slot->udata.data[0x0]>>0x0)&0x4000)
40 #define SSCTL(slot) ((slot->udata.data[0x0]>>0xA)&0x0001)
41 #define LPCTL(slot) ((slot->udata.data[0x0]>>0x9)&0x0001)
42 #define PCMS(slot) ((slot->udata.data[0x0]>>0x7)&0x0003)
43
44 #define SA(slot) (((slot->udata.data[0x0]&0x7F)<<16)|(slot->udata.data[0x4/2]))
45
46 #define LSA(slot) (slot->udata.data[0x8/2])
47
48 #define LEA(slot) (slot->udata.data[0xc/2])
49
50 #define D2R(slot) ((slot->udata.data[0x10/2]>>0xB)&0x001F)
51 #define D1R(slot) ((slot->udata.data[0x10/2]>>0x6)&0x001F)
52 #define AR(slot) ((slot->udata.data[0x10/2]>>0x0)&0x001F)
53
54 #define LPSLNK(slot) ((slot->udata.data[0x14/2]>>0x0)&0x4000)
55 #define KRS(slot) ((slot->udata.data[0x14/2]>>0xA)&0x000F)
56 #define DL(slot) ((slot->udata.data[0x14/2]>>0x5)&0x001F)
57 #define RR(slot) ((slot->udata.data[0x14/2]>>0x0)&0x001F)
58
59 #define TL(slot) ((slot->udata.data[0x28/2]>>0x8)&0x00FF)
60
61 #define OCT(slot) ((slot->udata.data[0x18/2]>>0xB)&0x000F)
62 #define FNS(slot) ((slot->udata.data[0x18/2]>>0x0)&0x03FF)
63
64 #define LFORE(slot) ((slot->udata.data[0x1c/2]>>0x0)&0x8000)
65 #define LFOF(slot) ((slot->udata.data[0x1c/2]>>0xA)&0x001F)
66 #define PLFOWS(slot) ((slot->udata.data[0x1c/2]>>0x8)&0x0003)
67 #define PLFOS(slot) ((slot->udata.data[0x1c/2]>>0x5)&0x0007)
68 #define ALFOWS(slot) ((slot->udata.data[0x1c/2]>>0x3)&0x0003)
69 #define ALFOS(slot) ((slot->udata.data[0x1c/2]>>0x0)&0x0007)
70
71 #define ISEL(slot) ((slot->udata.data[0x20/2]>>0x0)&0x000F)
72 #define IMXL(slot) ((slot->udata.data[0x20/2]>>0x4)&0x000F)
73
74 #define DISDL(slot) ((slot->udata.data[0x24/2]>>0x8)&0x000F)
75 #define DIPAN(slot) ((slot->udata.data[0x24/2]>>0x0)&0x001F)
76
77 #define EFSDL(slot) ((AICA->EFSPAN[slot*4]>>8)&0x000f)
78 #define EFPAN(slot) ((AICA->EFSPAN[slot*4]>>0)&0x001f)
79
80 //Envelope times in ms
81 static const double ARTimes[64]={100000/*infinity*/,100000/*infinity*/,8100.0,6900.0,6000.0,4800.0,4000.0,3400.0,3000.0,2400.0,2000.0,1700.0,1500.0,
82 1200.0,1000.0,860.0,760.0,600.0,500.0,430.0,380.0,300.0,250.0,220.0,190.0,150.0,130.0,110.0,95.0,
83 76.0,63.0,55.0,47.0,38.0,31.0,27.0,24.0,19.0,15.0,13.0,12.0,9.4,7.9,6.8,6.0,4.7,3.8,3.4,3.0,2.4,
84 2.0,1.8,1.6,1.3,1.1,0.93,0.85,0.65,0.53,0.44,0.40,0.35,0.0,0.0};
85 static const double DRTimes[64]={100000/*infinity*/,100000/*infinity*/,118200.0,101300.0,88600.0,70900.0,59100.0,50700.0,44300.0,35500.0,29600.0,25300.0,22200.0,17700.0,
86 14800.0,12700.0,11100.0,8900.0,7400.0,6300.0,5500.0,4400.0,3700.0,3200.0,2800.0,2200.0,1800.0,1600.0,1400.0,1100.0,
87 920.0,790.0,690.0,550.0,460.0,390.0,340.0,270.0,230.0,200.0,170.0,140.0,110.0,98.0,85.0,68.0,57.0,49.0,43.0,34.0,
88 28.0,25.0,22.0,18.0,14.0,12.0,11.0,8.5,7.1,6.1,5.4,4.3,3.6,3.1};
89 static UINT32 FNS_Table[0x400];
90 static INT32 EG_TABLE[0x400];
91
92 typedef enum {ATTACK,DECAY1,DECAY2,RELEASE} _STATE;
93 struct _EG
94 {
95 int volume; //
96 _STATE state;
97 int step;
98 //step vals
99 int AR; //Attack
100 int D1R; //Decay1
101 int D2R; //Decay2
102 int RR; //Release
103
104 int DL; //Decay level
105 UINT8 LPLINK;
106 };
107
108 struct _SLOT
109 {
110 union
111 {
112 UINT16 data[0x40]; //only 0x1a bytes used
113 UINT8 datab[0x80];
114 } udata;
115 UINT8 active; //this slot is currently playing
116 UINT8 *base; //samples base address
117 UINT32 prv_addr; // previous play address (for ADPCM)
118 UINT32 cur_addr; //current play address (24.8)
119 UINT32 nxt_addr; //next play address
120 UINT32 step; //pitch step (24.8)
121 UINT8 Backwards; //the wave is playing backwards
122 struct _EG EG; //Envelope
123 struct _EG FEG; //filter envelope
124 struct _LFO PLFO; //Phase LFO
125 struct _LFO ALFO; //Amplitude LFO
126 int slot;
127 int cur_sample; //current ADPCM sample
128 int cur_quant; //current ADPCM step
129 int curstep;
130 int cur_lpquant, cur_lpsample, cur_lpstep;
131 UINT8 *adbase, *adlpbase;
132 UINT8 mslc; // monitored?
133 };
134
135
136 #define MEM4B(aica) ((aica->udata.data[0]>>0x0)&0x0200)
137 #define DAC18B(aica) ((aica->udata.data[0]>>0x0)&0x0100)
138 #define MVOL(aica) ((aica->udata.data[0]>>0x0)&0x000F)
139 #define RBL(aica) ((aica->udata.data[2]>>0xD)&0x0003)
140 #define RBP(aica) ((aica->udata.data[2]>>0x0)&0x0fff)
141 #define MOFULL(aica) ((aica->udata.data[4]>>0x0)&0x1000)
142 #define MOEMPTY(aica) ((aica->udata.data[4]>>0x0)&0x0800)
143 #define MIOVF(aica) ((aica->udata.data[4]>>0x0)&0x0400)
144 #define MIFULL(aica) ((aica->udata.data[4]>>0x0)&0x0200)
145 #define MIEMPTY(aica) ((aica->udata.data[4]>>0x0)&0x0100)
146
147 #define AFSEL(aica) ((aica->udata.data[6]>>0x0)&0x4000)
148 #define MSLC(aica) ((aica->udata.data[6]>>0x8)&0x3F)
149
150 #define SCILV0(aica) ((aica->udata.data[0xa8/2]>>0x0)&0xff)
151 #define SCILV1(aica) ((aica->udata.data[0xac/2]>>0x0)&0xff)
152 #define SCILV2(aica) ((aica->udata.data[0xb0/2]>>0x0)&0xff)
153
154 #define SCIEX0 0
155 #define SCIEX1 1
156 #define SCIEX2 2
157 #define SCIMID 3
158 #define SCIDMA 4
159 #define SCIIRQ 5
160 #define SCITMA 6
161 #define SCITMB 7
162
163 struct _AICA
164 {
165 union
166 {
167 UINT16 data[0xc0/2];
168 UINT8 datab[0xc0];
169 } udata;
170 UINT16 IRQL, IRQR;
171 UINT16 EFSPAN[0x48];
172 struct _SLOT Slots[64];
173 signed short RINGBUF[64];
174 unsigned char BUFPTR;
175 unsigned char *AICARAM;
176 UINT32 AICARAM_LENGTH;
177 char Master;
178 void (*IntARMCB)(struct sARM7 *cpu, int irq);
179
180 INT32 *buffertmpl, *buffertmpr;
181
182 UINT32 IrqTimA;
183 UINT32 IrqTimBC;
184 UINT32 IrqMidi;
185
186 UINT8 MidiOutW,MidiOutR;
187 UINT8 MidiStack[16];
188 UINT8 MidiW,MidiR;
189
190 int LPANTABLE[0x20000];
191 int RPANTABLE[0x20000];
192
193 int TimPris[3];
194 int TimCnt[3];
195
196 // DMA stuff
197 UINT32 aica_dmea;
198 UINT16 aica_drga;
199 UINT16 aica_dtlg;
200
201 int ARTABLE[64], DRTABLE[64];
202
203 struct _AICADSP DSP;
204
205 struct sARM7 *cpu;
206
207 INT16 *bufferl;
208 INT16 *bufferr;
209
210 int length;
211
212 signed short *RBUFDST; //this points to where the sample will be stored in the RingBuf
213 };
214
215 //static struct _AICA *AllocedAICA;
216
217 static const float SDLT[16]={-1000000.0,-42.0,-39.0,-36.0,-33.0,-30.0,-27.0,-24.0,-21.0,-18.0,-15.0,-12.0,-9.0,-6.0,-3.0,0.0};
218
DecodeSCI(struct _AICA * AICA,unsigned char irq)219 static unsigned char DecodeSCI(struct _AICA *AICA, unsigned char irq)
220 {
221 unsigned char SCI=0;
222 unsigned char v;
223 v=(SCILV0((AICA))&(1<<irq))?1:0;
224 SCI|=v;
225 v=(SCILV1((AICA))&(1<<irq))?1:0;
226 SCI|=v<<1;
227 v=(SCILV2((AICA))&(1<<irq))?1:0;
228 SCI|=v<<2;
229 return SCI;
230 }
231
ResetInterrupts(struct _AICA * AICA)232 static void ResetInterrupts(struct _AICA *AICA)
233 {
234 #if 0
235 UINT32 reset = AICA->udata.data[0xa4/2];
236 if (reset & 0x40)
237 AICA->IntARMCB(-AICA->IrqTimA);
238 if (reset & 0x180)
239 AICA->IntARMCB(-AICA->IrqTimBC);
240 #endif
241 }
242
CheckPendingIRQ(struct _AICA * AICA)243 static void CheckPendingIRQ(struct _AICA *AICA)
244 {
245 UINT32 pend=AICA->udata.data[0xa0/2];
246 UINT32 en=AICA->udata.data[0x9c/2];
247 if(AICA->MidiW!=AICA->MidiR)
248 {
249 AICA->IRQL = AICA->IrqMidi;
250 AICA->IntARMCB(AICA->cpu, 1);
251 return;
252 }
253 if(!pend)
254 return;
255 if(pend&0x40)
256 if(en&0x40)
257 {
258 AICA->IRQL = AICA->IrqTimA;
259 AICA->IntARMCB(AICA->cpu, 1);
260 return;
261 }
262 if(pend&0x80)
263 if(en&0x80)
264 {
265 AICA->IRQL = AICA->IrqTimBC;
266 AICA->IntARMCB(AICA->cpu, 1);
267 return;
268 }
269 if(pend&0x100)
270 if(en&0x100)
271 {
272 AICA->IRQL = AICA->IrqTimBC;
273 AICA->IntARMCB(AICA->cpu, 1);
274 return;
275 }
276 }
277
Get_AR(struct _AICA * AICA,int base,int R)278 static int Get_AR(struct _AICA *AICA,int base,int R)
279 {
280 int Rate=base+(R<<1);
281 if(Rate>63) Rate=63;
282 if(Rate<0) Rate=0;
283 return AICA->ARTABLE[Rate];
284 }
285
Get_DR(struct _AICA * AICA,int base,int R)286 static int Get_DR(struct _AICA *AICA,int base,int R)
287 {
288 int Rate=base+(R<<1);
289 if(Rate>63) Rate=63;
290 if(Rate<0) Rate=0;
291 return AICA->DRTABLE[Rate];
292 }
293
Get_RR(struct _AICA * AICA,int base,int R)294 static int Get_RR(struct _AICA *AICA,int base,int R)
295 {
296 int Rate=base+(R<<1);
297 if(Rate>63) Rate=63;
298 if(Rate<0) Rate=0;
299 return AICA->DRTABLE[Rate];
300 }
301
Compute_EG(struct _AICA * AICA,struct _SLOT * slot)302 static void Compute_EG(struct _AICA *AICA,struct _SLOT *slot)
303 {
304 int octave=OCT(slot);
305 int rate;
306 if(octave&8) octave=octave-16;
307 if(KRS(slot)!=0xf)
308 rate=octave+2*KRS(slot)+((FNS(slot)>>9)&1);
309 else
310 rate=0; //rate=((FNS(slot)>>9)&1);
311
312 slot->EG.volume=0x17f<<EG_SHIFT;
313 slot->EG.AR=Get_AR(AICA,rate,AR(slot));
314 slot->EG.D1R=Get_DR(AICA,rate,D1R(slot));
315 slot->EG.D2R=Get_DR(AICA,rate,D2R(slot));
316 slot->EG.RR=Get_RR(AICA,rate,RR(slot));
317 slot->EG.DL=0x1f-DL(slot);
318 }
319
320 static void AICA_StopSlot(struct _SLOT *slot,int keyoff);
321
EG_Update(struct _SLOT * slot)322 static int EG_Update(struct _SLOT *slot)
323 {
324 switch(slot->EG.state)
325 {
326 case ATTACK:
327 slot->EG.volume+=slot->EG.AR;
328 if(slot->EG.volume>=(0x3ff<<EG_SHIFT))
329 {
330 if (!LPSLNK(slot))
331 {
332 slot->EG.state=DECAY1;
333 if(slot->EG.D1R>=(1024<<EG_SHIFT)) //Skip DECAY1, go directly to DECAY2
334 slot->EG.state=DECAY2;
335 }
336 slot->EG.volume=0x3ff<<EG_SHIFT;
337 }
338 break;
339 case DECAY1:
340 slot->EG.volume-=slot->EG.D1R;
341 if(slot->EG.volume<=0)
342 slot->EG.volume=0;
343 if(slot->EG.volume>>(EG_SHIFT+5)<slot->EG.DL)
344 slot->EG.state=DECAY2;
345 break;
346 case DECAY2:
347 if(D2R(slot)==0)
348 return (slot->EG.volume>>EG_SHIFT)<<(SHIFT-10);
349 slot->EG.volume-=slot->EG.D2R;
350 if(slot->EG.volume<=0)
351 slot->EG.volume=0;
352
353 break;
354 case RELEASE:
355 slot->EG.volume-=slot->EG.RR;
356 if(slot->EG.volume<=0)
357 {
358 slot->EG.volume=0;
359 AICA_StopSlot(slot,0);
360 // slot->EG.volume=0x17f<<EG_SHIFT;
361 // slot->EG.state=ATTACK;
362 }
363 break;
364 default:
365 return 1<<SHIFT;
366 }
367 return (slot->EG.volume>>EG_SHIFT)<<(SHIFT-10);
368 }
369
AICA_Step(struct _SLOT * slot)370 static UINT32 AICA_Step(struct _SLOT *slot)
371 {
372 int octave=OCT(slot);
373 UINT32 Fn;
374
375 Fn=(FNS_Table[FNS(slot)]); //24.8
376 if(octave&8)
377 Fn>>=(16-octave);
378 else
379 Fn<<=octave;
380
381 return Fn/(44100);
382 }
383
384
Compute_LFO(struct _SLOT * slot)385 static void Compute_LFO(struct _SLOT *slot)
386 {
387 if(PLFOS(slot)!=0)
388 AICALFO_ComputeStep(&(slot->PLFO),LFOF(slot),PLFOWS(slot),PLFOS(slot),0);
389 if(ALFOS(slot)!=0)
390 AICALFO_ComputeStep(&(slot->ALFO),LFOF(slot),ALFOWS(slot),ALFOS(slot),1);
391 }
392
393 #define ADPCMSHIFT 8
394 #define ADFIX(f) (int) ((float) f*(float) (1<<ADPCMSHIFT))
395
396 const int TableQuant[8]={ADFIX(0.8984375),ADFIX(0.8984375),ADFIX(0.8984375),ADFIX(0.8984375),ADFIX(1.19921875),ADFIX(1.59765625),ADFIX(2.0),ADFIX(2.3984375)};
397 const int quant_mul[16]= { 1, 3, 5, 7, 9, 11, 13, 15, -1, -3, -5, -7, -9, -11, -13, -15};
398
InitADPCM(int * PrevSignal,int * PrevQuant)399 void InitADPCM(int *PrevSignal, int *PrevQuant)
400 {
401 *PrevSignal=0;
402 *PrevQuant=0x7f;
403 }
404
DecodeADPCM(int * PrevSignal,unsigned char Delta,int * PrevQuant)405 static INLINE signed short DecodeADPCM(int *PrevSignal, unsigned char Delta, int *PrevQuant)
406 {
407 int x = *PrevQuant * quant_mul [Delta & 15];
408 x = *PrevSignal + ((int)(x + ((UINT32)x >> 29)) >> 3);
409 *PrevSignal=ICLIP16(x);
410 *PrevQuant=(*PrevQuant*TableQuant[Delta&7])>>ADPCMSHIFT;
411 *PrevQuant=(*PrevQuant<0x7f)?0x7f:((*PrevQuant>0x6000)?0x6000:*PrevQuant);
412 return *PrevSignal;
413 }
414
AICA_StartSlot(struct _AICA * AICA,struct _SLOT * slot)415 static void AICA_StartSlot(struct _AICA *AICA, struct _SLOT *slot)
416 {
417 UINT64 start_offset;
418
419 slot->active=1;
420 slot->Backwards=0;
421 slot->cur_addr=0; slot->nxt_addr=1<<SHIFT; slot->prv_addr=-1;
422 start_offset = SA(slot); // AICA can play 16-bit samples from any boundry
423 slot->base=&AICA->AICARAM[start_offset];
424 slot->step=AICA_Step(slot);
425 Compute_EG(AICA,slot);
426 slot->EG.state=ATTACK;
427 slot->EG.volume=0x17f<<EG_SHIFT;
428 Compute_LFO(slot);
429
430 if (PCMS(slot) >= 2)
431 {
432 UINT8 *base;
433 UINT32 curstep, steps_to_go;
434
435 slot->curstep = 0;
436 slot->adbase = (unsigned char *) (AICA->AICARAM+((SA(slot))&0x7fffff));
437 InitADPCM(&(slot->cur_sample), &(slot->cur_quant));
438 InitADPCM(&(slot->cur_lpsample), &(slot->cur_lpquant));
439
440 // walk to the ADPCM state at LSA
441 curstep = 0;
442 base = slot->adbase;
443 steps_to_go = LSA(slot);
444
445 while (curstep < steps_to_go)
446 {
447 int shift1, delta1;
448 shift1 = 4*((curstep&1));
449 delta1 = (*base>>shift1)&0xf;
450 DecodeADPCM(&(slot->cur_lpsample),delta1,&(slot->cur_lpquant));
451 curstep++;
452 if (!(curstep & 1))
453 {
454 base++;
455 }
456 }
457
458 slot->cur_lpstep = curstep;
459 slot->adlpbase = base;
460
461 // on real hardware this creates undefined behavior.
462 if (LSA(slot) > LEA(slot))
463 {
464 slot->udata.data[0xc/2] = 0xffff;
465 }
466 }
467 }
468
AICA_StopSlot(struct _SLOT * slot,int keyoff)469 static void AICA_StopSlot(struct _SLOT *slot,int keyoff)
470 {
471 if(keyoff /*&& slot->EG.state!=RELEASE*/)
472 {
473 slot->EG.state=RELEASE;
474 }
475 else
476 {
477 slot->active=0;
478 }
479 slot->udata.data[0]&=~0x4000;
480
481 }
482
483 #define log_base_2(n) (log((float) n)/log((float) 2))
484
AICA_Init(struct _AICA * AICA,const struct AICAinterface * intf)485 static void AICA_Init(struct _AICA *AICA, const struct AICAinterface *intf)
486 {
487 int i=0;
488
489 AICA->IrqTimA = AICA->IrqTimBC = AICA->IrqMidi = 0;
490 AICA->MidiR=AICA->MidiW=0;
491 AICA->MidiOutR=AICA->MidiOutW=0;
492
493 // get AICA RAM
494 {
495 memset(AICA,0,sizeof(*AICA));
496
497 if (!i)
498 {
499 AICA->Master=1;
500 }
501 else
502 {
503 AICA->Master=0;
504 }
505
506 if (intf->region)
507 {
508 AICA->AICARAM = &intf->cpu->dc_ram[0];
509 AICA->AICARAM_LENGTH = 2*1024*1024;
510 AICA->DSP.AICARAM = (UINT16 *)AICA->AICARAM;
511 AICA->DSP.AICARAM_LENGTH = (2*1024*1024)/2;
512 AICA->cpu = intf->cpu;
513 }
514 }
515
516 for(i=0;i<0x400;++i)
517 {
518 float fcent=(double) 1200.0*log_base_2((double)(((double) 1024.0+(double)i)/(double)1024.0));
519 fcent=(double) 44100.0*pow(2.0,fcent/1200.0);
520 FNS_Table[i]=(float) (1<<SHIFT) *fcent;
521 }
522
523 for(i=0;i<0x400;++i)
524 {
525 float envDB=((float)(3*(i-0x3ff)))/32.0;
526 float scale=(float)(1<<SHIFT);
527 EG_TABLE[i]=(INT32)(pow(10.0,envDB/20.0)*scale);
528 }
529
530 for(i=0;i<0x20000;++i)
531 {
532 int iTL =(i>>0x0)&0xff;
533 int iPAN=(i>>0x8)&0x1f;
534 int iSDL=(i>>0xD)&0x0F;
535 float TL=1.0;
536 float SegaDB=0;
537 float fSDL=1.0;
538 float PAN=1.0;
539 float LPAN,RPAN;
540
541 if(iTL&0x01) SegaDB-=0.4;
542 if(iTL&0x02) SegaDB-=0.8;
543 if(iTL&0x04) SegaDB-=1.5;
544 if(iTL&0x08) SegaDB-=3;
545 if(iTL&0x10) SegaDB-=6;
546 if(iTL&0x20) SegaDB-=12;
547 if(iTL&0x40) SegaDB-=24;
548 if(iTL&0x80) SegaDB-=48;
549
550 TL=pow(10.0,SegaDB/20.0);
551
552 SegaDB=0;
553 if(iPAN&0x1) SegaDB-=3;
554 if(iPAN&0x2) SegaDB-=6;
555 if(iPAN&0x4) SegaDB-=12;
556 if(iPAN&0x8) SegaDB-=24;
557
558 if((iPAN&0xf)==0xf) PAN=0.0;
559 else PAN=pow(10.0,SegaDB/20.0);
560
561 if(iPAN<0x10)
562 {
563 LPAN=PAN;
564 RPAN=1.0;
565 }
566 else
567 {
568 RPAN=PAN;
569 LPAN=1.0;
570 }
571
572 if(iSDL)
573 fSDL=pow(10.0,(SDLT[iSDL])/20.0);
574 else
575 fSDL=0.0;
576
577 AICA->LPANTABLE[i]=FIX((4.0*LPAN*TL*fSDL));
578 AICA->RPANTABLE[i]=FIX((4.0*RPAN*TL*fSDL));
579 }
580
581 AICA->ARTABLE[0]=AICA->DRTABLE[0]=0; //Infinite time
582 AICA->ARTABLE[1]=AICA->DRTABLE[1]=0; //Infinite time
583 for(i=2;i<64;++i)
584 {
585 double t,step,scale;
586 t=ARTimes[i]; //In ms
587 if(t!=0.0)
588 {
589 step=(1023*1000.0)/((float) 44100.0f*t);
590 scale=(double) (1<<EG_SHIFT);
591 AICA->ARTABLE[i]=(int) (step*scale);
592 }
593 else
594 AICA->ARTABLE[i]=1024<<EG_SHIFT;
595
596 t=DRTimes[i]; //In ms
597 step=(1023*1000.0)/((float) 44100.0f*t);
598 scale=(double) (1<<EG_SHIFT);
599 AICA->DRTABLE[i]=(int) (step*scale);
600 }
601
602 // make sure all the slots are off
603 for(i=0;i<64;++i)
604 {
605 AICA->Slots[i].slot=i;
606 AICA->Slots[i].active=0;
607 AICA->Slots[i].base=NULL;
608 AICA->Slots[i].EG.state=RELEASE;
609 AICA->Slots[i].mslc=0;
610 }
611
612 AICALFO_Init();
613 AICA->buffertmpl=(signed int*) malloc(44100*sizeof(signed int));
614 AICA->buffertmpr=(signed int*) malloc(44100*sizeof(signed int));
615 memset(AICA->buffertmpl,0,44100*sizeof(signed int));
616 memset(AICA->buffertmpr,0,44100*sizeof(signed int));
617
618 // no "pend"
619 AICA[0].udata.data[0xa0/2] = 0;
620 //AICA[1].udata.data[0x20/2] = 0;
621 AICA->TimCnt[0] = 0xffff;
622 AICA->TimCnt[1] = 0xffff;
623 AICA->TimCnt[2] = 0xffff;
624 }
625
AICA_UpdateSlotReg(struct _AICA * AICA,int s,int r)626 static void AICA_UpdateSlotReg(struct _AICA *AICA,int s,int r)
627 {
628 struct _SLOT *slot=AICA->Slots+s;
629 int sl;
630 switch(r&0x7f)
631 {
632 case 0:
633 case 1:
634 if(KEYONEX(slot))
635 {
636 for(sl=0;sl<64;++sl)
637 {
638 struct _SLOT *s2=AICA->Slots+sl;
639 {
640 if(KEYONB(s2) && s2->EG.state==RELEASE/*&& !s2->active*/)
641 {
642 if(s2->mslc) AICA->udata.data[0x10] &= 0x7FFF; // reset LP at KEY_ON
643 AICA_StartSlot(AICA, s2);
644
645 #if 0
646 printf("StartSlot[%02X]: SSCTL %01X SA %06X LSA %04X LEA %04X PCMS %01X LPCTL %01X\n",sl,SSCTL(s2),SA(s2),LSA(s2),LEA(s2),PCMS(s2),LPCTL(s2));
647 printf(" AR %02X D1R %02X D2R %02X RR %02X DL %02X KRS %01X LPSLNK %01X\n",AR(s2),D1R(s2),D2R(s2),RR(s2),DL(s2),KRS(s2),LPSLNK(s2)>>14);
648 printf(" TL %02X OCT %01X FNS %03X\n",TL(s2),OCT(s2),FNS(s2));
649 printf(" LFORE %01X LFOF %02X ALFOWS %01X ALFOS %01X PLFOWS %01X PLFOS %01X\n",LFORE(s2),LFOF(s2),ALFOWS(s2),ALFOS(s2),PLFOWS(s2),PLFOS(s2));
650 printf(" IMXL %01X ISEL %01X DISDL %01X DIPAN %02X\n",IMXL(s2),ISEL(s2),DISDL(s2),DIPAN(s2));
651 printf("\n");
652 fflush(stdout);
653 #endif
654 }
655 if(!KEYONB(s2) /*&& s2->active*/)
656 {
657 AICA_StopSlot(s2,1);
658 }
659 }
660 }
661 slot->udata.data[0]&=~0x8000;
662 }
663 break;
664 case 0x18:
665 case 0x19:
666 slot->step=AICA_Step(slot);
667 break;
668 case 0x14:
669 case 0x15:
670 slot->EG.RR=Get_RR(AICA,0,RR(slot));
671 slot->EG.DL=0x1f-DL(slot);
672 break;
673 case 0x1c:
674 case 0x1d:
675 Compute_LFO(slot);
676 break;
677 case 0x24:
678 // printf("[%02d]: %x to DISDL/DIPAN (PC=%x)\n", s, slot->udata.data[0x24/2], arm7_get_register(15));
679 break;
680 }
681 }
682
AICA_UpdateReg(struct _AICA * AICA,int reg)683 static void AICA_UpdateReg(struct _AICA *AICA, int reg)
684 {
685 switch(reg&0xff)
686 {
687 case 0x4:
688 case 0x5:
689 {
690 unsigned int v=RBL(AICA);
691 AICA->DSP.RBP=RBP(AICA);
692 if(v==0)
693 AICA->DSP.RBL=8*1024;
694 else if(v==1)
695 AICA->DSP.RBL=16*1024;
696 else if(v==2)
697 AICA->DSP.RBL=32*1024;
698 else if(v==3)
699 AICA->DSP.RBL=64*1024;
700 }
701 break;
702 case 0x8:
703 case 0x9:
704 AICA_MidiIn(AICA, 0, AICA->udata.data[0x8/2]&0xff, 0);
705 break;
706 case 0x12:
707 case 0x13:
708 case 0x14:
709 case 0x15:
710 case 0x16:
711 case 0x17:
712 break;
713 case 0x90:
714 case 0x91:
715 if(AICA->Master)
716 {
717 AICA->TimPris[0]=1<<((AICA->udata.data[0x90/2]>>8)&0x7);
718 AICA->TimCnt[0]=(AICA->udata.data[0x90/2]&0xff)<<8;
719 }
720 break;
721 case 0x94:
722 case 0x95:
723 if(AICA->Master)
724 {
725 AICA->TimPris[1]=1<<((AICA->udata.data[0x94/2]>>8)&0x7);
726 AICA->TimCnt[1]=(AICA->udata.data[0x94/2]&0xff)<<8;
727 }
728 break;
729 case 0x98:
730 case 0x99:
731 if(AICA->Master)
732 {
733 AICA->TimPris[2]=1<<((AICA->udata.data[0x98/2]>>8)&0x7);
734 AICA->TimCnt[2]=(AICA->udata.data[0x98/2]&0xff)<<8;
735 }
736 break;
737 case 0xa4: //SCIRE
738 case 0xa5:
739
740 if(AICA->Master)
741 {
742 AICA->udata.data[0xa0/2] &= ~AICA->udata.data[0xa4/2];
743 ResetInterrupts(AICA);
744
745 // behavior from real hardware (SCSP, assumed to carry over): if you SCIRE a timer that's expired,
746 // it'll immediately pop up again
747 if (AICA->TimCnt[0] >= 0xff00)
748 {
749 AICA->udata.data[0xa0/2] |= 0x40;
750 }
751 if (AICA->TimCnt[1] >= 0xff00)
752 {
753 AICA->udata.data[0xa0/2] |= 0x80;
754 }
755 if (AICA->TimCnt[2] >= 0xff00)
756 {
757 AICA->udata.data[0xa0/2] |= 0x100;
758 }
759 }
760 break;
761 case 0xa8:
762 case 0xa9:
763 case 0xac:
764 case 0xad:
765 case 0xb0:
766 case 0xb1:
767 if(AICA->Master)
768 {
769 AICA->IrqTimA=DecodeSCI(AICA,SCITMA);
770 AICA->IrqTimBC=DecodeSCI(AICA,SCITMB);
771 AICA->IrqMidi=DecodeSCI(AICA,SCIMID);
772 }
773 break;
774 }
775 }
776
AICA_UpdateSlotRegR(struct _AICA * AICA,int slot,int reg)777 static void AICA_UpdateSlotRegR(struct _AICA *AICA, int slot,int reg)
778 {
779
780 }
781
AICA_UpdateRegR(struct _AICA * AICA,int reg)782 static void AICA_UpdateRegR(struct _AICA *AICA, int reg)
783 {
784 switch(reg&0xff)
785 {
786 case 8:
787 case 9:
788 {
789 unsigned short v=AICA->udata.data[0x8/2];
790 v&=0xff00;
791 v|=AICA->MidiStack[AICA->MidiR];
792 AICA->IntARMCB(AICA->cpu, 0); // cancel the IRQ
793 if(AICA->MidiR!=AICA->MidiW)
794 {
795 ++AICA->MidiR;
796 AICA->MidiR&=15;
797 }
798 AICA->udata.data[0x8/2]=v;
799 }
800 break;
801
802 case 0x10: // LP check
803 case 0x11:
804 {
805 //int MSLC = (AICA->udata.data[0xc/2]>>8) & 0x3f; // which slot are we monitoring?
806 }
807 break;
808
809 case 0x14: // CA (slot address)
810 case 0x15:
811 {
812 int MSLC = (AICA->udata.data[0xc/2]>>8) & 0x3f; // which slot are we monitoring?
813 unsigned int CA = AICA->Slots[MSLC].cur_addr>>(SHIFT+12);
814
815 AICA->udata.data[0x14/2] = CA;
816 }
817 break;
818 }
819 }
820
AICA_w16(struct _AICA * AICA,unsigned int addr,unsigned short val)821 static void AICA_w16(struct _AICA *AICA,unsigned int addr,unsigned short val)
822 {
823 addr&=0xffff;
824 if(addr<0x2000)
825 {
826 int slot=addr/0x80;
827 addr&=0x7f;
828 // printf("%x to slot %d offset %x\n", val, slot, addr);
829 *((unsigned short *) (AICA->Slots[slot].udata.datab+(addr))) = val;
830 AICA_UpdateSlotReg(AICA,slot,addr&0x7f);
831 }
832 else if (addr < 0x2800)
833 {
834 if (addr <= 0x2044)
835 {
836 // printf("%x to EFSxx slot %d (addr %x)\n", val, (addr-0x2000)/4, addr&0x7f);
837 AICA->EFSPAN[addr&0x7f] = val;
838 }
839 }
840 else if(addr<0x3000)
841 {
842 if (addr < 0x28be)
843 {
844 // printf("%x to AICA global @ %x\n", val, addr & 0xff);
845 *((unsigned short *) (AICA->udata.datab+((addr&0xff)))) = val;
846 AICA_UpdateReg(AICA, addr&0xff);
847 }
848 else if (addr == 0x2d00)
849 {
850 AICA->IRQL = val;
851 }
852 else if (addr == 0x2d04)
853 {
854 AICA->IRQR = val;
855
856 if (val)
857 {
858 AICA->IntARMCB(AICA->cpu, 0);
859 }
860 }
861 }
862 else
863 {
864 //DSP
865 if(addr<0x3200) //COEF
866 *((unsigned short *) (AICA->DSP.COEF+(addr-0x3000)/2))=val;
867 else if(addr<0x3400)
868 *((unsigned short *) (AICA->DSP.MADRS+(addr-0x3200)/2))=val;
869 else if(addr<0x3c00)
870 {
871 *((unsigned short *) (AICA->DSP.MPRO+(addr-0x3400)/2))=val;
872
873 if (addr == 0x3bfe)
874 {
875 AICADSP_Start(&AICA->DSP);
876 }
877 }
878 }
879 }
880
AICA_r16(struct _AICA * AICA,unsigned int addr)881 static unsigned short AICA_r16(struct _AICA *AICA, unsigned int addr)
882 {
883 unsigned short v=0;
884 addr&=0xffff;
885 if(addr<0x2000)
886 {
887 int slot=addr/0x80;
888 addr&=0x7f;
889 AICA_UpdateSlotRegR(AICA, slot,addr&0x7f);
890 v=*((unsigned short *) (AICA->Slots[slot].udata.datab+(addr)));
891 }
892 else if(addr<0x3000)
893 {
894 if (addr <= 0x2044)
895 {
896 v = AICA->EFSPAN[addr&0x7f];
897 }
898 else if (addr < 0x28be)
899 {
900 AICA_UpdateRegR(AICA, addr&0xff);
901 v= *((unsigned short *) (AICA->udata.datab+((addr&0xff))));
902 if((addr&0xfe)==0x10) AICA->udata.data[0x10/2] &= 0x7FFF; // reset LP on read
903 }
904 else if (addr == 0x2d00)
905 {
906 return AICA->IRQL;
907 }
908 else if (addr == 0x2d04)
909 {
910 return AICA->IRQR;
911 }
912 }
913 // else if (addr<0x700)
914 // v=AICA->RINGBUF[(addr-0x600)/2];
915 return v;
916 }
917
918
919 #define REVSIGN(v) ((~v)+1)
920
AICA_TimersAddTicks(struct _AICA * AICA,int ticks)921 void AICA_TimersAddTicks(struct _AICA *AICA, int ticks)
922 {
923 if(AICA->TimCnt[0]<=0xff00)
924 {
925 AICA->TimCnt[0] += ticks << (8-((AICA->udata.data[0x90/2]>>8)&0x7));
926 if (AICA->TimCnt[0] >= 0xFF00)
927 {
928 AICA->TimCnt[0] = 0xFFFF;
929 AICA->udata.data[0xa0/2]|=0x40;
930 }
931 AICA->udata.data[0x90/2]&=0xff00;
932 AICA->udata.data[0x90/2]|=AICA->TimCnt[0]>>8;
933 }
934
935 if(AICA->TimCnt[1]<=0xff00)
936 {
937 AICA->TimCnt[1] += ticks << (8-((AICA->udata.data[0x94/2]>>8)&0x7));
938 if (AICA->TimCnt[1] >= 0xFF00)
939 {
940 AICA->TimCnt[1] = 0xFFFF;
941 AICA->udata.data[0xa0/2]|=0x80;
942 }
943 AICA->udata.data[0x94/2]&=0xff00;
944 AICA->udata.data[0x94/2]|=AICA->TimCnt[1]>>8;
945 }
946
947 if(AICA->TimCnt[2]<=0xff00)
948 {
949 AICA->TimCnt[2] += ticks << (8-((AICA->udata.data[0x98/2]>>8)&0x7));
950 if (AICA->TimCnt[2] >= 0xFF00)
951 {
952 AICA->TimCnt[2] = 0xFFFF;
953 AICA->udata.data[0xa0/2]|=0x100;
954 }
955 AICA->udata.data[0x98/2]&=0xff00;
956 AICA->udata.data[0x98/2]|=AICA->TimCnt[2]>>8;
957 }
958 }
959
AICA_UpdateSlot(struct _AICA * AICA,struct _SLOT * slot)960 static INLINE INT32 AICA_UpdateSlot(struct _AICA *AICA, struct _SLOT *slot)
961 {
962 INT32 sample, fpart;
963 int cur_sample; //current sample
964 int nxt_sample; //next sample
965 int step=slot->step;
966 UINT32 addr1,addr2; // current and next sample addresses
967
968 if(SSCTL(slot)!=0) //no FM or noise yet
969 return 0;
970
971 if(PLFOS(slot)!=0)
972 {
973 step=step*AICAPLFO_Step(&(slot->PLFO));
974 step>>=SHIFT;
975 }
976
977 if(PCMS(slot) == 0)
978 {
979 addr1=(slot->cur_addr>>(SHIFT-1))&0x7ffffe;
980 addr2=(slot->nxt_addr>>(SHIFT-1))&0x7ffffe;
981 }
982 else
983 {
984 addr1=slot->cur_addr>>SHIFT;
985 addr2=slot->nxt_addr>>SHIFT;
986 }
987
988 if(PCMS(slot) == 1) // 8-bit signed
989 {
990 INT8 *p1=(signed char *) (AICA->AICARAM+(((SA(slot)+addr1))&0x7fffff));
991 INT8 *p2=(signed char *) (AICA->AICARAM+(((SA(slot)+addr2))&0x7fffff));
992 cur_sample = p1[0] << 8;
993 nxt_sample = p2[0] << 8;
994 }
995 else if (PCMS(slot) == 0) //16 bit signed
996 {
997 INT16 *p1=(signed short *) (AICA->AICARAM+((SA(slot)+addr1)&0x7fffff));
998 INT16 *p2=(signed short *) (AICA->AICARAM+((SA(slot)+addr2)&0x7fffff));
999 cur_sample = LE16(p1[0]);
1000 nxt_sample = LE16(p2[0]);
1001 }
1002 else // 4-bit ADPCM
1003 {
1004 UINT8 *base= slot->adbase;
1005 UINT32 steps_to_go = addr2, curstep = slot->curstep;
1006
1007 if (base)
1008 {
1009 cur_sample = slot->cur_sample; // may already contains current decoded sample
1010
1011 // seek to the interpolation sample
1012 while (curstep < steps_to_go)
1013 {
1014 int shift1, delta1;
1015 shift1 = 4*((curstep&1));
1016 delta1 = (*base>>shift1)&0xf;
1017 DecodeADPCM(&(slot->cur_sample),delta1,&(slot->cur_quant));
1018 curstep++;
1019 if (!(curstep & 1))
1020 {
1021 base++;
1022 }
1023 if (curstep == addr1)
1024 cur_sample = slot->cur_sample;
1025 }
1026 nxt_sample = slot->cur_sample;
1027
1028 slot->adbase = base;
1029 slot->curstep = curstep;
1030 }
1031 else
1032 {
1033 cur_sample = nxt_sample = 0;
1034 }
1035 }
1036 fpart = slot->cur_addr & ((1<<SHIFT)-1);
1037 sample=cur_sample*((1<<SHIFT)-fpart)+nxt_sample*fpart;
1038 sample>>=SHIFT;
1039
1040 slot->prv_addr=slot->cur_addr;
1041 slot->cur_addr+=step;
1042 slot->nxt_addr=slot->cur_addr+(1<<SHIFT);
1043
1044 addr1=slot->cur_addr>>SHIFT;
1045 addr2=slot->nxt_addr>>SHIFT;
1046
1047 if(addr1>=LSA(slot))
1048 {
1049 if(LPSLNK(slot) && slot->EG.state==ATTACK)
1050 slot->EG.state = DECAY1;
1051 }
1052
1053 switch(LPCTL(slot))
1054 {
1055 case 0: //no loop
1056 if(addr2>=LSA(slot) && addr2>=LEA(slot)) // if next sample exceed then current must exceed too
1057 {
1058 //slot->active=0;
1059 if(slot->mslc) AICA->udata.data[8] |= 0x8000;
1060 AICA_StopSlot(slot,0);
1061 }
1062 break;
1063 case 1: //normal loop
1064 if(addr2>=LEA(slot))
1065 {
1066 INT32 rem_addr;
1067 if(slot->mslc) AICA->udata.data[8] |= 0x8000;
1068 rem_addr = slot->nxt_addr - (LEA(slot)<<SHIFT);
1069 slot->nxt_addr = (LSA(slot)<<SHIFT) + rem_addr;
1070 if(addr1>=LEA(slot))
1071 {
1072 rem_addr = slot->cur_addr - (LEA(slot)<<SHIFT);
1073 slot->cur_addr = (LSA(slot)<<SHIFT) + rem_addr;
1074 }
1075
1076 if(PCMS(slot)>=2)
1077 {
1078 // restore the state @ LSA - the sampler will naturally walk to (LSA + remainder)
1079 slot->adbase = &AICA->AICARAM[SA(slot)+(LSA(slot)/2)];
1080 slot->curstep = LSA(slot);
1081 if (PCMS(slot) == 2)
1082 {
1083 slot->cur_sample = slot->cur_lpsample;
1084 slot->cur_quant = slot->cur_lpquant;
1085 }
1086 //printf("Looping: slot_addr %x LSA %x LEA %x step %x base %x\n", slot->cur_addr>>SHIFT, LSA(slot), LEA(slot), slot->curstep, slot->adbase);
1087 }
1088 }
1089 break;
1090 }
1091
1092 if(ALFOS(slot)!=0)
1093 {
1094 sample=sample*AICAALFO_Step(&(slot->ALFO));
1095 sample>>=SHIFT;
1096 }
1097
1098 if(slot->EG.state==ATTACK)
1099 sample=(sample*EG_Update(slot))>>SHIFT;
1100 else
1101 sample=(sample*EG_TABLE[EG_Update(slot)>>(SHIFT-10)])>>SHIFT;
1102
1103 if(slot->mslc)
1104 {
1105 AICA->udata.data[0x14/2] = addr1;
1106 if (!(AFSEL(AICA)))
1107 {
1108 UINT16 res;
1109
1110 AICA->udata.data[0x10/2] |= slot->EG.state<<13;
1111
1112 res = 0x3FF - (slot->EG.volume>>EG_SHIFT);
1113
1114 res *= 959;
1115 res /= 1024;
1116
1117 if (res > 959) res = 959;
1118
1119 AICA->udata.data[0x10/2] = res;
1120
1121 //AICA->udata.data[0x10/2] |= 0x3FF - (slot->EG.volume>>EG_SHIFT);
1122 }
1123 }
1124
1125 return sample;
1126 }
1127
AICA_DoMasterSamples(struct _AICA * AICA,int nsamples)1128 static void AICA_DoMasterSamples(struct _AICA *AICA, int nsamples)
1129 {
1130 INT16 *bufr,*bufl;
1131 int sl, s, i;
1132
1133 bufr=AICA->bufferr;
1134 bufl=AICA->bufferl;
1135
1136 for(s=0;s<nsamples;++s)
1137 {
1138 INT32 smpl, smpr;
1139
1140 smpl = smpr = 0;
1141
1142 // mix slots' direct output
1143 for(sl=0;sl<64;++sl)
1144 {
1145 struct _SLOT *slot=AICA->Slots+sl;
1146 slot->mslc = (MSLC(AICA)==sl);
1147 AICA->RBUFDST=AICA->RINGBUF+AICA->BUFPTR;
1148 if(AICA->Slots[sl].active)
1149 {
1150 unsigned int Enc;
1151 signed int sample;
1152
1153 sample=AICA_UpdateSlot(AICA, slot);
1154
1155 Enc=((TL(slot))<<0x0)|((IMXL(slot))<<0xd);
1156 AICADSP_SetSample(&AICA->DSP,(sample*AICA->LPANTABLE[Enc])>>(SHIFT-2),ISEL(slot),IMXL(slot));
1157 Enc=((TL(slot))<<0x0)|((DIPAN(slot))<<0x8)|((DISDL(slot))<<0xd);
1158 {
1159 smpl+=(sample*AICA->LPANTABLE[Enc])>>SHIFT;
1160 smpr+=(sample*AICA->RPANTABLE[Enc])>>SHIFT;
1161 }
1162 }
1163
1164 AICA->BUFPTR&=63;
1165 }
1166
1167 // process the DSP
1168 AICADSP_Step(&AICA->DSP);
1169
1170 // mix DSP output
1171 for(i=0;i<16;++i)
1172 {
1173 if(EFSDL(i))
1174 {
1175 unsigned int Enc=((EFPAN(i))<<0x8)|((EFSDL(i))<<0xd);
1176 smpl+=(AICA->DSP.EFREG[i]*AICA->LPANTABLE[Enc])>>SHIFT;
1177 smpr+=(AICA->DSP.EFREG[i]*AICA->RPANTABLE[Enc])>>SHIFT;
1178 }
1179 }
1180
1181 *bufl++ = ICLIP16(smpl>>3);
1182 *bufr++ = ICLIP16(smpr>>3);
1183
1184 AICA_TimersAddTicks(AICA, 1);
1185 CheckPendingIRQ(AICA);
1186 }
1187 }
1188
AICA_IRQCB(void * param)1189 int AICA_IRQCB(void *param)
1190 {
1191 CheckPendingIRQ(param);
1192 return -1;
1193 }
1194
AICA_Update(struct _AICA * AICA,void * param,INT16 ** inputs,INT16 ** buf,int samples)1195 void AICA_Update(struct _AICA *AICA, void *param, INT16 **inputs, INT16 **buf, int samples)
1196 {
1197 AICA->bufferl = buf[0];
1198 AICA->bufferr = buf[1];
1199 AICA->length = samples;
1200 AICA_DoMasterSamples(AICA, samples);
1201 }
1202
aica_start(const void * config)1203 void *aica_start(const void *config)
1204 {
1205 const struct AICAinterface *intf;
1206
1207 struct _AICA *AICA;
1208
1209 AICA = malloc(sizeof(*AICA));
1210 memset(AICA, 0, sizeof(*AICA));
1211
1212 intf = config;
1213
1214 // init the emulation
1215 AICA_Init(AICA, intf);
1216
1217 // set up the IRQ callbacks
1218 {
1219 AICA->IntARMCB = intf->irq_callback[0];
1220
1221 // AICA->stream = stream_create(0, 2, 44100, AICA, AICA_Update);
1222 }
1223
1224 return AICA;
1225 }
1226
aica_stop(struct _AICA * AICA)1227 void aica_stop(struct _AICA *AICA)
1228 {
1229 if (AICA->buffertmpl) {
1230 free (AICA->buffertmpl);
1231 }
1232 if (AICA->buffertmpr) {
1233 free (AICA->buffertmpr);
1234 }
1235 free(AICA);
1236 }
1237
AICA_set_ram_base(struct _AICA * AICA,int which,void * base)1238 void AICA_set_ram_base(struct _AICA *AICA, int which, void *base)
1239 {
1240 if (AICA)
1241 {
1242 AICA->AICARAM = base;
1243 AICA->DSP.AICARAM = base;
1244 }
1245 }
1246
READ16_HANDLER(AICA_0_r)1247 READ16_HANDLER( AICA_0_r )
1248 {
1249 UINT16 res = AICA_r16(AICA, offset*2);
1250
1251 // printf("Read AICA @ %x => %x (PC=%x, R5=%x)\n", offset*2, res, arm7_get_register(15), arm7_get_register(5));
1252
1253 return res;
1254 }
1255
1256 extern UINT32* stv_scu;
1257
WRITE16_HANDLER(AICA_0_w)1258 WRITE16_HANDLER( AICA_0_w )
1259 {
1260 UINT16 tmp;
1261
1262 tmp = AICA_r16(AICA, offset*2);
1263 COMBINE_DATA(&tmp);
1264 AICA_w16(AICA,offset*2, tmp);
1265 }
1266
WRITE16_HANDLER(AICA_MidiIn)1267 WRITE16_HANDLER( AICA_MidiIn )
1268 {
1269 AICA->MidiStack[AICA->MidiW++]=data;
1270 AICA->MidiW &= 15;
1271 }
1272
READ16_HANDLER(AICA_MidiOutR)1273 READ16_HANDLER( AICA_MidiOutR )
1274 {
1275 unsigned char val;
1276
1277 val=AICA->MidiStack[AICA->MidiR++];
1278 AICA->MidiR&=7;
1279 return val;
1280 }
1281
1282