1 #ifndef _MIPS_H 2 #define _MIPS_H 3 4 #include "ao.h" 5 #include "osd_cpu.h" 6 //#include "driver.h" 7 8 typedef void genf(void); 9 typedef int offs_t; 10 11 #define cpu_readop32(pc) program_read_dword_32le(cpu, pc) 12 #define change_pc(pc) \ 13 14 15 #ifdef __GNUC__ 16 #if (__GNUC__ < 2) || ((__GNUC__ == 2) && (__GNUC_MINOR__ <= 7)) 17 #define UNUSEDARG 18 #else 19 #define UNUSEDARG __attribute__((__unused__)) 20 #endif 21 #else 22 #define UNUSEDARG 23 #endif 24 25 typedef int8 (*read8_handler) (UNUSEDARG offs_t offset); 26 typedef void (*write8_handler) (UNUSEDARG offs_t offset, UNUSEDARG int8 data); 27 typedef int16 (*read16_handler) (UNUSEDARG offs_t offset, UNUSEDARG int16 mem_mask); 28 typedef void (*write16_handler)(UNUSEDARG offs_t offset, UNUSEDARG int16 data, UNUSEDARG int16 mem_mask); 29 typedef int32 (*read32_handler) (UNUSEDARG offs_t offset, UNUSEDARG int32 mem_mask); 30 typedef void (*write32_handler)(UNUSEDARG offs_t offset, UNUSEDARG int32 data, UNUSEDARG int32 mem_mask); 31 typedef int64 (*read64_handler) (UNUSEDARG offs_t offset, UNUSEDARG int64 mem_mask); 32 typedef void (*write64_handler)(UNUSEDARG offs_t offset, UNUSEDARG int64 data, UNUSEDARG int64 mem_mask); 33 34 union read_handlers_t 35 { 36 genf * handler; 37 read8_handler handler8; 38 read16_handler handler16; 39 read32_handler handler32; 40 read64_handler handler64; 41 }; 42 43 union write_handlers_t 44 { 45 genf * handler; 46 write8_handler handler8; 47 write16_handler handler16; 48 write32_handler handler32; 49 write64_handler handler64; 50 }; 51 52 struct address_map_t 53 { 54 uint32 flags; /* flags and additional info about this entry */ 55 offs_t start, end; /* start/end (or mask/match) values */ 56 offs_t mirror; /* mirror bits */ 57 offs_t mask; /* mask bits */ 58 union read_handlers_t read; /* read handler callback */ 59 union write_handlers_t write; /* write handler callback */ 60 void * memory; /* pointer to memory backing this entry */ 61 uint32 share; /* index of a shared memory block */ 62 void ** base; /* receives pointer to memory (optional) */ 63 size_t * size; /* receives size of area in bytes (optional) */ 64 }; 65 typedef struct address_map_t *(*construct_map_t)(struct address_map_t *map); 66 67 #define MAX_FILE_SLOTS (32) 68 69 typedef struct 70 { 71 char name[10]; 72 uint32 dispatch; 73 } ExternLibEntries; 74 75 typedef struct 76 { 77 int32 iState; // state of thread 78 79 uint32 flags; // flags 80 uint32 routine; // start of code for the thread 81 uint32 stackloc; // stack location in IOP RAM 82 uint32 stacksize; // stack size 83 uint32 refCon; // user value passed in at CreateThread time 84 85 uint32 waitparm; // what we're waiting on if in one the TS_WAIT* states 86 87 uint32 save_regs[37]; // CPU registers belonging to this thread 88 } Thread; 89 90 typedef struct 91 { 92 uint32 attr; 93 uint32 option; 94 int32 init; 95 int32 current; 96 int32 max; 97 int32 threadsWaiting; 98 int32 inuse; 99 } Semaphore; 100 101 #define SEMA_MAX (64) 102 103 typedef struct 104 { 105 uint32 type; 106 uint32 value; 107 uint32 param; 108 int inUse; 109 } EventFlag; 110 111 typedef struct 112 { 113 uint32 count; 114 uint32 mode; 115 uint32 target; 116 uint32 sysclock; 117 } Counter; 118 119 120 typedef struct 121 { 122 uint32 desc; 123 int32 status; 124 int32 mode; 125 uint32 fhandler; 126 } EvtCtrlBlk[32]; 127 128 typedef struct 129 { 130 int32 iActive; 131 uint32 count; 132 uint32 target; 133 uint32 source; 134 uint32 prescale; 135 uint32 handler; 136 uint32 hparam; 137 uint32 mode; 138 } IOPTimer; 139 140 typedef struct mips_cpu_context_s 141 { 142 int psf_refresh; 143 UINT32 op; 144 UINT32 pc; 145 UINT32 prevpc; 146 UINT32 delayv; 147 UINT32 delayr; 148 UINT32 hi; 149 UINT32 lo; 150 UINT32 r[ 32 ]; 151 UINT32 cp0r[ 32 ]; 152 PAIR cp2cr[ 32 ]; 153 PAIR cp2dr[ 32 ]; 154 int (*irq_callback)(struct mips_cpu_context_s *cpu, int irqline); 155 int mips_ICount; 156 // PSX main RAM 157 uint32 psx_ram[(2*1024*1024)/4]; 158 uint32 psx_scratch[0x400]; 159 // backup image to restart songs 160 uint32 initial_ram[(2*1024*1024)/4]; 161 uint32 initial_scratch[0x400]; 162 163 // spu 164 struct spu_state_s *spu; 165 struct spu2_state_s *spu2; 166 void (*spu_callback)(unsigned char *, long, void *); 167 void *spu_callback_data; 168 169 // state 170 Counter root_cnts[3]; // 3 of the bastards 171 172 EvtCtrlBlk *Event; 173 EvtCtrlBlk *CounterEvent; 174 175 uint32 spu_delay, dma_icr, irq_data, irq_mask, dma_timer, WAI; 176 uint32 dma4_madr, dma4_bcr, dma4_chcr, dma4_delay; 177 uint32 dma7_madr, dma7_bcr, dma7_chcr, dma7_delay; 178 uint32 dma4_cb, dma7_cb, dma4_fval, dma4_flag, dma7_fval, dma7_flag; 179 uint32 irq9_cb, irq9_fval, irq9_flag; 180 181 volatile int softcall_target; 182 int filestat[MAX_FILE_SLOTS]; 183 uint8 *filedata[MAX_FILE_SLOTS]; 184 uint32 filesize[MAX_FILE_SLOTS], filepos[MAX_FILE_SLOTS]; 185 int intr_susp; 186 187 uint64 sys_time; 188 int timerexp; 189 190 int32 iNumLibs; 191 ExternLibEntries reglibs[32]; 192 193 int32 iNumFlags; 194 EventFlag evflags[32]; 195 196 int32 iNumSema; 197 Semaphore semaphores[SEMA_MAX]; 198 199 int32 iNumThreads, iCurThread; 200 Thread threads[32]; 201 IOPTimer iop_timers[8]; 202 int32 iNumTimers; 203 int fcnt; 204 uint32 heap_addr, entry_int; 205 uint32 irq_regs[37]; 206 int irq_mutex; 207 208 } mips_cpu_context; 209 210 union cpuinfo 211 { 212 int64 i; /* generic integers */ 213 void * p; /* generic pointers */ 214 genf * f; /* generic function pointers */ 215 char * s; /* generic strings */ 216 mips_cpu_context *cpu; 217 218 void (*setinfo)(mips_cpu_context *cpu, UINT32 state, union cpuinfo *info);/* CPUINFO_PTR_SET_INFO */ 219 // void (*getcontext)(void *context); /* CPUINFO_PTR_GET_CONTEXT */ 220 // void (*setcontext)(void *context); /* CPUINFO_PTR_SET_CONTEXT */ 221 void (*init)(mips_cpu_context *cpu); /* CPUINFO_PTR_INIT */ 222 void (*reset)(mips_cpu_context *cpu, void *param); /* CPUINFO_PTR_RESET */ 223 void (*exit)(mips_cpu_context *cpu); /* CPUINFO_PTR_EXIT */ 224 int (*execute)(mips_cpu_context *cpu, int cycles); /* CPUINFO_PTR_EXECUTE */ 225 void (*burn)(mips_cpu_context *cpu, int cycles); /* CPUINFO_PTR_BURN */ 226 offs_t (*disassemble)(mips_cpu_context *cpu, char *buffer, offs_t pc); /* CPUINFO_PTR_DISASSEMBLE */ 227 int (*irqcallback)(mips_cpu_context *cpu, int state); /* CPUINFO_PTR_IRQCALLBACK */ 228 int * icount; /* CPUINFO_PTR_INSTRUCTION_COUNTER */ 229 construct_map_t internal_map; /* CPUINFO_PTR_INTERNAL_MEMORY_MAP */ 230 }; 231 232 enum 233 { 234 MIPS_PC = 1, 235 MIPS_DELAYV, MIPS_DELAYR, 236 MIPS_HI, MIPS_LO, 237 MIPS_R0, MIPS_R1, 238 MIPS_R2, MIPS_R3, 239 MIPS_R4, MIPS_R5, 240 MIPS_R6, MIPS_R7, 241 MIPS_R8, MIPS_R9, 242 MIPS_R10, MIPS_R11, 243 MIPS_R12, MIPS_R13, 244 MIPS_R14, MIPS_R15, 245 MIPS_R16, MIPS_R17, 246 MIPS_R18, MIPS_R19, 247 MIPS_R20, MIPS_R21, 248 MIPS_R22, MIPS_R23, 249 MIPS_R24, MIPS_R25, 250 MIPS_R26, MIPS_R27, 251 MIPS_R28, MIPS_R29, 252 MIPS_R30, MIPS_R31, 253 MIPS_CP0R0, MIPS_CP0R1, 254 MIPS_CP0R2, MIPS_CP0R3, 255 MIPS_CP0R4, MIPS_CP0R5, 256 MIPS_CP0R6, MIPS_CP0R7, 257 MIPS_CP0R8, MIPS_CP0R9, 258 MIPS_CP0R10, MIPS_CP0R11, 259 MIPS_CP0R12, MIPS_CP0R13, 260 MIPS_CP0R14, MIPS_CP0R15, 261 MIPS_CP0R16, MIPS_CP0R17, 262 MIPS_CP0R18, MIPS_CP0R19, 263 MIPS_CP0R20, MIPS_CP0R21, 264 MIPS_CP0R22, MIPS_CP0R23, 265 MIPS_CP0R24, MIPS_CP0R25, 266 MIPS_CP0R26, MIPS_CP0R27, 267 MIPS_CP0R28, MIPS_CP0R29, 268 MIPS_CP0R30, MIPS_CP0R31, 269 MIPS_CP2DR0, MIPS_CP2DR1, 270 MIPS_CP2DR2, MIPS_CP2DR3, 271 MIPS_CP2DR4, MIPS_CP2DR5, 272 MIPS_CP2DR6, MIPS_CP2DR7, 273 MIPS_CP2DR8, MIPS_CP2DR9, 274 MIPS_CP2DR10, MIPS_CP2DR11, 275 MIPS_CP2DR12, MIPS_CP2DR13, 276 MIPS_CP2DR14, MIPS_CP2DR15, 277 MIPS_CP2DR16, MIPS_CP2DR17, 278 MIPS_CP2DR18, MIPS_CP2DR19, 279 MIPS_CP2DR20, MIPS_CP2DR21, 280 MIPS_CP2DR22, MIPS_CP2DR23, 281 MIPS_CP2DR24, MIPS_CP2DR25, 282 MIPS_CP2DR26, MIPS_CP2DR27, 283 MIPS_CP2DR28, MIPS_CP2DR29, 284 MIPS_CP2DR30, MIPS_CP2DR31, 285 MIPS_CP2CR0, MIPS_CP2CR1, 286 MIPS_CP2CR2, MIPS_CP2CR3, 287 MIPS_CP2CR4, MIPS_CP2CR5, 288 MIPS_CP2CR6, MIPS_CP2CR7, 289 MIPS_CP2CR8, MIPS_CP2CR9, 290 MIPS_CP2CR10, MIPS_CP2CR11, 291 MIPS_CP2CR12, MIPS_CP2CR13, 292 MIPS_CP2CR14, MIPS_CP2CR15, 293 MIPS_CP2CR16, MIPS_CP2CR17, 294 MIPS_CP2CR18, MIPS_CP2CR19, 295 MIPS_CP2CR20, MIPS_CP2CR21, 296 MIPS_CP2CR22, MIPS_CP2CR23, 297 MIPS_CP2CR24, MIPS_CP2CR25, 298 MIPS_CP2CR26, MIPS_CP2CR27, 299 MIPS_CP2CR28, MIPS_CP2CR29, 300 MIPS_CP2CR30, MIPS_CP2CR31 301 }; 302 303 #define MIPS_INT_NONE ( -1 ) 304 305 #define MIPS_IRQ0 ( 0 ) 306 #define MIPS_IRQ1 ( 1 ) 307 #define MIPS_IRQ2 ( 2 ) 308 #define MIPS_IRQ3 ( 3 ) 309 #define MIPS_IRQ4 ( 4 ) 310 #define MIPS_IRQ5 ( 5 ) 311 312 #define MIPS_BYTE_EXTEND( a ) ( (INT32)(INT8)a ) 313 #define MIPS_WORD_EXTEND( a ) ( (INT32)(INT16)a ) 314 315 #define INS_OP( op ) ( ( op >> 26 ) & 63 ) 316 #define INS_RS( op ) ( ( op >> 21 ) & 31 ) 317 #define INS_RT( op ) ( ( op >> 16 ) & 31 ) 318 #define INS_IMMEDIATE( op ) ( op & 0xffff ) 319 #define INS_TARGET( op ) ( op & 0x3ffffff ) 320 #define INS_RD( op ) ( ( op >> 11 ) & 31 ) 321 #define INS_SHAMT( op ) ( ( op >> 6 ) & 31 ) 322 #define INS_FUNCT( op ) ( op & 63 ) 323 #define INS_CODE( op ) ( ( op >> 6 ) & 0xfffff ) 324 #define INS_CO( op ) ( ( op >> 25 ) & 1 ) 325 #define INS_COFUN( op ) ( op & 0x1ffffff ) 326 #define INS_CF( op ) ( op & 63 ) 327 328 #define GTE_OP( op ) ( ( op >> 20 ) & 31 ) 329 #define GTE_SF( op ) ( ( op >> 19 ) & 1 ) 330 #define GTE_MX( op ) ( ( op >> 17 ) & 3 ) 331 #define GTE_V( op ) ( ( op >> 15 ) & 3 ) 332 #define GTE_CV( op ) ( ( op >> 13 ) & 3 ) 333 #define GTE_CD( op ) ( ( op >> 11 ) & 3 ) /* not used */ 334 #define GTE_LM( op ) ( ( op >> 10 ) & 1 ) 335 #define GTE_CT( op ) ( ( op >> 6 ) & 15 ) /* not used */ 336 #define GTE_FUNCT( op ) ( op & 63 ) 337 338 #define OP_SPECIAL ( 0 ) 339 #define OP_REGIMM ( 1 ) 340 #define OP_J ( 2 ) 341 #define OP_JAL ( 3 ) 342 #define OP_BEQ ( 4 ) 343 #define OP_BNE ( 5 ) 344 #define OP_BLEZ ( 6 ) 345 #define OP_BGTZ ( 7 ) 346 #define OP_ADDI ( 8 ) 347 #define OP_ADDIU ( 9 ) 348 #define OP_SLTI ( 10 ) 349 #define OP_SLTIU ( 11 ) 350 #define OP_ANDI ( 12 ) 351 #define OP_ORI ( 13 ) 352 #define OP_XORI ( 14 ) 353 #define OP_LUI ( 15 ) 354 #define OP_COP0 ( 16 ) 355 #define OP_COP1 ( 17 ) 356 #define OP_COP2 ( 18 ) 357 #define OP_LB ( 32 ) 358 #define OP_LH ( 33 ) 359 #define OP_LWL ( 34 ) 360 #define OP_LW ( 35 ) 361 #define OP_LBU ( 36 ) 362 #define OP_LHU ( 37 ) 363 #define OP_LWR ( 38 ) 364 #define OP_SB ( 40 ) 365 #define OP_SH ( 41 ) 366 #define OP_SWL ( 42 ) 367 #define OP_SW ( 43 ) 368 #define OP_SWR ( 46 ) 369 #define OP_LWC1 ( 49 ) 370 #define OP_LWC2 ( 50 ) 371 #define OP_SWC1 ( 57 ) 372 #define OP_SWC2 ( 58 ) 373 374 /* OP_SPECIAL */ 375 #define FUNCT_SLL ( 0 ) 376 #define FUNCT_SRL ( 2 ) 377 #define FUNCT_SRA ( 3 ) 378 #define FUNCT_SLLV ( 4 ) 379 #define FUNCT_SRLV ( 6 ) 380 #define FUNCT_SRAV ( 7 ) 381 #define FUNCT_JR ( 8 ) 382 #define FUNCT_JALR ( 9 ) 383 #define FUNCT_HLECALL ( 11 ) 384 #define FUNCT_SYSCALL ( 12 ) 385 #define FUNCT_BREAK ( 13 ) 386 #define FUNCT_MFHI ( 16 ) 387 #define FUNCT_MTHI ( 17 ) 388 #define FUNCT_MFLO ( 18 ) 389 #define FUNCT_MTLO ( 19 ) 390 #define FUNCT_MULT ( 24 ) 391 #define FUNCT_MULTU ( 25 ) 392 #define FUNCT_DIV ( 26 ) 393 #define FUNCT_DIVU ( 27 ) 394 #define FUNCT_ADD ( 32 ) 395 #define FUNCT_ADDU ( 33 ) 396 #define FUNCT_SUB ( 34 ) 397 #define FUNCT_SUBU ( 35 ) 398 #define FUNCT_AND ( 36 ) 399 #define FUNCT_OR ( 37 ) 400 #define FUNCT_XOR ( 38 ) 401 #define FUNCT_NOR ( 39 ) 402 #define FUNCT_SLT ( 42 ) 403 #define FUNCT_SLTU ( 43 ) 404 405 /* OP_REGIMM */ 406 #define RT_BLTZ ( 0 ) 407 #define RT_BGEZ ( 1 ) 408 #define RT_BLTZAL ( 16 ) 409 #define RT_BGEZAL ( 17 ) 410 411 /* OP_COP0/OP_COP1/OP_COP2 */ 412 #define RS_MFC ( 0 ) 413 #define RS_CFC ( 2 ) 414 #define RS_MTC ( 4 ) 415 #define RS_CTC ( 6 ) 416 #define RS_BC ( 8 ) 417 418 /* RS_BC */ 419 #define RT_BCF ( 0 ) 420 #define RT_BCT ( 1 ) 421 422 /* OP_COP0 */ 423 #define CF_RFE ( 16 ) 424 425 #ifdef MAME_DEBUG 426 unsigned DasmMIPS(char *buff, unsigned _pc); 427 #endif 428 429 #if (HAS_PSXCPU) 430 void psxcpu_get_info(mips_cpu_context *cpu, UINT32 state, union cpuinfo *info); 431 #endif 432 433 mips_cpu_context *mips_alloc(void); 434 void mips_free (mips_cpu_context *cpu); 435 436 void mips_init(mips_cpu_context *cpu); 437 void mips_exit(mips_cpu_context *cpu); 438 void mips_reset(mips_cpu_context *cpu, void *param ); 439 int mips_execute(mips_cpu_context *cpu, int cycles ); 440 void mips_set_info(mips_cpu_context *cpu, UINT32 state, union cpuinfo *info); 441 void mips_get_info(mips_cpu_context *cpu, UINT32 state, union cpuinfo *info); 442 int mips_execute( mips_cpu_context *cpu, int cycles ); 443 int mips_get_icount(mips_cpu_context *cpu); 444 void mips_set_icount(mips_cpu_context *cpu, int count); 445 446 uint32 mips_get_cause(mips_cpu_context *cpu); 447 uint32 mips_get_status(mips_cpu_context *cpu); 448 void mips_set_status(mips_cpu_context *cpu, uint32 status); 449 uint32 mips_get_ePC(mips_cpu_context *cpu); 450 451 452 void psx_hw_init(mips_cpu_context *cpu); 453 void psx_hw_slice(mips_cpu_context *cpu); 454 void psx_hw_frame(mips_cpu_context *cpu); 455 void ps2_hw_slice(mips_cpu_context *cpu); 456 void ps2_hw_frame(mips_cpu_context *cpu); 457 458 void mips_shorten_frame(mips_cpu_context *cpu); 459 uint32 psf2_load_file(mips_cpu_context *cpu, char *file, uint8 *buf, uint32 buflen); 460 uint32 psf2_load_elf(mips_cpu_context *cpu, uint8 *start, uint32 len); 461 void psx_hw_runcounters(mips_cpu_context *cpu); 462 463 464 void psx_bios_hle(mips_cpu_context *cpu, uint32 pc); 465 void psx_iop_call(mips_cpu_context *cpu, uint32 pc, uint32 callnum); 466 uint8 program_read_byte_32le(mips_cpu_context *cpu, offs_t address); 467 uint16 program_read_word_32le(mips_cpu_context *cpu, offs_t address); 468 uint32 program_read_dword_32le(mips_cpu_context *cpu, offs_t address); 469 void program_write_byte_32le(mips_cpu_context *cpu, offs_t address, uint8 data); 470 void program_write_word_32le(mips_cpu_context *cpu, offs_t address, uint16 data); 471 void program_write_dword_32le(mips_cpu_context *cpu, offs_t address, uint32 data); 472 473 // SPU1 474 void setlength(struct spu_state_s *spu, s32 stop, s32 fade); 475 476 // SPU2 477 void SPU2write(mips_cpu_context *cpu, unsigned long reg, unsigned short val); 478 unsigned short SPU2read(mips_cpu_context *cpu, unsigned long reg); 479 void SPU2readDMA4Mem(mips_cpu_context *cpu, uint32 usPSXMem,int iSize); 480 void SPU2writeDMA4Mem(mips_cpu_context *cpu, uint32 usPSXMem,int iSize); 481 void SPU2readDMA7Mem(mips_cpu_context *cpu, uint32 usPSXMem,int iSize); 482 void SPU2writeDMA7Mem(mips_cpu_context *cpu, uint32 usPSXMem,int iSize); 483 void SPU2interruptDMA4(mips_cpu_context *cpu); 484 void SPU2interruptDMA7(mips_cpu_context *cpu); 485 486 #endif 487