1 /*
2 **
3 ** File: ymf262.c - software implementation of YMF262
4 ** FM sound generator type OPL3
5 **
6 ** Copyright Jarek Burczynski
7 **
8 ** Version 0.2
9 **
10
11 Revision History:
12
13 03-03-2003: initial release
14 - thanks to Olivier Galibert and Chris Hardy for YMF262 and YAC512 chips
15 - thanks to Stiletto for the datasheets
16
17 Features as listed in 4MF262A6 data sheet:
18 1. Registers are compatible with YM3812 (OPL2) FM sound source.
19 2. Up to six sounds can be used as four-operator melody sounds for variety.
20 3. 18 simultaneous melody sounds, or 15 melody sounds with 5 rhythm sounds (with two operators).
21 4. 6 four-operator melody sounds and 6 two-operator melody sounds, or 6 four-operator melody
22 sounds, 3 two-operator melody sounds and 5 rhythm sounds (with four operators).
23 5. 8 selectable waveforms.
24 6. 4-channel sound output.
25 7. YMF262 compabile DAC (YAC512) is available.
26 8. LFO for vibrato and tremolo effedts.
27 9. 2 programable timers.
28 10. Shorter register access time compared with YM3812.
29 11. 5V single supply silicon gate CMOS process.
30 12. 24 Pin SOP Package (YMF262-M), 48 Pin SQFP Package (YMF262-S).
31
32
33 differences between OPL2 and OPL3 not documented in Yamaha datahasheets:
34 - sinus table is a little different: the negative part is off by one...
35
36 - in order to enable selection of four different waveforms on OPL2
37 one must set bit 5 in register 0x01(test).
38 on OPL3 this bit is ignored and 4-waveform select works *always*.
39 (Don't confuse this with OPL3's 8-waveform select.)
40
41 - Envelope Generator: all 15 x rates take zero time on OPL3
42 (on OPL2 15 0 and 15 1 rates take some time while 15 2 and 15 3 rates
43 take zero time)
44
45 - channel calculations: output of operator 1 is in perfect sync with
46 output of operator 2 on OPL3; on OPL and OPL2 output of operator 1
47 is always delayed by one sample compared to output of operator 2
48
49
50 differences between OPL2 and OPL3 shown in datasheets:
51 - YMF262 does not support CSM mode
52
53
54 */
55
56 #include <math.h>
57 #include "mamedef.h"
58 #include <stdlib.h>
59 #include <memory.h>
60 //#include "sndintrf.h"
61 #include "ymf262.h"
62
63 #define NULL ((void *)0)
64
65
66 /* output final shift */
67 #if (OPL3_SAMPLE_BITS==16)
68 #define FINAL_SH (0)
69 #define MAXOUT (+32767)
70 #define MINOUT (-32768)
71 #else
72 #define FINAL_SH (8)
73 #define MAXOUT (+127)
74 #define MINOUT (-128)
75 #endif
76
77
78 #define FREQ_SH 16 /* 16.16 fixed point (frequency calculations) */
79 #define EG_SH 16 /* 16.16 fixed point (EG timing) */
80 #define LFO_SH 24 /* 8.24 fixed point (LFO calculations) */
81 #define TIMER_SH 16 /* 16.16 fixed point (timers calculations) */
82
83 #define FREQ_MASK ((1<<FREQ_SH)-1)
84
85 /* envelope output entries */
86 #define ENV_BITS 10
87 #define ENV_LEN (1<<ENV_BITS)
88 #define ENV_STEP (128.0/ENV_LEN)
89
90 #define MAX_ATT_INDEX ((1<<(ENV_BITS-1))-1) /*511*/
91 #define MIN_ATT_INDEX (0)
92
93 /* sinwave entries */
94 #define SIN_BITS 10
95 #define SIN_LEN (1<<SIN_BITS)
96 #define SIN_MASK (SIN_LEN-1)
97
98 #define TL_RES_LEN (256) /* 8 bits addressing (real chip) */
99
100
101
102 /* register number to channel number , slot offset */
103 #define SLOT1 0
104 #define SLOT2 1
105
106 /* Envelope Generator phases */
107
108 #define EG_ATT 4
109 #define EG_DEC 3
110 #define EG_SUS 2
111 #define EG_REL 1
112 #define EG_OFF 0
113
114
115 /* save output as raw 16-bit sample */
116
117 /*#define SAVE_SAMPLE*/
118
119 #ifdef SAVE_SAMPLE
120 static FILE *sample[1];
121 #if 1 /*save to MONO file */
122 #define SAVE_ALL_CHANNELS \
123 { signed int pom = a; \
124 fputc((unsigned short)pom&0xff,sample[0]); \
125 fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
126 }
127 #else /*save to STEREO file */
128 #define SAVE_ALL_CHANNELS \
129 { signed int pom = a; \
130 fputc((unsigned short)pom&0xff,sample[0]); \
131 fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
132 pom = b; \
133 fputc((unsigned short)pom&0xff,sample[0]); \
134 fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
135 }
136 #endif
137 #endif
138
139 //#define LOG_CYM_FILE 0
140 //static FILE * cymfile = NULL;
141
142
143
144
145
146 #define OPL3_TYPE_YMF262 (0) /* 36 operators, 8 waveforms */
147
148
149 typedef struct{
150 UINT32 ar; /* attack rate: AR<<2 */
151 UINT32 dr; /* decay rate: DR<<2 */
152 UINT32 rr; /* release rate:RR<<2 */
153 UINT8 KSR; /* key scale rate */
154 UINT8 ksl; /* keyscale level */
155 UINT8 ksr; /* key scale rate: kcode>>KSR */
156 UINT8 mul; /* multiple: mul_tab[ML] */
157
158 /* Phase Generator */
159 UINT32 Cnt; /* frequency counter */
160 UINT32 Incr; /* frequency counter step */
161 UINT8 FB; /* feedback shift value */
162 INT32 *connect; /* slot output pointer */
163 INT32 op1_out[2]; /* slot1 output for feedback */
164 UINT8 CON; /* connection (algorithm) type */
165
166 /* Envelope Generator */
167 UINT8 eg_type; /* percussive/non-percussive mode */
168 UINT8 state; /* phase type */
169 UINT32 TL; /* total level: TL << 2 */
170 INT32 TLL; /* adjusted now TL */
171 INT32 volume; /* envelope counter */
172 UINT32 sl; /* sustain level: sl_tab[SL] */
173
174 UINT32 eg_m_ar; /* (attack state) */
175 UINT8 eg_sh_ar; /* (attack state) */
176 UINT8 eg_sel_ar; /* (attack state) */
177 UINT32 eg_m_dr; /* (decay state) */
178 UINT8 eg_sh_dr; /* (decay state) */
179 UINT8 eg_sel_dr; /* (decay state) */
180 UINT32 eg_m_rr; /* (release state) */
181 UINT8 eg_sh_rr; /* (release state) */
182 UINT8 eg_sel_rr; /* (release state) */
183
184 UINT32 key; /* 0 = KEY OFF, >0 = KEY ON */
185
186 /* LFO */
187 UINT32 AMmask; /* LFO Amplitude Modulation enable mask */
188 UINT8 vib; /* LFO Phase Modulation enable flag (active high)*/
189
190 /* waveform select */
191 UINT8 waveform_number;
192 unsigned int wavetable;
193
194 //unsigned char reserved[128-84];//speedup: pump up the struct size to power of 2
195 unsigned char reserved[128-100];//speedup: pump up the struct size to power of 2
196
197 } OPL3_SLOT;
198
199 typedef struct{
200 OPL3_SLOT SLOT[2];
201
202 UINT32 block_fnum; /* block+fnum */
203 UINT32 fc; /* Freq. Increment base */
204 UINT32 ksl_base; /* KeyScaleLevel Base step */
205 UINT8 kcode; /* key code (for key scaling) */
206
207 /*
208 there are 12 2-operator channels which can be combined in pairs
209 to form six 4-operator channel, they are:
210 0 and 3,
211 1 and 4,
212 2 and 5,
213 9 and 12,
214 10 and 13,
215 11 and 14
216 */
217 UINT8 extended; /* set to 1 if this channel forms up a 4op channel with another channel(only used by first of pair of channels, ie 0,1,2 and 9,10,11) */
218 UINT8 Muted;
219
220 unsigned char reserved[512-272];//speedup:pump up the struct size to power of 2
221
222 } OPL3_CH;
223
224 /* OPL3 state */
225 typedef struct {
226 OPL3_CH P_CH[18]; /* OPL3 chips have 18 channels */
227
228 UINT32 pan[18*4]; /* channels output masks (0xffffffff = enable); 4 masks per one channel */
229 UINT32 pan_ctrl_value[18]; /* output control values 1 per one channel (1 value contains 4 masks) */
230 UINT8 MuteSpc[5]; /* for the 5 Rhythm Channels */
231
232 signed int chanout[18]; /* 18 channels */
233 signed int phase_modulation; /* phase modulation input (SLOT 2) */
234 signed int phase_modulation2; /* phase modulation input (SLOT 3 in 4 operator channels) */
235
236 UINT32 eg_cnt; /* global envelope generator counter */
237 UINT32 eg_timer; /* global envelope generator counter works at frequency = chipclock/288 (288=8*36) */
238 UINT32 eg_timer_add; /* step of eg_timer */
239 UINT32 eg_timer_overflow; /* envelope generator timer overlfows every 1 sample (on real chip) */
240
241 UINT32 fn_tab[1024]; /* fnumber->increment counter */
242
243 /* LFO */
244 UINT32 LFO_AM;
245 INT32 LFO_PM;
246 UINT8 lfo_am_depth;
247 UINT8 lfo_pm_depth_range;
248 UINT32 lfo_am_cnt;
249 UINT32 lfo_am_inc;
250 UINT32 lfo_pm_cnt;
251 UINT32 lfo_pm_inc;
252
253 UINT32 noise_rng; /* 23 bit noise shift register */
254 UINT32 noise_p; /* current noise 'phase' */
255 UINT32 noise_f; /* current noise period */
256
257 UINT8 OPL3_mode; /* OPL3 extension enable flag */
258
259 UINT8 rhythm; /* Rhythm mode */
260
261 int T[2]; /* timer counters */
262 UINT8 st[2]; /* timer enable */
263
264 UINT32 address; /* address register */
265 UINT8 status; /* status flag */
266 UINT8 statusmask; /* status mask */
267
268 UINT8 nts; /* NTS (note select) */
269
270 /* external event callback handlers */
271 OPL3_TIMERHANDLER timer_handler;/* TIMER handler */
272 void *TimerParam; /* TIMER parameter */
273 OPL3_IRQHANDLER IRQHandler; /* IRQ handler */
274 void *IRQParam; /* IRQ parameter */
275 OPL3_UPDATEHANDLER UpdateHandler;/* stream update handler */
276 void *UpdateParam; /* stream update parameter */
277
278 UINT8 type; /* chip type */
279 int clock; /* master clock (Hz) */
280 int rate; /* sampling rate (Hz) */
281 double freqbase; /* frequency base */
282 //attotime TimerBase; /* Timer base time (==sampling time)*/
283 } OPL3;
284
285
286
287 /* mapping of register number (offset) to slot number used by the emulator */
288 static const int slot_array[32]=
289 {
290 0, 2, 4, 1, 3, 5,-1,-1,
291 6, 8,10, 7, 9,11,-1,-1,
292 12,14,16,13,15,17,-1,-1,
293 -1,-1,-1,-1,-1,-1,-1,-1
294 };
295
296 /* key scale level */
297 /* table is 3dB/octave , DV converts this into 6dB/octave */
298 /* 0.1875 is bit 0 weight of the envelope counter (volume) expressed in the 'decibel' scale */
299 #define DV (0.1875/2.0)
300 static const UINT32 ksl_tab[8*16]=
301 {
302 /* OCT 0 */
303 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
304 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
305 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
306 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
307 /* OCT 1 */
308 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
309 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
310 0.000/DV, 0.750/DV, 1.125/DV, 1.500/DV,
311 1.875/DV, 2.250/DV, 2.625/DV, 3.000/DV,
312 /* OCT 2 */
313 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
314 0.000/DV, 1.125/DV, 1.875/DV, 2.625/DV,
315 3.000/DV, 3.750/DV, 4.125/DV, 4.500/DV,
316 4.875/DV, 5.250/DV, 5.625/DV, 6.000/DV,
317 /* OCT 3 */
318 0.000/DV, 0.000/DV, 0.000/DV, 1.875/DV,
319 3.000/DV, 4.125/DV, 4.875/DV, 5.625/DV,
320 6.000/DV, 6.750/DV, 7.125/DV, 7.500/DV,
321 7.875/DV, 8.250/DV, 8.625/DV, 9.000/DV,
322 /* OCT 4 */
323 0.000/DV, 0.000/DV, 3.000/DV, 4.875/DV,
324 6.000/DV, 7.125/DV, 7.875/DV, 8.625/DV,
325 9.000/DV, 9.750/DV,10.125/DV,10.500/DV,
326 10.875/DV,11.250/DV,11.625/DV,12.000/DV,
327 /* OCT 5 */
328 0.000/DV, 3.000/DV, 6.000/DV, 7.875/DV,
329 9.000/DV,10.125/DV,10.875/DV,11.625/DV,
330 12.000/DV,12.750/DV,13.125/DV,13.500/DV,
331 13.875/DV,14.250/DV,14.625/DV,15.000/DV,
332 /* OCT 6 */
333 0.000/DV, 6.000/DV, 9.000/DV,10.875/DV,
334 12.000/DV,13.125/DV,13.875/DV,14.625/DV,
335 15.000/DV,15.750/DV,16.125/DV,16.500/DV,
336 16.875/DV,17.250/DV,17.625/DV,18.000/DV,
337 /* OCT 7 */
338 0.000/DV, 9.000/DV,12.000/DV,13.875/DV,
339 15.000/DV,16.125/DV,16.875/DV,17.625/DV,
340 18.000/DV,18.750/DV,19.125/DV,19.500/DV,
341 19.875/DV,20.250/DV,20.625/DV,21.000/DV
342 };
343 #undef DV
344
345 /* 0 / 3.0 / 1.5 / 6.0 dB/OCT */
346 static const UINT32 ksl_shift[4] = { 31, 1, 2, 0 };
347
348
349 /* sustain level table (3dB per step) */
350 /* 0 - 15: 0, 3, 6, 9,12,15,18,21,24,27,30,33,36,39,42,93 (dB)*/
351 #define SC(db) (UINT32) ( db * (2.0/ENV_STEP) )
352 static const UINT32 sl_tab[16]={
353 SC( 0),SC( 1),SC( 2),SC(3 ),SC(4 ),SC(5 ),SC(6 ),SC( 7),
354 SC( 8),SC( 9),SC(10),SC(11),SC(12),SC(13),SC(14),SC(31)
355 };
356 #undef SC
357
358
359 #define RATE_STEPS (8)
360 static const unsigned char eg_inc[15*RATE_STEPS]={
361
362 /*cycle:0 1 2 3 4 5 6 7*/
363
364 /* 0 */ 0,1, 0,1, 0,1, 0,1, /* rates 00..12 0 (increment by 0 or 1) */
365 /* 1 */ 0,1, 0,1, 1,1, 0,1, /* rates 00..12 1 */
366 /* 2 */ 0,1, 1,1, 0,1, 1,1, /* rates 00..12 2 */
367 /* 3 */ 0,1, 1,1, 1,1, 1,1, /* rates 00..12 3 */
368
369 /* 4 */ 1,1, 1,1, 1,1, 1,1, /* rate 13 0 (increment by 1) */
370 /* 5 */ 1,1, 1,2, 1,1, 1,2, /* rate 13 1 */
371 /* 6 */ 1,2, 1,2, 1,2, 1,2, /* rate 13 2 */
372 /* 7 */ 1,2, 2,2, 1,2, 2,2, /* rate 13 3 */
373
374 /* 8 */ 2,2, 2,2, 2,2, 2,2, /* rate 14 0 (increment by 2) */
375 /* 9 */ 2,2, 2,4, 2,2, 2,4, /* rate 14 1 */
376 /*10 */ 2,4, 2,4, 2,4, 2,4, /* rate 14 2 */
377 /*11 */ 2,4, 4,4, 2,4, 4,4, /* rate 14 3 */
378
379 /*12 */ 4,4, 4,4, 4,4, 4,4, /* rates 15 0, 15 1, 15 2, 15 3 for decay */
380 /*13 */ 8,8, 8,8, 8,8, 8,8, /* rates 15 0, 15 1, 15 2, 15 3 for attack (zero time) */
381 /*14 */ 0,0, 0,0, 0,0, 0,0, /* infinity rates for attack and decay(s) */
382 };
383
384
385 #define O(a) (a*RATE_STEPS)
386
387 /* note that there is no O(13) in this table - it's directly in the code */
388 static const unsigned char eg_rate_select[16+64+16]={ /* Envelope Generator rates (16 + 64 rates + 16 RKS) */
389 /* 16 infinite time rates */
390 O(14),O(14),O(14),O(14),O(14),O(14),O(14),O(14),
391 O(14),O(14),O(14),O(14),O(14),O(14),O(14),O(14),
392
393 /* rates 00-12 */
394 O( 0),O( 1),O( 2),O( 3),
395 O( 0),O( 1),O( 2),O( 3),
396 O( 0),O( 1),O( 2),O( 3),
397 O( 0),O( 1),O( 2),O( 3),
398 O( 0),O( 1),O( 2),O( 3),
399 O( 0),O( 1),O( 2),O( 3),
400 O( 0),O( 1),O( 2),O( 3),
401 O( 0),O( 1),O( 2),O( 3),
402 O( 0),O( 1),O( 2),O( 3),
403 O( 0),O( 1),O( 2),O( 3),
404 O( 0),O( 1),O( 2),O( 3),
405 O( 0),O( 1),O( 2),O( 3),
406 O( 0),O( 1),O( 2),O( 3),
407
408 /* rate 13 */
409 O( 4),O( 5),O( 6),O( 7),
410
411 /* rate 14 */
412 O( 8),O( 9),O(10),O(11),
413
414 /* rate 15 */
415 O(12),O(12),O(12),O(12),
416
417 /* 16 dummy rates (same as 15 3) */
418 O(12),O(12),O(12),O(12),O(12),O(12),O(12),O(12),
419 O(12),O(12),O(12),O(12),O(12),O(12),O(12),O(12),
420
421 };
422 #undef O
423
424 /*rate 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 */
425 /*shift 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 0, 0, 0 */
426 /*mask 4095, 2047, 1023, 511, 255, 127, 63, 31, 15, 7, 3, 1, 0, 0, 0, 0 */
427
428 #define O(a) (a*1)
429 static const unsigned char eg_rate_shift[16+64+16]={ /* Envelope Generator counter shifts (16 + 64 rates + 16 RKS) */
430 /* 16 infinite time rates */
431 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
432 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
433
434 /* rates 00-12 */
435 O(12),O(12),O(12),O(12),
436 O(11),O(11),O(11),O(11),
437 O(10),O(10),O(10),O(10),
438 O( 9),O( 9),O( 9),O( 9),
439 O( 8),O( 8),O( 8),O( 8),
440 O( 7),O( 7),O( 7),O( 7),
441 O( 6),O( 6),O( 6),O( 6),
442 O( 5),O( 5),O( 5),O( 5),
443 O( 4),O( 4),O( 4),O( 4),
444 O( 3),O( 3),O( 3),O( 3),
445 O( 2),O( 2),O( 2),O( 2),
446 O( 1),O( 1),O( 1),O( 1),
447 O( 0),O( 0),O( 0),O( 0),
448
449 /* rate 13 */
450 O( 0),O( 0),O( 0),O( 0),
451
452 /* rate 14 */
453 O( 0),O( 0),O( 0),O( 0),
454
455 /* rate 15 */
456 O( 0),O( 0),O( 0),O( 0),
457
458 /* 16 dummy rates (same as 15 3) */
459 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
460 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
461
462 };
463 #undef O
464
465
466 /* multiple table */
467 #define ML 2
468 static const UINT8 mul_tab[16]= {
469 /* 1/2, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,10,12,12,15,15 */
470 0.50*ML, 1.00*ML, 2.00*ML, 3.00*ML, 4.00*ML, 5.00*ML, 6.00*ML, 7.00*ML,
471 8.00*ML, 9.00*ML,10.00*ML,10.00*ML,12.00*ML,12.00*ML,15.00*ML,15.00*ML
472 };
473 #undef ML
474
475 /* TL_TAB_LEN is calculated as:
476
477 * (12+1)=13 - sinus amplitude bits (Y axis)
478 * additional 1: to compensate for calculations of negative part of waveform
479 * (if we don't add it then the greatest possible _negative_ value would be -2
480 * and we really need -1 for waveform #7)
481 * 2 - sinus sign bit (Y axis)
482 * TL_RES_LEN - sinus resolution (X axis)
483 */
484 #define TL_TAB_LEN (13*2*TL_RES_LEN)
485 static signed int tl_tab[TL_TAB_LEN];
486
487 #define ENV_QUIET (TL_TAB_LEN>>4)
488
489 /* sin waveform table in 'decibel' scale */
490 /* there are eight waveforms on OPL3 chips */
491 static unsigned int sin_tab[SIN_LEN * 8];
492
493
494 /* LFO Amplitude Modulation table (verified on real YM3812)
495 27 output levels (triangle waveform); 1 level takes one of: 192, 256 or 448 samples
496
497 Length: 210 elements.
498
499 Each of the elements has to be repeated
500 exactly 64 times (on 64 consecutive samples).
501 The whole table takes: 64 * 210 = 13440 samples.
502
503 When AM = 1 data is used directly
504 When AM = 0 data is divided by 4 before being used (losing precision is important)
505 */
506
507 #define LFO_AM_TAB_ELEMENTS 210
508
509 static const UINT8 lfo_am_table[LFO_AM_TAB_ELEMENTS] = {
510 0,0,0,0,0,0,0,
511 1,1,1,1,
512 2,2,2,2,
513 3,3,3,3,
514 4,4,4,4,
515 5,5,5,5,
516 6,6,6,6,
517 7,7,7,7,
518 8,8,8,8,
519 9,9,9,9,
520 10,10,10,10,
521 11,11,11,11,
522 12,12,12,12,
523 13,13,13,13,
524 14,14,14,14,
525 15,15,15,15,
526 16,16,16,16,
527 17,17,17,17,
528 18,18,18,18,
529 19,19,19,19,
530 20,20,20,20,
531 21,21,21,21,
532 22,22,22,22,
533 23,23,23,23,
534 24,24,24,24,
535 25,25,25,25,
536 26,26,26,
537 25,25,25,25,
538 24,24,24,24,
539 23,23,23,23,
540 22,22,22,22,
541 21,21,21,21,
542 20,20,20,20,
543 19,19,19,19,
544 18,18,18,18,
545 17,17,17,17,
546 16,16,16,16,
547 15,15,15,15,
548 14,14,14,14,
549 13,13,13,13,
550 12,12,12,12,
551 11,11,11,11,
552 10,10,10,10,
553 9,9,9,9,
554 8,8,8,8,
555 7,7,7,7,
556 6,6,6,6,
557 5,5,5,5,
558 4,4,4,4,
559 3,3,3,3,
560 2,2,2,2,
561 1,1,1,1
562 };
563
564 /* LFO Phase Modulation table (verified on real YM3812) */
565 static const INT8 lfo_pm_table[8*8*2] = {
566
567 /* FNUM2/FNUM = 00 0xxxxxxx (0x0000) */
568 0, 0, 0, 0, 0, 0, 0, 0, /*LFO PM depth = 0*/
569 0, 0, 0, 0, 0, 0, 0, 0, /*LFO PM depth = 1*/
570
571 /* FNUM2/FNUM = 00 1xxxxxxx (0x0080) */
572 0, 0, 0, 0, 0, 0, 0, 0, /*LFO PM depth = 0*/
573 1, 0, 0, 0,-1, 0, 0, 0, /*LFO PM depth = 1*/
574
575 /* FNUM2/FNUM = 01 0xxxxxxx (0x0100) */
576 1, 0, 0, 0,-1, 0, 0, 0, /*LFO PM depth = 0*/
577 2, 1, 0,-1,-2,-1, 0, 1, /*LFO PM depth = 1*/
578
579 /* FNUM2/FNUM = 01 1xxxxxxx (0x0180) */
580 1, 0, 0, 0,-1, 0, 0, 0, /*LFO PM depth = 0*/
581 3, 1, 0,-1,-3,-1, 0, 1, /*LFO PM depth = 1*/
582
583 /* FNUM2/FNUM = 10 0xxxxxxx (0x0200) */
584 2, 1, 0,-1,-2,-1, 0, 1, /*LFO PM depth = 0*/
585 4, 2, 0,-2,-4,-2, 0, 2, /*LFO PM depth = 1*/
586
587 /* FNUM2/FNUM = 10 1xxxxxxx (0x0280) */
588 2, 1, 0,-1,-2,-1, 0, 1, /*LFO PM depth = 0*/
589 5, 2, 0,-2,-5,-2, 0, 2, /*LFO PM depth = 1*/
590
591 /* FNUM2/FNUM = 11 0xxxxxxx (0x0300) */
592 3, 1, 0,-1,-3,-1, 0, 1, /*LFO PM depth = 0*/
593 6, 3, 0,-3,-6,-3, 0, 3, /*LFO PM depth = 1*/
594
595 /* FNUM2/FNUM = 11 1xxxxxxx (0x0380) */
596 3, 1, 0,-1,-3,-1, 0, 1, /*LFO PM depth = 0*/
597 7, 3, 0,-3,-7,-3, 0, 3 /*LFO PM depth = 1*/
598 };
599
600
601 /* lock level of common table */
602 static int num_lock = 0;
603
604 /* work table */
605 #define SLOT7_1 (&chip->P_CH[7].SLOT[SLOT1])
606 #define SLOT7_2 (&chip->P_CH[7].SLOT[SLOT2])
607 #define SLOT8_1 (&chip->P_CH[8].SLOT[SLOT1])
608 #define SLOT8_2 (&chip->P_CH[8].SLOT[SLOT2])
609
610
611
612 /*INLINE int limit( int val, int max, int min ) {
613 if ( val > max )
614 val = max;
615 else if ( val < min )
616 val = min;
617
618 return val;
619 }*/
620
621
622 /* status set and IRQ handling */
OPL3_STATUS_SET(OPL3 * chip,int flag)623 INLINE void OPL3_STATUS_SET(OPL3 *chip,int flag)
624 {
625 /* set status flag masking out disabled IRQs */
626 chip->status |= (flag & chip->statusmask);
627 if(!(chip->status & 0x80))
628 {
629 if(chip->status & 0x7f)
630 { /* IRQ on */
631 chip->status |= 0x80;
632 /* callback user interrupt handler (IRQ is OFF to ON) */
633 if(chip->IRQHandler) (chip->IRQHandler)(chip->IRQParam,1);
634 }
635 }
636 }
637
638 /* status reset and IRQ handling */
OPL3_STATUS_RESET(OPL3 * chip,int flag)639 INLINE void OPL3_STATUS_RESET(OPL3 *chip,int flag)
640 {
641 /* reset status flag */
642 chip->status &= ~flag;
643 if(chip->status & 0x80)
644 {
645 if (!(chip->status & 0x7f))
646 {
647 chip->status &= 0x7f;
648 /* callback user interrupt handler (IRQ is ON to OFF) */
649 if(chip->IRQHandler) (chip->IRQHandler)(chip->IRQParam,0);
650 }
651 }
652 }
653
654 /* IRQ mask set */
OPL3_STATUSMASK_SET(OPL3 * chip,int flag)655 INLINE void OPL3_STATUSMASK_SET(OPL3 *chip,int flag)
656 {
657 chip->statusmask = flag;
658 /* IRQ handling check */
659 OPL3_STATUS_SET(chip,0);
660 OPL3_STATUS_RESET(chip,0);
661 }
662
663
664 /* advance LFO to next sample */
advance_lfo(OPL3 * chip)665 INLINE void advance_lfo(OPL3 *chip)
666 {
667 UINT8 tmp;
668
669 /* LFO */
670 chip->lfo_am_cnt += chip->lfo_am_inc;
671 if (chip->lfo_am_cnt >= ((UINT32)LFO_AM_TAB_ELEMENTS<<LFO_SH) ) /* lfo_am_table is 210 elements long */
672 chip->lfo_am_cnt -= ((UINT32)LFO_AM_TAB_ELEMENTS<<LFO_SH);
673
674 tmp = lfo_am_table[ chip->lfo_am_cnt >> LFO_SH ];
675
676 if (chip->lfo_am_depth)
677 chip->LFO_AM = tmp;
678 else
679 chip->LFO_AM = tmp>>2;
680
681 chip->lfo_pm_cnt += chip->lfo_pm_inc;
682 chip->LFO_PM = ((chip->lfo_pm_cnt>>LFO_SH) & 7) | chip->lfo_pm_depth_range;
683 }
684
685 /* advance to next sample */
advance(OPL3 * chip)686 INLINE void advance(OPL3 *chip)
687 {
688 OPL3_CH *CH;
689 OPL3_SLOT *op;
690 int i;
691
692 chip->eg_timer += chip->eg_timer_add;
693
694 while (chip->eg_timer >= chip->eg_timer_overflow)
695 {
696 chip->eg_timer -= chip->eg_timer_overflow;
697
698 chip->eg_cnt++;
699
700 for (i=0; i<9*2*2; i++)
701 {
702 CH = &chip->P_CH[i/2];
703 op = &CH->SLOT[i&1];
704 #if 1
705 /* Envelope Generator */
706 switch(op->state)
707 {
708 case EG_ATT: /* attack phase */
709 // if ( !(chip->eg_cnt & ((1<<op->eg_sh_ar)-1) ) )
710 if ( !(chip->eg_cnt & op->eg_m_ar) )
711 {
712 op->volume += (~op->volume *
713 (eg_inc[op->eg_sel_ar + ((chip->eg_cnt>>op->eg_sh_ar)&7)])
714 ) >>3;
715
716 if (op->volume <= MIN_ATT_INDEX)
717 {
718 op->volume = MIN_ATT_INDEX;
719 op->state = EG_DEC;
720 }
721
722 }
723 break;
724
725 case EG_DEC: /* decay phase */
726 // if ( !(chip->eg_cnt & ((1<<op->eg_sh_dr)-1) ) )
727 if ( !(chip->eg_cnt & op->eg_m_dr) )
728 {
729 op->volume += eg_inc[op->eg_sel_dr + ((chip->eg_cnt>>op->eg_sh_dr)&7)];
730
731 if ( op->volume >= op->sl )
732 op->state = EG_SUS;
733
734 }
735 break;
736
737 case EG_SUS: /* sustain phase */
738
739 /* this is important behaviour:
740 one can change percusive/non-percussive modes on the fly and
741 the chip will remain in sustain phase - verified on real YM3812 */
742
743 if(op->eg_type) /* non-percussive mode */
744 {
745 /* do nothing */
746 }
747 else /* percussive mode */
748 {
749 /* during sustain phase chip adds Release Rate (in percussive mode) */
750 // if ( !(chip->eg_cnt & ((1<<op->eg_sh_rr)-1) ) )
751 if ( !(chip->eg_cnt & op->eg_m_rr) )
752 {
753 op->volume += eg_inc[op->eg_sel_rr + ((chip->eg_cnt>>op->eg_sh_rr)&7)];
754
755 if ( op->volume >= MAX_ATT_INDEX )
756 op->volume = MAX_ATT_INDEX;
757 }
758 /* else do nothing in sustain phase */
759 }
760 break;
761
762 case EG_REL: /* release phase */
763 // if ( !(chip->eg_cnt & ((1<<op->eg_sh_rr)-1) ) )
764 if ( !(chip->eg_cnt & op->eg_m_rr) )
765 {
766 op->volume += eg_inc[op->eg_sel_rr + ((chip->eg_cnt>>op->eg_sh_rr)&7)];
767
768 if ( op->volume >= MAX_ATT_INDEX )
769 {
770 op->volume = MAX_ATT_INDEX;
771 op->state = EG_OFF;
772 }
773
774 }
775 break;
776
777 default:
778 break;
779 }
780 #endif
781 }
782 }
783
784 for (i=0; i<9*2*2; i++)
785 {
786 CH = &chip->P_CH[i/2];
787 op = &CH->SLOT[i&1];
788
789 /* Phase Generator */
790 if(op->vib)
791 {
792 UINT8 block;
793 unsigned int block_fnum = CH->block_fnum;
794
795 unsigned int fnum_lfo = (block_fnum&0x0380) >> 7;
796
797 signed int lfo_fn_table_index_offset = lfo_pm_table[chip->LFO_PM + 16*fnum_lfo ];
798
799 if (lfo_fn_table_index_offset) /* LFO phase modulation active */
800 {
801 block_fnum += lfo_fn_table_index_offset;
802 block = (block_fnum&0x1c00) >> 10;
803 op->Cnt += (chip->fn_tab[block_fnum&0x03ff] >> (7-block)) * op->mul;
804 }
805 else /* LFO phase modulation = zero */
806 {
807 op->Cnt += op->Incr;
808 }
809 }
810 else /* LFO phase modulation disabled for this operator */
811 {
812 op->Cnt += op->Incr;
813 }
814 }
815
816 /* The Noise Generator of the YM3812 is 23-bit shift register.
817 * Period is equal to 2^23-2 samples.
818 * Register works at sampling frequency of the chip, so output
819 * can change on every sample.
820 *
821 * Output of the register and input to the bit 22 is:
822 * bit0 XOR bit14 XOR bit15 XOR bit22
823 *
824 * Simply use bit 22 as the noise output.
825 */
826
827 chip->noise_p += chip->noise_f;
828 i = chip->noise_p >> FREQ_SH; /* number of events (shifts of the shift register) */
829 chip->noise_p &= FREQ_MASK;
830 while (i)
831 {
832 /*
833 UINT32 j;
834 j = ( (chip->noise_rng) ^ (chip->noise_rng>>14) ^ (chip->noise_rng>>15) ^ (chip->noise_rng>>22) ) & 1;
835 chip->noise_rng = (j<<22) | (chip->noise_rng>>1);
836 */
837
838 /*
839 Instead of doing all the logic operations above, we
840 use a trick here (and use bit 0 as the noise output).
841 The difference is only that the noise bit changes one
842 step ahead. This doesn't matter since we don't know
843 what is real state of the noise_rng after the reset.
844 */
845
846 if (chip->noise_rng & 1) chip->noise_rng ^= 0x800302;
847 chip->noise_rng >>= 1;
848
849 i--;
850 }
851 }
852
853
op_calc(UINT32 phase,unsigned int env,signed int pm,unsigned int wave_tab)854 INLINE signed int op_calc(UINT32 phase, unsigned int env, signed int pm, unsigned int wave_tab)
855 {
856 UINT32 p;
857
858 p = (env<<4) + sin_tab[wave_tab + ((((signed int)((phase & ~FREQ_MASK) + (pm<<16))) >> FREQ_SH ) & SIN_MASK) ];
859
860 if (p >= TL_TAB_LEN)
861 return 0;
862 return tl_tab[p];
863 }
864
op_calc1(UINT32 phase,unsigned int env,signed int pm,unsigned int wave_tab)865 INLINE signed int op_calc1(UINT32 phase, unsigned int env, signed int pm, unsigned int wave_tab)
866 {
867 UINT32 p;
868
869 p = (env<<4) + sin_tab[wave_tab + ((((signed int)((phase & ~FREQ_MASK) + pm))>>FREQ_SH) & SIN_MASK)];
870
871 if (p >= TL_TAB_LEN)
872 return 0;
873 return tl_tab[p];
874 }
875
876
877 #define volume_calc(OP) ((OP)->TLL + ((UINT32)(OP)->volume) + (chip->LFO_AM & (OP)->AMmask))
878
879 /* calculate output of a standard 2 operator channel
880 (or 1st part of a 4-op channel) */
chan_calc(OPL3 * chip,OPL3_CH * CH)881 INLINE void chan_calc( OPL3 *chip, OPL3_CH *CH )
882 {
883 OPL3_SLOT *SLOT;
884 unsigned int env;
885 signed int out;
886
887 if (CH->Muted)
888 return;
889
890 chip->phase_modulation = 0;
891 chip->phase_modulation2= 0;
892
893 /* SLOT 1 */
894 SLOT = &CH->SLOT[SLOT1];
895 env = volume_calc(SLOT);
896 out = SLOT->op1_out[0] + SLOT->op1_out[1];
897 SLOT->op1_out[0] = SLOT->op1_out[1];
898 SLOT->op1_out[1] = 0;
899 if( env < ENV_QUIET )
900 {
901 if (!SLOT->FB)
902 out = 0;
903 SLOT->op1_out[1] = op_calc1(SLOT->Cnt, env, (out<<SLOT->FB), SLOT->wavetable );
904 }
905 *SLOT->connect += SLOT->op1_out[1];
906 //logerror("out0=%5i vol0=%4i ", SLOT->op1_out[1], env );
907
908 /* SLOT 2 */
909 SLOT++;
910 env = volume_calc(SLOT);
911 if( env < ENV_QUIET )
912 *SLOT->connect += op_calc(SLOT->Cnt, env, chip->phase_modulation, SLOT->wavetable);
913
914 //logerror("out1=%5i vol1=%4i\n", op_calc(SLOT->Cnt, env, chip->phase_modulation, SLOT->wavetable), env );
915
916 }
917
918 /* calculate output of a 2nd part of 4-op channel */
chan_calc_ext(OPL3 * chip,OPL3_CH * CH)919 INLINE void chan_calc_ext( OPL3 *chip, OPL3_CH *CH )
920 {
921 OPL3_SLOT *SLOT;
922 unsigned int env;
923
924 if (CH->Muted)
925 return;
926
927 chip->phase_modulation = 0;
928
929 /* SLOT 1 */
930 SLOT = &CH->SLOT[SLOT1];
931 env = volume_calc(SLOT);
932 if( env < ENV_QUIET )
933 *SLOT->connect += op_calc(SLOT->Cnt, env, chip->phase_modulation2, SLOT->wavetable );
934
935 /* SLOT 2 */
936 SLOT++;
937 env = volume_calc(SLOT);
938 if( env < ENV_QUIET )
939 *SLOT->connect += op_calc(SLOT->Cnt, env, chip->phase_modulation, SLOT->wavetable);
940
941 }
942
943 /*
944 operators used in the rhythm sounds generation process:
945
946 Envelope Generator:
947
948 channel operator register number Bass High Snare Tom Top
949 / slot number TL ARDR SLRR Wave Drum Hat Drum Tom Cymbal
950 6 / 0 12 50 70 90 f0 +
951 6 / 1 15 53 73 93 f3 +
952 7 / 0 13 51 71 91 f1 +
953 7 / 1 16 54 74 94 f4 +
954 8 / 0 14 52 72 92 f2 +
955 8 / 1 17 55 75 95 f5 +
956
957 Phase Generator:
958
959 channel operator register number Bass High Snare Tom Top
960 / slot number MULTIPLE Drum Hat Drum Tom Cymbal
961 6 / 0 12 30 +
962 6 / 1 15 33 +
963 7 / 0 13 31 + + +
964 7 / 1 16 34 ----- n o t u s e d -----
965 8 / 0 14 32 +
966 8 / 1 17 35 + +
967
968 channel operator register number Bass High Snare Tom Top
969 number number BLK/FNUM2 FNUM Drum Hat Drum Tom Cymbal
970 6 12,15 B6 A6 +
971
972 7 13,16 B7 A7 + + +
973
974 8 14,17 B8 A8 + + +
975
976 */
977
978 /* calculate rhythm */
979
chan_calc_rhythm(OPL3 * chip,OPL3_CH * CH,unsigned int noise)980 INLINE void chan_calc_rhythm( OPL3 *chip, OPL3_CH *CH, unsigned int noise )
981 {
982 OPL3_SLOT *SLOT;
983 signed int *chanout = chip->chanout;
984 signed int out;
985 unsigned int env;
986
987
988 /* Bass Drum (verified on real YM3812):
989 - depends on the channel 6 'connect' register:
990 when connect = 0 it works the same as in normal (non-rhythm) mode (op1->op2->out)
991 when connect = 1 _only_ operator 2 is present on output (op2->out), operator 1 is ignored
992 - output sample always is multiplied by 2
993 */
994
995 chip->phase_modulation = 0;
996
997 /* SLOT 1 */
998 SLOT = &CH[6].SLOT[SLOT1];
999 env = volume_calc(SLOT);
1000
1001 out = SLOT->op1_out[0] + SLOT->op1_out[1];
1002 SLOT->op1_out[0] = SLOT->op1_out[1];
1003
1004 if (!SLOT->CON)
1005 chip->phase_modulation = SLOT->op1_out[0];
1006 //else ignore output of operator 1
1007
1008 SLOT->op1_out[1] = 0;
1009 if( env < ENV_QUIET )
1010 {
1011 if (!SLOT->FB)
1012 out = 0;
1013 SLOT->op1_out[1] = op_calc1(SLOT->Cnt, env, (out<<SLOT->FB), SLOT->wavetable );
1014 }
1015
1016 /* SLOT 2 */
1017 SLOT++;
1018 env = volume_calc(SLOT);
1019 if( env < ENV_QUIET && ! chip->MuteSpc[0] )
1020 chanout[6] += op_calc(SLOT->Cnt, env, chip->phase_modulation, SLOT->wavetable) * 2;
1021
1022
1023 /* Phase generation is based on: */
1024 // HH (13) channel 7->slot 1 combined with channel 8->slot 2 (same combination as TOP CYMBAL but different output phases)
1025 // SD (16) channel 7->slot 1
1026 // TOM (14) channel 8->slot 1
1027 // TOP (17) channel 7->slot 1 combined with channel 8->slot 2 (same combination as HIGH HAT but different output phases)
1028
1029 /* Envelope generation based on: */
1030 // HH channel 7->slot1
1031 // SD channel 7->slot2
1032 // TOM channel 8->slot1
1033 // TOP channel 8->slot2
1034
1035
1036 /* The following formulas can be well optimized.
1037 I leave them in direct form for now (in case I've missed something).
1038 */
1039
1040 /* High Hat (verified on real YM3812) */
1041 env = volume_calc(SLOT7_1);
1042 if( env < ENV_QUIET && ! chip->MuteSpc[4] )
1043 {
1044
1045 /* high hat phase generation:
1046 phase = d0 or 234 (based on frequency only)
1047 phase = 34 or 2d0 (based on noise)
1048 */
1049
1050 /* base frequency derived from operator 1 in channel 7 */
1051 unsigned char bit7 = ((SLOT7_1->Cnt>>FREQ_SH)>>7)&1;
1052 unsigned char bit3 = ((SLOT7_1->Cnt>>FREQ_SH)>>3)&1;
1053 unsigned char bit2 = ((SLOT7_1->Cnt>>FREQ_SH)>>2)&1;
1054
1055 unsigned char res1 = (bit2 ^ bit7) | bit3;
1056
1057 /* when res1 = 0 phase = 0x000 | 0xd0; */
1058 /* when res1 = 1 phase = 0x200 | (0xd0>>2); */
1059 UINT32 phase = res1 ? (0x200|(0xd0>>2)) : 0xd0;
1060
1061 /* enable gate based on frequency of operator 2 in channel 8 */
1062 unsigned char bit5e= ((SLOT8_2->Cnt>>FREQ_SH)>>5)&1;
1063 unsigned char bit3e= ((SLOT8_2->Cnt>>FREQ_SH)>>3)&1;
1064
1065 unsigned char res2 = (bit3e ^ bit5e);
1066
1067 /* when res2 = 0 pass the phase from calculation above (res1); */
1068 /* when res2 = 1 phase = 0x200 | (0xd0>>2); */
1069 if (res2)
1070 phase = (0x200|(0xd0>>2));
1071
1072
1073 /* when phase & 0x200 is set and noise=1 then phase = 0x200|0xd0 */
1074 /* when phase & 0x200 is set and noise=0 then phase = 0x200|(0xd0>>2), ie no change */
1075 if (phase&0x200)
1076 {
1077 if (noise)
1078 phase = 0x200|0xd0;
1079 }
1080 else
1081 /* when phase & 0x200 is clear and noise=1 then phase = 0xd0>>2 */
1082 /* when phase & 0x200 is clear and noise=0 then phase = 0xd0, ie no change */
1083 {
1084 if (noise)
1085 phase = 0xd0>>2;
1086 }
1087
1088 chanout[7] += op_calc(phase<<FREQ_SH, env, 0, SLOT7_1->wavetable) * 2;
1089 }
1090
1091 /* Snare Drum (verified on real YM3812) */
1092 env = volume_calc(SLOT7_2);
1093 if( env < ENV_QUIET && ! chip->MuteSpc[1] )
1094 {
1095 /* base frequency derived from operator 1 in channel 7 */
1096 unsigned char bit8 = ((SLOT7_1->Cnt>>FREQ_SH)>>8)&1;
1097
1098 /* when bit8 = 0 phase = 0x100; */
1099 /* when bit8 = 1 phase = 0x200; */
1100 UINT32 phase = bit8 ? 0x200 : 0x100;
1101
1102 /* Noise bit XOR'es phase by 0x100 */
1103 /* when noisebit = 0 pass the phase from calculation above */
1104 /* when noisebit = 1 phase ^= 0x100; */
1105 /* in other words: phase ^= (noisebit<<8); */
1106 if (noise)
1107 phase ^= 0x100;
1108
1109 chanout[7] += op_calc(phase<<FREQ_SH, env, 0, SLOT7_2->wavetable) * 2;
1110 }
1111
1112 /* Tom Tom (verified on real YM3812) */
1113 env = volume_calc(SLOT8_1);
1114 if( env < ENV_QUIET && ! chip->MuteSpc[2] )
1115 chanout[8] += op_calc(SLOT8_1->Cnt, env, 0, SLOT8_1->wavetable) * 2;
1116
1117 /* Top Cymbal (verified on real YM3812) */
1118 env = volume_calc(SLOT8_2);
1119 if( env < ENV_QUIET && ! chip->MuteSpc[3] )
1120 {
1121 /* base frequency derived from operator 1 in channel 7 */
1122 unsigned char bit7 = ((SLOT7_1->Cnt>>FREQ_SH)>>7)&1;
1123 unsigned char bit3 = ((SLOT7_1->Cnt>>FREQ_SH)>>3)&1;
1124 unsigned char bit2 = ((SLOT7_1->Cnt>>FREQ_SH)>>2)&1;
1125
1126 unsigned char res1 = (bit2 ^ bit7) | bit3;
1127
1128 /* when res1 = 0 phase = 0x000 | 0x100; */
1129 /* when res1 = 1 phase = 0x200 | 0x100; */
1130 UINT32 phase = res1 ? 0x300 : 0x100;
1131
1132 /* enable gate based on frequency of operator 2 in channel 8 */
1133 unsigned char bit5e= ((SLOT8_2->Cnt>>FREQ_SH)>>5)&1;
1134 unsigned char bit3e= ((SLOT8_2->Cnt>>FREQ_SH)>>3)&1;
1135
1136 unsigned char res2 = (bit3e ^ bit5e);
1137 /* when res2 = 0 pass the phase from calculation above (res1); */
1138 /* when res2 = 1 phase = 0x200 | 0x100; */
1139 if (res2)
1140 phase = 0x300;
1141
1142 chanout[8] += op_calc(phase<<FREQ_SH, env, 0, SLOT8_2->wavetable) * 2;
1143 }
1144
1145 }
1146
1147
1148 /* generic table initialize */
init_tables(void)1149 static int init_tables(void)
1150 {
1151 signed int i,x;
1152 signed int n;
1153 double o,m;
1154
1155
1156 for (x=0; x<TL_RES_LEN; x++)
1157 {
1158 m = (1<<16) / pow(2, (x+1) * (ENV_STEP/4.0) / 8.0);
1159 m = floor(m);
1160
1161 /* we never reach (1<<16) here due to the (x+1) */
1162 /* result fits within 16 bits at maximum */
1163
1164 n = (int)m; /* 16 bits here */
1165 n >>= 4; /* 12 bits here */
1166 if (n&1) /* round to nearest */
1167 n = (n>>1)+1;
1168 else
1169 n = n>>1;
1170 /* 11 bits here (rounded) */
1171 n <<= 1; /* 12 bits here (as in real chip) */
1172 tl_tab[ x*2 + 0 ] = n;
1173 tl_tab[ x*2 + 1 ] = ~tl_tab[ x*2 + 0 ]; /* this *is* different from OPL2 (verified on real YMF262) */
1174
1175 for (i=1; i<13; i++)
1176 {
1177 tl_tab[ x*2+0 + i*2*TL_RES_LEN ] = tl_tab[ x*2+0 ]>>i;
1178 tl_tab[ x*2+1 + i*2*TL_RES_LEN ] = ~tl_tab[ x*2+0 + i*2*TL_RES_LEN ]; /* this *is* different from OPL2 (verified on real YMF262) */
1179 }
1180 #if 0
1181 logerror("tl %04i", x*2);
1182 for (i=0; i<13; i++)
1183 logerror(", [%02i] %5i", i*2, tl_tab[ x*2 +0 + i*2*TL_RES_LEN ] ); /* positive */
1184 logerror("\n");
1185
1186 logerror("tl %04i", x*2);
1187 for (i=0; i<13; i++)
1188 logerror(", [%02i] %5i", i*2, tl_tab[ x*2 +1 + i*2*TL_RES_LEN ] ); /* negative */
1189 logerror("\n");
1190 #endif
1191 }
1192
1193 for (i=0; i<SIN_LEN; i++)
1194 {
1195 /* non-standard sinus */
1196 m = sin( ((i*2)+1) * M_PI / SIN_LEN ); /* checked against the real chip */
1197
1198 /* we never reach zero here due to ((i*2)+1) */
1199
1200 if (m>0.0)
1201 o = 8*log(1.0/m)/log(2.0); /* convert to 'decibels' */
1202 else
1203 o = 8*log(-1.0/m)/log(2.0); /* convert to 'decibels' */
1204
1205 o = o / (ENV_STEP/4);
1206
1207 n = (int)(2.0*o);
1208 if (n&1) /* round to nearest */
1209 n = (n>>1)+1;
1210 else
1211 n = n>>1;
1212
1213 sin_tab[ i ] = n*2 + (m>=0.0? 0: 1 );
1214
1215 /*logerror("YMF262.C: sin [%4i (hex=%03x)]= %4i (tl_tab value=%5i)\n", i, i, sin_tab[i], tl_tab[sin_tab[i]] );*/
1216 }
1217
1218 for (i=0; i<SIN_LEN; i++)
1219 {
1220 /* these 'pictures' represent _two_ cycles */
1221 /* waveform 1: __ __ */
1222 /* / \____/ \____*/
1223 /* output only first half of the sinus waveform (positive one) */
1224
1225 if (i & (1<<(SIN_BITS-1)) )
1226 sin_tab[1*SIN_LEN+i] = TL_TAB_LEN;
1227 else
1228 sin_tab[1*SIN_LEN+i] = sin_tab[i];
1229
1230 /* waveform 2: __ __ __ __ */
1231 /* / \/ \/ \/ \*/
1232 /* abs(sin) */
1233
1234 sin_tab[2*SIN_LEN+i] = sin_tab[i & (SIN_MASK>>1) ];
1235
1236 /* waveform 3: _ _ _ _ */
1237 /* / |_/ |_/ |_/ |_*/
1238 /* abs(output only first quarter of the sinus waveform) */
1239
1240 if (i & (1<<(SIN_BITS-2)) )
1241 sin_tab[3*SIN_LEN+i] = TL_TAB_LEN;
1242 else
1243 sin_tab[3*SIN_LEN+i] = sin_tab[i & (SIN_MASK>>2)];
1244
1245 /* waveform 4: */
1246 /* /\ ____/\ ____*/
1247 /* \/ \/ */
1248 /* output whole sinus waveform in half the cycle(step=2) and output 0 on the other half of cycle */
1249
1250 if (i & (1<<(SIN_BITS-1)) )
1251 sin_tab[4*SIN_LEN+i] = TL_TAB_LEN;
1252 else
1253 sin_tab[4*SIN_LEN+i] = sin_tab[i*2];
1254
1255 /* waveform 5: */
1256 /* /\/\____/\/\____*/
1257 /* */
1258 /* output abs(whole sinus) waveform in half the cycle(step=2) and output 0 on the other half of cycle */
1259
1260 if (i & (1<<(SIN_BITS-1)) )
1261 sin_tab[5*SIN_LEN+i] = TL_TAB_LEN;
1262 else
1263 sin_tab[5*SIN_LEN+i] = sin_tab[(i*2) & (SIN_MASK>>1) ];
1264
1265 /* waveform 6: ____ ____ */
1266 /* */
1267 /* ____ ____*/
1268 /* output maximum in half the cycle and output minimum on the other half of cycle */
1269
1270 if (i & (1<<(SIN_BITS-1)) )
1271 sin_tab[6*SIN_LEN+i] = 1; /* negative */
1272 else
1273 sin_tab[6*SIN_LEN+i] = 0; /* positive */
1274
1275 /* waveform 7: */
1276 /* |\____ |\____ */
1277 /* \| \|*/
1278 /* output sawtooth waveform */
1279
1280 if (i & (1<<(SIN_BITS-1)) )
1281 x = ((SIN_LEN-1)-i)*16 + 1; /* negative: from 8177 to 1 */
1282 else
1283 x = i*16; /*positive: from 0 to 8176 */
1284
1285 if (x > TL_TAB_LEN)
1286 x = TL_TAB_LEN; /* clip to the allowed range */
1287
1288 sin_tab[7*SIN_LEN+i] = x;
1289
1290 //logerror("YMF262.C: sin1[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[1*SIN_LEN+i], tl_tab[sin_tab[1*SIN_LEN+i]] );
1291 //logerror("YMF262.C: sin2[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[2*SIN_LEN+i], tl_tab[sin_tab[2*SIN_LEN+i]] );
1292 //logerror("YMF262.C: sin3[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[3*SIN_LEN+i], tl_tab[sin_tab[3*SIN_LEN+i]] );
1293 //logerror("YMF262.C: sin4[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[4*SIN_LEN+i], tl_tab[sin_tab[4*SIN_LEN+i]] );
1294 //logerror("YMF262.C: sin5[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[5*SIN_LEN+i], tl_tab[sin_tab[5*SIN_LEN+i]] );
1295 //logerror("YMF262.C: sin6[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[6*SIN_LEN+i], tl_tab[sin_tab[6*SIN_LEN+i]] );
1296 //logerror("YMF262.C: sin7[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[7*SIN_LEN+i], tl_tab[sin_tab[7*SIN_LEN+i]] );
1297 }
1298 /*logerror("YMF262.C: ENV_QUIET= %08x (dec*8=%i)\n", ENV_QUIET, ENV_QUIET*8 );*/
1299
1300 #ifdef SAVE_SAMPLE
1301 sample[0]=fopen("sampsum.pcm","wb");
1302 #endif
1303
1304 return 1;
1305 }
1306
OPLCloseTable(void)1307 static void OPLCloseTable( void )
1308 {
1309 #ifdef SAVE_SAMPLE
1310 fclose(sample[0]);
1311 #endif
1312 }
1313
1314
1315
OPL3_initalize(OPL3 * chip)1316 static void OPL3_initalize(OPL3 *chip)
1317 {
1318 int i;
1319
1320 /* frequency base */
1321 chip->freqbase = (chip->rate) ? ((double)chip->clock / (8.0*36)) / chip->rate : 0;
1322 #if 0
1323 chip->rate = (double)chip->clock / (8.0*36);
1324 chip->freqbase = 1.0;
1325 #endif
1326
1327 /* logerror("YMF262: freqbase=%f\n", chip->freqbase); */
1328
1329 /* Timer base time */
1330 //chip->TimerBase = attotime_mul(ATTOTIME_IN_HZ(chip->clock), 8*36);
1331
1332 /* make fnumber -> increment counter table */
1333 for( i=0 ; i < 1024 ; i++ )
1334 {
1335 /* opn phase increment counter = 20bit */
1336 chip->fn_tab[i] = (UINT32)( (double)i * 64 * chip->freqbase * (1<<(FREQ_SH-10)) ); /* -10 because chip works with 10.10 fixed point, while we use 16.16 */
1337 #if 0
1338 logerror("YMF262.C: fn_tab[%4i] = %08x (dec=%8i)\n",
1339 i, chip->fn_tab[i]>>6, chip->fn_tab[i]>>6 );
1340 #endif
1341 }
1342
1343 #if 0
1344 for( i=0 ; i < 16 ; i++ )
1345 {
1346 logerror("YMF262.C: sl_tab[%i] = %08x\n",
1347 i, sl_tab[i] );
1348 }
1349 for( i=0 ; i < 8 ; i++ )
1350 {
1351 int j;
1352 logerror("YMF262.C: ksl_tab[oct=%2i] =",i);
1353 for (j=0; j<16; j++)
1354 {
1355 logerror("%08x ", ksl_tab[i*16+j] );
1356 }
1357 logerror("\n");
1358 }
1359 #endif
1360
1361
1362 /* Amplitude modulation: 27 output levels (triangle waveform); 1 level takes one of: 192, 256 or 448 samples */
1363 /* One entry from LFO_AM_TABLE lasts for 64 samples */
1364 chip->lfo_am_inc = (1.0 / 64.0 ) * (1<<LFO_SH) * chip->freqbase;
1365
1366 /* Vibrato: 8 output levels (triangle waveform); 1 level takes 1024 samples */
1367 chip->lfo_pm_inc = (1.0 / 1024.0) * (1<<LFO_SH) * chip->freqbase;
1368
1369 /*logerror ("chip->lfo_am_inc = %8x ; chip->lfo_pm_inc = %8x\n", chip->lfo_am_inc, chip->lfo_pm_inc);*/
1370
1371 /* Noise generator: a step takes 1 sample */
1372 chip->noise_f = (1.0 / 1.0) * (1<<FREQ_SH) * chip->freqbase;
1373
1374 chip->eg_timer_add = (1<<EG_SH) * chip->freqbase;
1375 chip->eg_timer_overflow = ( 1 ) * (1<<EG_SH);
1376 /*logerror("YMF262init eg_timer_add=%8x eg_timer_overflow=%8x\n", chip->eg_timer_add, chip->eg_timer_overflow);*/
1377
1378 }
1379
FM_KEYON(OPL3_SLOT * SLOT,UINT32 key_set)1380 INLINE void FM_KEYON(OPL3_SLOT *SLOT, UINT32 key_set)
1381 {
1382 if( !SLOT->key )
1383 {
1384 /* restart Phase Generator */
1385 SLOT->Cnt = 0;
1386 /* phase -> Attack */
1387 SLOT->state = EG_ATT;
1388 }
1389 SLOT->key |= key_set;
1390 }
1391
FM_KEYOFF(OPL3_SLOT * SLOT,UINT32 key_clr)1392 INLINE void FM_KEYOFF(OPL3_SLOT *SLOT, UINT32 key_clr)
1393 {
1394 if( SLOT->key )
1395 {
1396 SLOT->key &= key_clr;
1397
1398 if( !SLOT->key )
1399 {
1400 /* phase -> Release */
1401 if (SLOT->state>EG_REL)
1402 SLOT->state = EG_REL;
1403 }
1404 }
1405 }
1406
1407 /* update phase increment counter of operator (also update the EG rates if necessary) */
CALC_FCSLOT(OPL3_CH * CH,OPL3_SLOT * SLOT)1408 INLINE void CALC_FCSLOT(OPL3_CH *CH,OPL3_SLOT *SLOT)
1409 {
1410 int ksr;
1411
1412 /* (frequency) phase increment counter */
1413 SLOT->Incr = CH->fc * SLOT->mul;
1414 ksr = CH->kcode >> SLOT->KSR;
1415
1416 if( SLOT->ksr != ksr )
1417 {
1418 SLOT->ksr = ksr;
1419
1420 /* calculate envelope generator rates */
1421 if ((SLOT->ar + SLOT->ksr) < 16+60)
1422 {
1423 SLOT->eg_sh_ar = eg_rate_shift [SLOT->ar + SLOT->ksr ];
1424 SLOT->eg_m_ar = (1<<SLOT->eg_sh_ar)-1;
1425 SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr ];
1426 }
1427 else
1428 {
1429 SLOT->eg_sh_ar = 0;
1430 SLOT->eg_m_ar = (1<<SLOT->eg_sh_ar)-1;
1431 SLOT->eg_sel_ar = 13*RATE_STEPS;
1432 }
1433 SLOT->eg_sh_dr = eg_rate_shift [SLOT->dr + SLOT->ksr ];
1434 SLOT->eg_m_dr = (1<<SLOT->eg_sh_dr)-1;
1435 SLOT->eg_sel_dr = eg_rate_select[SLOT->dr + SLOT->ksr ];
1436 SLOT->eg_sh_rr = eg_rate_shift [SLOT->rr + SLOT->ksr ];
1437 SLOT->eg_m_rr = (1<<SLOT->eg_sh_rr)-1;
1438 SLOT->eg_sel_rr = eg_rate_select[SLOT->rr + SLOT->ksr ];
1439 }
1440 }
1441
1442 /* set multi,am,vib,EG-TYP,KSR,mul */
set_mul(OPL3 * chip,int slot,int v)1443 INLINE void set_mul(OPL3 *chip,int slot,int v)
1444 {
1445 OPL3_CH *CH = &chip->P_CH[slot/2];
1446 OPL3_SLOT *SLOT = &CH->SLOT[slot&1];
1447
1448 SLOT->mul = mul_tab[v&0x0f];
1449 SLOT->KSR = (v&0x10) ? 0 : 2;
1450 SLOT->eg_type = (v&0x20);
1451 SLOT->vib = (v&0x40);
1452 SLOT->AMmask = (v&0x80) ? ~0 : 0;
1453
1454 if (chip->OPL3_mode & 1)
1455 {
1456 int chan_no = slot/2;
1457
1458 /* in OPL3 mode */
1459 //DO THIS:
1460 //if this is one of the slots of 1st channel forming up a 4-op channel
1461 //do normal operation
1462 //else normal 2 operator function
1463 //OR THIS:
1464 //if this is one of the slots of 2nd channel forming up a 4-op channel
1465 //update it using channel data of 1st channel of a pair
1466 //else normal 2 operator function
1467 switch(chan_no)
1468 {
1469 case 0: case 1: case 2:
1470 case 9: case 10: case 11:
1471 if (CH->extended)
1472 {
1473 /* normal */
1474 CALC_FCSLOT(CH,SLOT);
1475 }
1476 else
1477 {
1478 /* normal */
1479 CALC_FCSLOT(CH,SLOT);
1480 }
1481 break;
1482 case 3: case 4: case 5:
1483 case 12: case 13: case 14:
1484 if ((CH-3)->extended)
1485 {
1486 /* update this SLOT using frequency data for 1st channel of a pair */
1487 CALC_FCSLOT(CH-3,SLOT);
1488 }
1489 else
1490 {
1491 /* normal */
1492 CALC_FCSLOT(CH,SLOT);
1493 }
1494 break;
1495 default:
1496 /* normal */
1497 CALC_FCSLOT(CH,SLOT);
1498 break;
1499 }
1500 }
1501 else
1502 {
1503 /* in OPL2 mode */
1504 CALC_FCSLOT(CH,SLOT);
1505 }
1506 }
1507
1508 /* set ksl & tl */
set_ksl_tl(OPL3 * chip,int slot,int v)1509 INLINE void set_ksl_tl(OPL3 *chip,int slot,int v)
1510 {
1511 OPL3_CH *CH = &chip->P_CH[slot/2];
1512 OPL3_SLOT *SLOT = &CH->SLOT[slot&1];
1513
1514 SLOT->ksl = ksl_shift[v >> 6];
1515 SLOT->TL = (v&0x3f)<<(ENV_BITS-1-7); /* 7 bits TL (bit 6 = always 0) */
1516
1517 if (chip->OPL3_mode & 1)
1518 {
1519 int chan_no = slot/2;
1520
1521 /* in OPL3 mode */
1522 //DO THIS:
1523 //if this is one of the slots of 1st channel forming up a 4-op channel
1524 //do normal operation
1525 //else normal 2 operator function
1526 //OR THIS:
1527 //if this is one of the slots of 2nd channel forming up a 4-op channel
1528 //update it using channel data of 1st channel of a pair
1529 //else normal 2 operator function
1530 switch(chan_no)
1531 {
1532 case 0: case 1: case 2:
1533 case 9: case 10: case 11:
1534 if (CH->extended)
1535 {
1536 /* normal */
1537 SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl);
1538 }
1539 else
1540 {
1541 /* normal */
1542 SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl);
1543 }
1544 break;
1545 case 3: case 4: case 5:
1546 case 12: case 13: case 14:
1547 if ((CH-3)->extended)
1548 {
1549 /* update this SLOT using frequency data for 1st channel of a pair */
1550 SLOT->TLL = SLOT->TL + ((CH-3)->ksl_base>>SLOT->ksl);
1551 }
1552 else
1553 {
1554 /* normal */
1555 SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl);
1556 }
1557 break;
1558 default:
1559 /* normal */
1560 SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl);
1561 break;
1562 }
1563 }
1564 else
1565 {
1566 /* in OPL2 mode */
1567 SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl);
1568 }
1569
1570 }
1571
1572 /* set attack rate & decay rate */
set_ar_dr(OPL3 * chip,int slot,int v)1573 INLINE void set_ar_dr(OPL3 *chip,int slot,int v)
1574 {
1575 OPL3_CH *CH = &chip->P_CH[slot/2];
1576 OPL3_SLOT *SLOT = &CH->SLOT[slot&1];
1577
1578 SLOT->ar = (v>>4) ? 16 + ((v>>4) <<2) : 0;
1579
1580 if ((SLOT->ar + SLOT->ksr) < 16+60) /* verified on real YMF262 - all 15 x rates take "zero" time */
1581 {
1582 SLOT->eg_sh_ar = eg_rate_shift [SLOT->ar + SLOT->ksr ];
1583 SLOT->eg_m_ar = (1<<SLOT->eg_sh_ar)-1;
1584 SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr ];
1585 }
1586 else
1587 {
1588 SLOT->eg_sh_ar = 0;
1589 SLOT->eg_m_ar = (1<<SLOT->eg_sh_ar)-1;
1590 SLOT->eg_sel_ar = 13*RATE_STEPS;
1591 }
1592
1593 SLOT->dr = (v&0x0f)? 16 + ((v&0x0f)<<2) : 0;
1594 SLOT->eg_sh_dr = eg_rate_shift [SLOT->dr + SLOT->ksr ];
1595 SLOT->eg_m_dr = (1<<SLOT->eg_sh_dr)-1;
1596 SLOT->eg_sel_dr = eg_rate_select[SLOT->dr + SLOT->ksr ];
1597 }
1598
1599 /* set sustain level & release rate */
set_sl_rr(OPL3 * chip,int slot,int v)1600 INLINE void set_sl_rr(OPL3 *chip,int slot,int v)
1601 {
1602 OPL3_CH *CH = &chip->P_CH[slot/2];
1603 OPL3_SLOT *SLOT = &CH->SLOT[slot&1];
1604
1605 SLOT->sl = sl_tab[ v>>4 ];
1606
1607 SLOT->rr = (v&0x0f)? 16 + ((v&0x0f)<<2) : 0;
1608 SLOT->eg_sh_rr = eg_rate_shift [SLOT->rr + SLOT->ksr ];
1609 SLOT->eg_m_rr = (1<<SLOT->eg_sh_rr)-1;
1610 SLOT->eg_sel_rr = eg_rate_select[SLOT->rr + SLOT->ksr ];
1611 }
1612
1613
update_channels(OPL3 * chip,OPL3_CH * CH)1614 static void update_channels(OPL3 *chip, OPL3_CH *CH)
1615 {
1616 /* update channel passed as a parameter and a channel at CH+=3; */
1617 if (CH->extended)
1618 { /* we've just switched to combined 4 operator mode */
1619
1620 }
1621 else
1622 { /* we've just switched to normal 2 operator mode */
1623
1624 }
1625
1626 }
1627
1628 /* write a value v to register r on OPL chip */
OPL3WriteReg(OPL3 * chip,int r,int v)1629 static void OPL3WriteReg(OPL3 *chip, int r, int v)
1630 {
1631 OPL3_CH *CH;
1632 signed int *chanout = chip->chanout;
1633 unsigned int ch_offset = 0;
1634 int slot;
1635 int block_fnum;
1636
1637
1638
1639 /*if (LOG_CYM_FILE && (cymfile) && ((r&255)!=0) && (r!=255) )
1640 {
1641 if (r>0xff)
1642 fputc( (unsigned char)0xff, cymfile );//mark writes to second register set
1643
1644 fputc( (unsigned char)r&0xff, cymfile );
1645 fputc( (unsigned char)v, cymfile );
1646 }*/
1647
1648 if(r&0x100)
1649 {
1650 switch(r)
1651 {
1652 case 0x101: /* test register */
1653 return;
1654
1655 case 0x104: /* 6 channels enable */
1656 {
1657 UINT8 prev;
1658
1659 CH = &chip->P_CH[0]; /* channel 0 */
1660 prev = CH->extended;
1661 CH->extended = (v>>0) & 1;
1662 if(prev != CH->extended)
1663 update_channels(chip, CH);
1664 CH++; /* channel 1 */
1665 prev = CH->extended;
1666 CH->extended = (v>>1) & 1;
1667 if(prev != CH->extended)
1668 update_channels(chip, CH);
1669 CH++; /* channel 2 */
1670 prev = CH->extended;
1671 CH->extended = (v>>2) & 1;
1672 if(prev != CH->extended)
1673 update_channels(chip, CH);
1674
1675
1676 CH = &chip->P_CH[9]; /* channel 9 */
1677 prev = CH->extended;
1678 CH->extended = (v>>3) & 1;
1679 if(prev != CH->extended)
1680 update_channels(chip, CH);
1681 CH++; /* channel 10 */
1682 prev = CH->extended;
1683 CH->extended = (v>>4) & 1;
1684 if(prev != CH->extended)
1685 update_channels(chip, CH);
1686 CH++; /* channel 11 */
1687 prev = CH->extended;
1688 CH->extended = (v>>5) & 1;
1689 if(prev != CH->extended)
1690 update_channels(chip, CH);
1691
1692 }
1693 return;
1694
1695 case 0x105: /* OPL3 extensions enable register */
1696
1697 chip->OPL3_mode = v&0x01; /* OPL3 mode when bit0=1 otherwise it is OPL2 mode */
1698
1699 /* following behaviour was tested on real YMF262,
1700 switching OPL3/OPL2 modes on the fly:
1701 - does not change the waveform previously selected (unless when ....)
1702 - does not update CH.A, CH.B, CH.C and CH.D output selectors (registers c0-c8) (unless when ....)
1703 - does not disable channels 9-17 on OPL3->OPL2 switch
1704 - does not switch 4 operator channels back to 2 operator channels
1705 */
1706
1707 return;
1708
1709 default:
1710 #ifdef _DEBUG
1711 if (r < 0x120)
1712 logerror("YMF262: write to unknown register (set#2): %03x value=%02x\n",r,v);
1713 #endif
1714 break;
1715 }
1716
1717 ch_offset = 9; /* register page #2 starts from channel 9 (counting from 0) */
1718 }
1719
1720 /* adjust bus to 8 bits */
1721 r &= 0xff;
1722 v &= 0xff;
1723
1724
1725 switch(r&0xe0)
1726 {
1727 case 0x00: /* 00-1f:control */
1728 switch(r&0x1f)
1729 {
1730 case 0x01: /* test register */
1731 break;
1732 case 0x02: /* Timer 1 */
1733 chip->T[0] = (256-v)*4;
1734 break;
1735 case 0x03: /* Timer 2 */
1736 chip->T[1] = (256-v)*16;
1737 break;
1738 case 0x04: /* IRQ clear / mask and Timer enable */
1739 if(v&0x80)
1740 { /* IRQ flags clear */
1741 OPL3_STATUS_RESET(chip,0x60);
1742 }
1743 else
1744 { /* set IRQ mask ,timer enable */
1745 UINT8 st1 = v & 1;
1746 UINT8 st2 = (v>>1) & 1;
1747
1748 /* IRQRST,T1MSK,t2MSK,x,x,x,ST2,ST1 */
1749 OPL3_STATUS_RESET(chip, v & 0x60);
1750 OPL3_STATUSMASK_SET(chip, (~v) & 0x60 );
1751
1752 /* timer 2 */
1753 if(chip->st[1] != st2)
1754 {
1755 //attotime period = st2 ? attotime_mul(chip->TimerBase, chip->T[1]) : attotime_zero;
1756 chip->st[1] = st2;
1757 //if (chip->timer_handler) (chip->timer_handler)(chip->TimerParam,1,period);
1758 }
1759 /* timer 1 */
1760 if(chip->st[0] != st1)
1761 {
1762 //attotime period = st1 ? attotime_mul(chip->TimerBase, chip->T[0]) : attotime_zero;
1763 chip->st[0] = st1;
1764 //if (chip->timer_handler) (chip->timer_handler)(chip->TimerParam,0,period);
1765 }
1766 }
1767 break;
1768 case 0x08: /* x,NTS,x,x, x,x,x,x */
1769 chip->nts = v;
1770 break;
1771
1772 default:
1773 #ifdef _DEBUG
1774 logerror("YMF262: write to unknown register: %02x value=%02x\n",r,v);
1775 #endif
1776 break;
1777 }
1778 break;
1779 case 0x20: /* am ON, vib ON, ksr, eg_type, mul */
1780 slot = slot_array[r&0x1f];
1781 if(slot < 0) return;
1782 set_mul(chip, slot + ch_offset*2, v);
1783 break;
1784 case 0x40:
1785 slot = slot_array[r&0x1f];
1786 if(slot < 0) return;
1787 set_ksl_tl(chip, slot + ch_offset*2, v);
1788 break;
1789 case 0x60:
1790 slot = slot_array[r&0x1f];
1791 if(slot < 0) return;
1792 set_ar_dr(chip, slot + ch_offset*2, v);
1793 break;
1794 case 0x80:
1795 slot = slot_array[r&0x1f];
1796 if(slot < 0) return;
1797 set_sl_rr(chip, slot + ch_offset*2, v);
1798 break;
1799 case 0xa0:
1800 if (r == 0xbd) /* am depth, vibrato depth, r,bd,sd,tom,tc,hh */
1801 {
1802 if (ch_offset != 0) /* 0xbd register is present in set #1 only */
1803 return;
1804
1805 chip->lfo_am_depth = v & 0x80;
1806 chip->lfo_pm_depth_range = (v&0x40) ? 8 : 0;
1807
1808 chip->rhythm = v&0x3f;
1809
1810 if(chip->rhythm&0x20)
1811 {
1812 /* BD key on/off */
1813 if(v&0x10)
1814 {
1815 FM_KEYON (&chip->P_CH[6].SLOT[SLOT1], 2);
1816 FM_KEYON (&chip->P_CH[6].SLOT[SLOT2], 2);
1817 }
1818 else
1819 {
1820 FM_KEYOFF(&chip->P_CH[6].SLOT[SLOT1],~2);
1821 FM_KEYOFF(&chip->P_CH[6].SLOT[SLOT2],~2);
1822 }
1823 /* HH key on/off */
1824 if(v&0x01) FM_KEYON (&chip->P_CH[7].SLOT[SLOT1], 2);
1825 else FM_KEYOFF(&chip->P_CH[7].SLOT[SLOT1],~2);
1826 /* SD key on/off */
1827 if(v&0x08) FM_KEYON (&chip->P_CH[7].SLOT[SLOT2], 2);
1828 else FM_KEYOFF(&chip->P_CH[7].SLOT[SLOT2],~2);
1829 /* TOM key on/off */
1830 if(v&0x04) FM_KEYON (&chip->P_CH[8].SLOT[SLOT1], 2);
1831 else FM_KEYOFF(&chip->P_CH[8].SLOT[SLOT1],~2);
1832 /* TOP-CY key on/off */
1833 if(v&0x02) FM_KEYON (&chip->P_CH[8].SLOT[SLOT2], 2);
1834 else FM_KEYOFF(&chip->P_CH[8].SLOT[SLOT2],~2);
1835 }
1836 else
1837 {
1838 /* BD key off */
1839 FM_KEYOFF(&chip->P_CH[6].SLOT[SLOT1],~2);
1840 FM_KEYOFF(&chip->P_CH[6].SLOT[SLOT2],~2);
1841 /* HH key off */
1842 FM_KEYOFF(&chip->P_CH[7].SLOT[SLOT1],~2);
1843 /* SD key off */
1844 FM_KEYOFF(&chip->P_CH[7].SLOT[SLOT2],~2);
1845 /* TOM key off */
1846 FM_KEYOFF(&chip->P_CH[8].SLOT[SLOT1],~2);
1847 /* TOP-CY off */
1848 FM_KEYOFF(&chip->P_CH[8].SLOT[SLOT2],~2);
1849 }
1850 return;
1851 }
1852
1853 /* keyon,block,fnum */
1854 if( (r&0x0f) > 8) return;
1855 CH = &chip->P_CH[(r&0x0f) + ch_offset];
1856
1857 if(!(r&0x10))
1858 { /* a0-a8 */
1859 block_fnum = (CH->block_fnum&0x1f00) | v;
1860 }
1861 else
1862 { /* b0-b8 */
1863 block_fnum = ((v&0x1f)<<8) | (CH->block_fnum&0xff);
1864
1865 if (chip->OPL3_mode & 1)
1866 {
1867 int chan_no = (r&0x0f) + ch_offset;
1868
1869 /* in OPL3 mode */
1870 //DO THIS:
1871 //if this is 1st channel forming up a 4-op channel
1872 //ALSO keyon/off slots of 2nd channel forming up 4-op channel
1873 //else normal 2 operator function keyon/off
1874 //OR THIS:
1875 //if this is 2nd channel forming up 4-op channel just do nothing
1876 //else normal 2 operator function keyon/off
1877 switch(chan_no)
1878 {
1879 case 0: case 1: case 2:
1880 case 9: case 10: case 11:
1881 if (CH->extended)
1882 {
1883 //if this is 1st channel forming up a 4-op channel
1884 //ALSO keyon/off slots of 2nd channel forming up 4-op channel
1885 if(v&0x20)
1886 {
1887 FM_KEYON (&CH->SLOT[SLOT1], 1);
1888 FM_KEYON (&CH->SLOT[SLOT2], 1);
1889 FM_KEYON (&(CH+3)->SLOT[SLOT1], 1);
1890 FM_KEYON (&(CH+3)->SLOT[SLOT2], 1);
1891 }
1892 else
1893 {
1894 FM_KEYOFF(&CH->SLOT[SLOT1],~1);
1895 FM_KEYOFF(&CH->SLOT[SLOT2],~1);
1896 FM_KEYOFF(&(CH+3)->SLOT[SLOT1],~1);
1897 FM_KEYOFF(&(CH+3)->SLOT[SLOT2],~1);
1898 }
1899 }
1900 else
1901 {
1902 //else normal 2 operator function keyon/off
1903 if(v&0x20)
1904 {
1905 FM_KEYON (&CH->SLOT[SLOT1], 1);
1906 FM_KEYON (&CH->SLOT[SLOT2], 1);
1907 }
1908 else
1909 {
1910 FM_KEYOFF(&CH->SLOT[SLOT1],~1);
1911 FM_KEYOFF(&CH->SLOT[SLOT2],~1);
1912 }
1913 }
1914 break;
1915
1916 case 3: case 4: case 5:
1917 case 12: case 13: case 14:
1918 if ((CH-3)->extended)
1919 {
1920 //if this is 2nd channel forming up 4-op channel just do nothing
1921 }
1922 else
1923 {
1924 //else normal 2 operator function keyon/off
1925 if(v&0x20)
1926 {
1927 FM_KEYON (&CH->SLOT[SLOT1], 1);
1928 FM_KEYON (&CH->SLOT[SLOT2], 1);
1929 }
1930 else
1931 {
1932 FM_KEYOFF(&CH->SLOT[SLOT1],~1);
1933 FM_KEYOFF(&CH->SLOT[SLOT2],~1);
1934 }
1935 }
1936 break;
1937
1938 default:
1939 if(v&0x20)
1940 {
1941 FM_KEYON (&CH->SLOT[SLOT1], 1);
1942 FM_KEYON (&CH->SLOT[SLOT2], 1);
1943 }
1944 else
1945 {
1946 FM_KEYOFF(&CH->SLOT[SLOT1],~1);
1947 FM_KEYOFF(&CH->SLOT[SLOT2],~1);
1948 }
1949 break;
1950 }
1951 }
1952 else
1953 {
1954 if(v&0x20)
1955 {
1956 FM_KEYON (&CH->SLOT[SLOT1], 1);
1957 FM_KEYON (&CH->SLOT[SLOT2], 1);
1958 }
1959 else
1960 {
1961 FM_KEYOFF(&CH->SLOT[SLOT1],~1);
1962 FM_KEYOFF(&CH->SLOT[SLOT2],~1);
1963 }
1964 }
1965 }
1966 /* update */
1967 if(CH->block_fnum != block_fnum)
1968 {
1969 UINT8 block = block_fnum >> 10;
1970
1971 CH->block_fnum = block_fnum;
1972
1973 CH->ksl_base = ksl_tab[block_fnum>>6];
1974 CH->fc = chip->fn_tab[block_fnum&0x03ff] >> (7-block);
1975
1976 /* BLK 2,1,0 bits -> bits 3,2,1 of kcode */
1977 CH->kcode = (CH->block_fnum&0x1c00)>>9;
1978
1979 /* the info below is actually opposite to what is stated in the Manuals (verifed on real YMF262) */
1980 /* if notesel == 0 -> lsb of kcode is bit 10 (MSB) of fnum */
1981 /* if notesel == 1 -> lsb of kcode is bit 9 (MSB-1) of fnum */
1982 if (chip->nts&0x40)
1983 CH->kcode |= (CH->block_fnum&0x100)>>8; /* notesel == 1 */
1984 else
1985 CH->kcode |= (CH->block_fnum&0x200)>>9; /* notesel == 0 */
1986
1987 if (chip->OPL3_mode & 1)
1988 {
1989 int chan_no = (r&0x0f) + ch_offset;
1990 /* in OPL3 mode */
1991 //DO THIS:
1992 //if this is 1st channel forming up a 4-op channel
1993 //ALSO update slots of 2nd channel forming up 4-op channel
1994 //else normal 2 operator function keyon/off
1995 //OR THIS:
1996 //if this is 2nd channel forming up 4-op channel just do nothing
1997 //else normal 2 operator function keyon/off
1998 switch(chan_no)
1999 {
2000 case 0: case 1: case 2:
2001 case 9: case 10: case 11:
2002 if (CH->extended)
2003 {
2004 //if this is 1st channel forming up a 4-op channel
2005 //ALSO update slots of 2nd channel forming up 4-op channel
2006
2007 /* refresh Total Level in FOUR SLOTs of this channel and channel+3 using data from THIS channel */
2008 CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl);
2009 CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl);
2010 (CH+3)->SLOT[SLOT1].TLL = (CH+3)->SLOT[SLOT1].TL + (CH->ksl_base>>(CH+3)->SLOT[SLOT1].ksl);
2011 (CH+3)->SLOT[SLOT2].TLL = (CH+3)->SLOT[SLOT2].TL + (CH->ksl_base>>(CH+3)->SLOT[SLOT2].ksl);
2012
2013 /* refresh frequency counter in FOUR SLOTs of this channel and channel+3 using data from THIS channel */
2014 CALC_FCSLOT(CH,&CH->SLOT[SLOT1]);
2015 CALC_FCSLOT(CH,&CH->SLOT[SLOT2]);
2016 CALC_FCSLOT(CH,&(CH+3)->SLOT[SLOT1]);
2017 CALC_FCSLOT(CH,&(CH+3)->SLOT[SLOT2]);
2018 }
2019 else
2020 {
2021 //else normal 2 operator function
2022 /* refresh Total Level in both SLOTs of this channel */
2023 CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl);
2024 CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl);
2025
2026 /* refresh frequency counter in both SLOTs of this channel */
2027 CALC_FCSLOT(CH,&CH->SLOT[SLOT1]);
2028 CALC_FCSLOT(CH,&CH->SLOT[SLOT2]);
2029 }
2030 break;
2031
2032 case 3: case 4: case 5:
2033 case 12: case 13: case 14:
2034 if ((CH-3)->extended)
2035 {
2036 //if this is 2nd channel forming up 4-op channel just do nothing
2037 }
2038 else
2039 {
2040 //else normal 2 operator function
2041 /* refresh Total Level in both SLOTs of this channel */
2042 CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl);
2043 CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl);
2044
2045 /* refresh frequency counter in both SLOTs of this channel */
2046 CALC_FCSLOT(CH,&CH->SLOT[SLOT1]);
2047 CALC_FCSLOT(CH,&CH->SLOT[SLOT2]);
2048 }
2049 break;
2050
2051 default:
2052 /* refresh Total Level in both SLOTs of this channel */
2053 CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl);
2054 CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl);
2055
2056 /* refresh frequency counter in both SLOTs of this channel */
2057 CALC_FCSLOT(CH,&CH->SLOT[SLOT1]);
2058 CALC_FCSLOT(CH,&CH->SLOT[SLOT2]);
2059 break;
2060 }
2061 }
2062 else
2063 {
2064 /* in OPL2 mode */
2065
2066 /* refresh Total Level in both SLOTs of this channel */
2067 CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl);
2068 CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl);
2069
2070 /* refresh frequency counter in both SLOTs of this channel */
2071 CALC_FCSLOT(CH,&CH->SLOT[SLOT1]);
2072 CALC_FCSLOT(CH,&CH->SLOT[SLOT2]);
2073 }
2074 }
2075 break;
2076
2077 case 0xc0:
2078 /* CH.D, CH.C, CH.B, CH.A, FB(3bits), C */
2079 if( (r&0xf) > 8) return;
2080
2081 CH = &chip->P_CH[(r&0xf) + ch_offset];
2082
2083 if( chip->OPL3_mode & 1 )
2084 {
2085 int base = ((r&0xf) + ch_offset) * 4;
2086
2087 /* OPL3 mode */
2088 chip->pan[ base ] = (v & 0x10) ? ~0 : 0; /* ch.A */
2089 chip->pan[ base +1 ] = (v & 0x20) ? ~0 : 0; /* ch.B */
2090 chip->pan[ base +2 ] = (v & 0x40) ? ~0 : 0; /* ch.C */
2091 chip->pan[ base +3 ] = (v & 0x80) ? ~0 : 0; /* ch.D */
2092 }
2093 else
2094 {
2095 int base = ((r&0xf) + ch_offset) * 4;
2096
2097 /* OPL2 mode - always enabled */
2098 chip->pan[ base ] = ~0; /* ch.A */
2099 chip->pan[ base +1 ] = ~0; /* ch.B */
2100 chip->pan[ base +2 ] = ~0; /* ch.C */
2101 chip->pan[ base +3 ] = ~0; /* ch.D */
2102 }
2103
2104 chip->pan_ctrl_value[ (r&0xf) + ch_offset ] = v; /* store control value for OPL3/OPL2 mode switching on the fly */
2105
2106 CH->SLOT[SLOT1].FB = (v>>1)&7 ? ((v>>1)&7) + 7 : 0;
2107 CH->SLOT[SLOT1].CON = v&1;
2108
2109 if( chip->OPL3_mode & 1 )
2110 {
2111 int chan_no = (r&0x0f) + ch_offset;
2112
2113 switch(chan_no)
2114 {
2115 case 0: case 1: case 2:
2116 case 9: case 10: case 11:
2117 if (CH->extended)
2118 {
2119 UINT8 conn = (CH->SLOT[SLOT1].CON<<1) | ((CH+3)->SLOT[SLOT1].CON<<0);
2120 switch(conn)
2121 {
2122 case 0:
2123 /* 1 -> 2 -> 3 -> 4 - out */
2124
2125 CH->SLOT[SLOT1].connect = &chip->phase_modulation;
2126 CH->SLOT[SLOT2].connect = &chip->phase_modulation2;
2127 (CH+3)->SLOT[SLOT1].connect = &chip->phase_modulation;
2128 (CH+3)->SLOT[SLOT2].connect = &chanout[ chan_no + 3 ];
2129 break;
2130 case 1:
2131 /* 1 -> 2 -\
2132 3 -> 4 -+- out */
2133
2134 CH->SLOT[SLOT1].connect = &chip->phase_modulation;
2135 CH->SLOT[SLOT2].connect = &chanout[ chan_no ];
2136 (CH+3)->SLOT[SLOT1].connect = &chip->phase_modulation;
2137 (CH+3)->SLOT[SLOT2].connect = &chanout[ chan_no + 3 ];
2138 break;
2139 case 2:
2140 /* 1 -----------\
2141 2 -> 3 -> 4 -+- out */
2142
2143 CH->SLOT[SLOT1].connect = &chanout[ chan_no ];
2144 CH->SLOT[SLOT2].connect = &chip->phase_modulation2;
2145 (CH+3)->SLOT[SLOT1].connect = &chip->phase_modulation;
2146 (CH+3)->SLOT[SLOT2].connect = &chanout[ chan_no + 3 ];
2147 break;
2148 case 3:
2149 /* 1 ------\
2150 2 -> 3 -+- out
2151 4 ------/ */
2152 CH->SLOT[SLOT1].connect = &chanout[ chan_no ];
2153 CH->SLOT[SLOT2].connect = &chip->phase_modulation2;
2154 (CH+3)->SLOT[SLOT1].connect = &chanout[ chan_no + 3 ];
2155 (CH+3)->SLOT[SLOT2].connect = &chanout[ chan_no + 3 ];
2156 break;
2157 }
2158 }
2159 else
2160 {
2161 /* 2 operators mode */
2162 CH->SLOT[SLOT1].connect = CH->SLOT[SLOT1].CON ? &chanout[(r&0xf)+ch_offset] : &chip->phase_modulation;
2163 CH->SLOT[SLOT2].connect = &chanout[(r&0xf)+ch_offset];
2164 }
2165 break;
2166
2167 case 3: case 4: case 5:
2168 case 12: case 13: case 14:
2169 if ((CH-3)->extended)
2170 {
2171 UINT8 conn = ((CH-3)->SLOT[SLOT1].CON<<1) | (CH->SLOT[SLOT1].CON<<0);
2172 switch(conn)
2173 {
2174 case 0:
2175 /* 1 -> 2 -> 3 -> 4 - out */
2176
2177 (CH-3)->SLOT[SLOT1].connect = &chip->phase_modulation;
2178 (CH-3)->SLOT[SLOT2].connect = &chip->phase_modulation2;
2179 CH->SLOT[SLOT1].connect = &chip->phase_modulation;
2180 CH->SLOT[SLOT2].connect = &chanout[ chan_no ];
2181 break;
2182 case 1:
2183 /* 1 -> 2 -\
2184 3 -> 4 -+- out */
2185
2186 (CH-3)->SLOT[SLOT1].connect = &chip->phase_modulation;
2187 (CH-3)->SLOT[SLOT2].connect = &chanout[ chan_no - 3 ];
2188 CH->SLOT[SLOT1].connect = &chip->phase_modulation;
2189 CH->SLOT[SLOT2].connect = &chanout[ chan_no ];
2190 break;
2191 case 2:
2192 /* 1 -----------\
2193 2 -> 3 -> 4 -+- out */
2194
2195 (CH-3)->SLOT[SLOT1].connect = &chanout[ chan_no - 3 ];
2196 (CH-3)->SLOT[SLOT2].connect = &chip->phase_modulation2;
2197 CH->SLOT[SLOT1].connect = &chip->phase_modulation;
2198 CH->SLOT[SLOT2].connect = &chanout[ chan_no ];
2199 break;
2200 case 3:
2201 /* 1 ------\
2202 2 -> 3 -+- out
2203 4 ------/ */
2204 (CH-3)->SLOT[SLOT1].connect = &chanout[ chan_no - 3 ];
2205 (CH-3)->SLOT[SLOT2].connect = &chip->phase_modulation2;
2206 CH->SLOT[SLOT1].connect = &chanout[ chan_no ];
2207 CH->SLOT[SLOT2].connect = &chanout[ chan_no ];
2208 break;
2209 }
2210 }
2211 else
2212 {
2213 /* 2 operators mode */
2214 CH->SLOT[SLOT1].connect = CH->SLOT[SLOT1].CON ? &chanout[(r&0xf)+ch_offset] : &chip->phase_modulation;
2215 CH->SLOT[SLOT2].connect = &chanout[(r&0xf)+ch_offset];
2216 }
2217 break;
2218
2219 default:
2220 /* 2 operators mode */
2221 CH->SLOT[SLOT1].connect = CH->SLOT[SLOT1].CON ? &chanout[(r&0xf)+ch_offset] : &chip->phase_modulation;
2222 CH->SLOT[SLOT2].connect = &chanout[(r&0xf)+ch_offset];
2223 break;
2224 }
2225 }
2226 else
2227 {
2228 /* OPL2 mode - always 2 operators mode */
2229 CH->SLOT[SLOT1].connect = CH->SLOT[SLOT1].CON ? &chanout[(r&0xf)+ch_offset] : &chip->phase_modulation;
2230 CH->SLOT[SLOT2].connect = &chanout[(r&0xf)+ch_offset];
2231 }
2232 break;
2233
2234 case 0xe0: /* waveform select */
2235 slot = slot_array[r&0x1f];
2236 if(slot < 0) return;
2237
2238 slot += ch_offset*2;
2239
2240 CH = &chip->P_CH[slot/2];
2241
2242
2243 /* store 3-bit value written regardless of current OPL2 or OPL3 mode... (verified on real YMF262) */
2244 v &= 7;
2245 CH->SLOT[slot&1].waveform_number = v;
2246
2247 /* ... but select only waveforms 0-3 in OPL2 mode */
2248 if( !(chip->OPL3_mode & 1) )
2249 {
2250 v &= 3; /* we're in OPL2 mode */
2251 }
2252 CH->SLOT[slot&1].wavetable = v * SIN_LEN;
2253 break;
2254 }
2255 }
2256
2257 /*static TIMER_CALLBACK( cymfile_callback )
2258 {
2259 if (cymfile)
2260 {
2261 fputc( (unsigned char)0, cymfile );
2262 }
2263 }*/
2264
2265 /* lock/unlock for common table */
OPL3_LockTable()2266 static int OPL3_LockTable()
2267 {
2268 num_lock++;
2269 if(num_lock>1) return 0;
2270
2271 /* first time */
2272
2273 if( !init_tables() )
2274 {
2275 num_lock--;
2276 return -1;
2277 }
2278
2279 /*if (LOG_CYM_FILE)
2280 {
2281 cymfile = fopen("ymf262_.cym","wb");
2282 if (cymfile)
2283 timer_pulse ( device->machine, ATTOTIME_IN_HZ(110), NULL, 0, cymfile_callback); //110 Hz pulse timer
2284 else
2285 logerror("Could not create ymf262_.cym file\n");
2286 }*/
2287
2288 return 0;
2289 }
2290
OPL3_UnLockTable(void)2291 static void OPL3_UnLockTable(void)
2292 {
2293 if(num_lock) num_lock--;
2294 if(num_lock) return;
2295
2296 /* last time */
2297
2298 OPLCloseTable();
2299
2300 /*if (LOG_CYM_FILE)
2301 fclose (cymfile);
2302 cymfile = NULL;*/
2303 }
2304
OPL3ResetChip(OPL3 * chip)2305 static void OPL3ResetChip(OPL3 *chip)
2306 {
2307 int c,s;
2308
2309 chip->eg_timer = 0;
2310 chip->eg_cnt = 0;
2311
2312 chip->noise_rng = 1; /* noise shift register */
2313 chip->nts = 0; /* note split */
2314 OPL3_STATUS_RESET(chip,0x60);
2315
2316 /* reset with register write */
2317 OPL3WriteReg(chip,0x01,0); /* test register */
2318 OPL3WriteReg(chip,0x02,0); /* Timer1 */
2319 OPL3WriteReg(chip,0x03,0); /* Timer2 */
2320 OPL3WriteReg(chip,0x04,0); /* IRQ mask clear */
2321
2322
2323 //FIX IT registers 101, 104 and 105
2324
2325
2326 //FIX IT (dont change CH.D, CH.C, CH.B and CH.A in C0-C8 registers)
2327 for(c = 0xff ; c >= 0x20 ; c-- )
2328 OPL3WriteReg(chip,c,0);
2329 //FIX IT (dont change CH.D, CH.C, CH.B and CH.A in C0-C8 registers)
2330 for(c = 0x1ff ; c >= 0x120 ; c-- )
2331 OPL3WriteReg(chip,c,0);
2332
2333
2334
2335 /* reset operator parameters */
2336 for( c = 0 ; c < 9*2 ; c++ )
2337 {
2338 OPL3_CH *CH = &chip->P_CH[c];
2339 for(s = 0 ; s < 2 ; s++ )
2340 {
2341 CH->SLOT[s].state = EG_OFF;
2342 CH->SLOT[s].volume = MAX_ATT_INDEX;
2343 }
2344 }
2345 }
2346
2347 /* Create one of virtual YMF262 */
2348 /* 'clock' is chip clock in Hz */
2349 /* 'rate' is sampling rate */
OPL3Create(int clock,int rate,int type)2350 static OPL3 *OPL3Create(int clock, int rate, int type)
2351 {
2352 OPL3 *chip;
2353
2354 if (OPL3_LockTable() == -1) return NULL;
2355
2356 /* allocate memory block */
2357 chip = (OPL3 *)malloc(sizeof(OPL3));
2358
2359 if (chip==NULL)
2360 return NULL;
2361
2362 /* clear */
2363 memset(chip, 0, sizeof(OPL3));
2364
2365 chip->type = type;
2366 chip->clock = clock;
2367 chip->rate = rate;
2368
2369 /* init global tables */
2370 OPL3_initalize(chip);
2371
2372 /* reset chip */
2373 OPL3ResetChip(chip);
2374 return chip;
2375 }
2376
2377 /* Destroy one of virtual YMF262 */
OPL3Destroy(OPL3 * chip)2378 static void OPL3Destroy(OPL3 *chip)
2379 {
2380 OPL3_UnLockTable();
2381 free(chip);
2382 }
2383
2384
2385 /* Optional handlers */
2386
OPL3SetTimerHandler(OPL3 * chip,OPL3_TIMERHANDLER timer_handler,void * param)2387 static void OPL3SetTimerHandler(OPL3 *chip,OPL3_TIMERHANDLER timer_handler,void *param)
2388 {
2389 chip->timer_handler = timer_handler;
2390 chip->TimerParam = param;
2391 }
OPL3SetIRQHandler(OPL3 * chip,OPL3_IRQHANDLER IRQHandler,void * param)2392 static void OPL3SetIRQHandler(OPL3 *chip,OPL3_IRQHANDLER IRQHandler,void *param)
2393 {
2394 chip->IRQHandler = IRQHandler;
2395 chip->IRQParam = param;
2396 }
OPL3SetUpdateHandler(OPL3 * chip,OPL3_UPDATEHANDLER UpdateHandler,void * param)2397 static void OPL3SetUpdateHandler(OPL3 *chip,OPL3_UPDATEHANDLER UpdateHandler,void *param)
2398 {
2399 chip->UpdateHandler = UpdateHandler;
2400 chip->UpdateParam = param;
2401 }
2402
2403 /* YMF262 I/O interface */
OPL3Write(OPL3 * chip,int a,int v)2404 static int OPL3Write(OPL3 *chip, int a, int v)
2405 {
2406 /* data bus is 8 bits */
2407 v &= 0xff;
2408
2409 switch(a&3)
2410 {
2411 case 0: /* address port 0 (register set #1) */
2412 chip->address = v;
2413 break;
2414
2415 case 1: /* data port - ignore A1 */
2416 case 3: /* data port - ignore A1 */
2417 if(chip->UpdateHandler) chip->UpdateHandler(chip->UpdateParam/*,0*/);
2418 OPL3WriteReg(chip,chip->address,v);
2419 break;
2420
2421 case 2: /* address port 1 (register set #2) */
2422
2423 /* verified on real YMF262:
2424 in OPL3 mode:
2425 address line A1 is stored during *address* write and ignored during *data* write.
2426
2427 in OPL2 mode:
2428 register set#2 writes go to register set#1 (ignoring A1)
2429 verified on registers from set#2: 0x01, 0x04, 0x20-0xef
2430 The only exception is register 0x05.
2431 */
2432 if( chip->OPL3_mode & 1 )
2433 {
2434 /* OPL3 mode */
2435 chip->address = v | 0x100;
2436 }
2437 else
2438 {
2439 /* in OPL2 mode the only accessible in set #2 is register 0x05 */
2440 if( v==5 )
2441 chip->address = v | 0x100;
2442 else
2443 chip->address = v; /* verified range: 0x01, 0x04, 0x20-0xef(set #2 becomes set #1 in opl2 mode) */
2444 }
2445 break;
2446 }
2447
2448 return chip->status>>7;
2449 }
2450
OPL3Read(OPL3 * chip,int a)2451 static unsigned char OPL3Read(OPL3 *chip,int a)
2452 {
2453 if( a==0 )
2454 {
2455 /* status port */
2456 return chip->status;
2457 }
2458
2459 return 0x00; /* verified on real YMF262 */
2460 }
2461
2462
2463
OPL3TimerOver(OPL3 * chip,int c)2464 static int OPL3TimerOver(OPL3 *chip,int c)
2465 {
2466 if( c )
2467 { /* Timer B */
2468 OPL3_STATUS_SET(chip,0x20);
2469 }
2470 else
2471 { /* Timer A */
2472 OPL3_STATUS_SET(chip,0x40);
2473 }
2474 /* reload timer */
2475 //if (chip->timer_handler) (chip->timer_handler)(chip->TimerParam,c,attotime_mul(chip->TimerBase, chip->T[c]));
2476 return chip->status>>7;
2477 }
2478
2479
2480
2481
ymf262_init(int clock,int rate)2482 void * ymf262_init(int clock, int rate)
2483 {
2484 return OPL3Create(clock,rate,OPL3_TYPE_YMF262);
2485 }
2486
ymf262_shutdown(void * chip)2487 void ymf262_shutdown(void *chip)
2488 {
2489 OPL3Destroy((OPL3 *)chip);
2490 }
ymf262_reset_chip(void * chip)2491 void ymf262_reset_chip(void *chip)
2492 {
2493 OPL3ResetChip((OPL3 *)chip);
2494 }
2495
ymf262_write(void * chip,int a,int v)2496 int ymf262_write(void *chip, int a, int v)
2497 {
2498 return OPL3Write((OPL3 *)chip, a, v);
2499 }
2500
ymf262_read(void * chip,int a)2501 unsigned char ymf262_read(void *chip, int a)
2502 {
2503 /* Note on status register: */
2504
2505 /* YM3526(OPL) and YM3812(OPL2) return bit2 and bit1 in HIGH state */
2506
2507 /* YMF262(OPL3) always returns bit2 and bit1 in LOW state */
2508 /* which can be used to identify the chip */
2509
2510 /* YMF278(OPL4) returns bit2 in LOW and bit1 in HIGH state ??? info from manual - not verified */
2511
2512 return OPL3Read((OPL3 *)chip, a);
2513 }
ymf262_timer_over(void * chip,int c)2514 int ymf262_timer_over(void *chip, int c)
2515 {
2516 return OPL3TimerOver((OPL3 *)chip, c);
2517 }
2518
ymf262_set_timer_handler(void * chip,OPL3_TIMERHANDLER timer_handler,void * param)2519 void ymf262_set_timer_handler(void *chip, OPL3_TIMERHANDLER timer_handler, void *param)
2520 {
2521 OPL3SetTimerHandler((OPL3 *)chip, timer_handler, param);
2522 }
ymf262_set_irq_handler(void * chip,OPL3_IRQHANDLER IRQHandler,void * param)2523 void ymf262_set_irq_handler(void *chip,OPL3_IRQHANDLER IRQHandler,void *param)
2524 {
2525 OPL3SetIRQHandler((OPL3 *)chip, IRQHandler, param);
2526 }
ymf262_set_update_handler(void * chip,OPL3_UPDATEHANDLER UpdateHandler,void * param)2527 void ymf262_set_update_handler(void *chip,OPL3_UPDATEHANDLER UpdateHandler,void *param)
2528 {
2529 OPL3SetUpdateHandler((OPL3 *)chip, UpdateHandler, param);
2530 }
2531
ymf262_set_mutemask(void * chip,UINT32 MuteMask)2532 void ymf262_set_mutemask(void *chip, UINT32 MuteMask)
2533 {
2534 OPL3 *opl3 = (OPL3 *)chip;
2535 UINT8 CurChn;
2536
2537 for (CurChn = 0; CurChn < 18; CurChn ++)
2538 opl3->P_CH[CurChn].Muted = (MuteMask >> CurChn) & 0x01;
2539 for (CurChn = 0; CurChn < 5; CurChn ++)
2540 opl3->MuteSpc[CurChn] = (MuteMask >> (CurChn + 18)) & 0x01;
2541
2542 return;
2543 }
2544
2545
2546 /*
2547 ** Generate samples for one of the YMF262's
2548 **
2549 ** 'which' is the virtual YMF262 number
2550 ** '**buffers' is table of 4 pointers to the buffers: CH.A, CH.B, CH.C and CH.D
2551 ** 'length' is the number of samples that should be generated
2552 */
ymf262_update_one(void * _chip,OPL3SAMPLE ** buffers,int length)2553 void ymf262_update_one(void *_chip, OPL3SAMPLE **buffers, int length)
2554 {
2555 OPL3 *chip = (OPL3 *)_chip;
2556 UINT8 rhythm = chip->rhythm&0x20;
2557
2558 OPL3SAMPLE *ch_a = buffers[0];
2559 OPL3SAMPLE *ch_b = buffers[1];
2560 //OPL3SAMPLE *ch_c = buffers[2];
2561 //OPL3SAMPLE *ch_d = buffers[3];
2562
2563 int i;
2564 int chn;
2565
2566 for( i=0; i < length ; i++ )
2567 {
2568 int a,b,c,d;
2569
2570
2571 advance_lfo(chip);
2572
2573 /* clear channel outputs */
2574 memset(chip->chanout, 0, sizeof(signed int) * 18);
2575
2576 #if 1
2577 /* register set #1 */
2578 chan_calc(chip, &chip->P_CH[0]); /* extended 4op ch#0 part 1 or 2op ch#0 */
2579 if (chip->P_CH[0].extended)
2580 chan_calc_ext(chip, &chip->P_CH[3]); /* extended 4op ch#0 part 2 */
2581 else
2582 chan_calc(chip, &chip->P_CH[3]); /* standard 2op ch#3 */
2583
2584
2585 chan_calc(chip, &chip->P_CH[1]); /* extended 4op ch#1 part 1 or 2op ch#1 */
2586 if (chip->P_CH[1].extended)
2587 chan_calc_ext(chip, &chip->P_CH[4]); /* extended 4op ch#1 part 2 */
2588 else
2589 chan_calc(chip, &chip->P_CH[4]); /* standard 2op ch#4 */
2590
2591
2592 chan_calc(chip, &chip->P_CH[2]); /* extended 4op ch#2 part 1 or 2op ch#2 */
2593 if (chip->P_CH[2].extended)
2594 chan_calc_ext(chip, &chip->P_CH[5]); /* extended 4op ch#2 part 2 */
2595 else
2596 chan_calc(chip, &chip->P_CH[5]); /* standard 2op ch#5 */
2597
2598
2599 if(!rhythm)
2600 {
2601 chan_calc(chip, &chip->P_CH[6]);
2602 chan_calc(chip, &chip->P_CH[7]);
2603 chan_calc(chip, &chip->P_CH[8]);
2604 }
2605 else /* Rhythm part */
2606 {
2607 chan_calc_rhythm(chip, &chip->P_CH[0], (chip->noise_rng>>0)&1 );
2608 }
2609
2610 /* register set #2 */
2611 chan_calc(chip, &chip->P_CH[ 9]);
2612 if (chip->P_CH[9].extended)
2613 chan_calc_ext(chip, &chip->P_CH[12]);
2614 else
2615 chan_calc(chip, &chip->P_CH[12]);
2616
2617
2618 chan_calc(chip, &chip->P_CH[10]);
2619 if (chip->P_CH[10].extended)
2620 chan_calc_ext(chip, &chip->P_CH[13]);
2621 else
2622 chan_calc(chip, &chip->P_CH[13]);
2623
2624
2625 chan_calc(chip, &chip->P_CH[11]);
2626 if (chip->P_CH[11].extended)
2627 chan_calc_ext(chip, &chip->P_CH[14]);
2628 else
2629 chan_calc(chip, &chip->P_CH[14]);
2630
2631
2632 /* channels 15,16,17 are fixed 2-operator channels only */
2633 chan_calc(chip, &chip->P_CH[15]);
2634 chan_calc(chip, &chip->P_CH[16]);
2635 chan_calc(chip, &chip->P_CH[17]);
2636 #endif
2637
2638 /* accumulator register set #1 */
2639 a = chip->chanout[0] & chip->pan[0];
2640 b = chip->chanout[0] & chip->pan[1];
2641 c = chip->chanout[0] & chip->pan[2];
2642 d = chip->chanout[0] & chip->pan[3];
2643 #if 1
2644 a += chip->chanout[1] & chip->pan[4];
2645 b += chip->chanout[1] & chip->pan[5];
2646 c += chip->chanout[1] & chip->pan[6];
2647 d += chip->chanout[1] & chip->pan[7];
2648 a += chip->chanout[2] & chip->pan[8];
2649 b += chip->chanout[2] & chip->pan[9];
2650 c += chip->chanout[2] & chip->pan[10];
2651 d += chip->chanout[2] & chip->pan[11];
2652
2653 a += chip->chanout[3] & chip->pan[12];
2654 b += chip->chanout[3] & chip->pan[13];
2655 c += chip->chanout[3] & chip->pan[14];
2656 d += chip->chanout[3] & chip->pan[15];
2657 a += chip->chanout[4] & chip->pan[16];
2658 b += chip->chanout[4] & chip->pan[17];
2659 c += chip->chanout[4] & chip->pan[18];
2660 d += chip->chanout[4] & chip->pan[19];
2661 a += chip->chanout[5] & chip->pan[20];
2662 b += chip->chanout[5] & chip->pan[21];
2663 c += chip->chanout[5] & chip->pan[22];
2664 d += chip->chanout[5] & chip->pan[23];
2665
2666 a += chip->chanout[6] & chip->pan[24];
2667 b += chip->chanout[6] & chip->pan[25];
2668 c += chip->chanout[6] & chip->pan[26];
2669 d += chip->chanout[6] & chip->pan[27];
2670 a += chip->chanout[7] & chip->pan[28];
2671 b += chip->chanout[7] & chip->pan[29];
2672 c += chip->chanout[7] & chip->pan[30];
2673 d += chip->chanout[7] & chip->pan[31];
2674 a += chip->chanout[8] & chip->pan[32];
2675 b += chip->chanout[8] & chip->pan[33];
2676 c += chip->chanout[8] & chip->pan[34];
2677 d += chip->chanout[8] & chip->pan[35];
2678
2679 /* accumulator register set #2 */
2680 a += chip->chanout[9] & chip->pan[36];
2681 b += chip->chanout[9] & chip->pan[37];
2682 c += chip->chanout[9] & chip->pan[38];
2683 d += chip->chanout[9] & chip->pan[39];
2684 a += chip->chanout[10] & chip->pan[40];
2685 b += chip->chanout[10] & chip->pan[41];
2686 c += chip->chanout[10] & chip->pan[42];
2687 d += chip->chanout[10] & chip->pan[43];
2688 a += chip->chanout[11] & chip->pan[44];
2689 b += chip->chanout[11] & chip->pan[45];
2690 c += chip->chanout[11] & chip->pan[46];
2691 d += chip->chanout[11] & chip->pan[47];
2692
2693 a += chip->chanout[12] & chip->pan[48];
2694 b += chip->chanout[12] & chip->pan[49];
2695 c += chip->chanout[12] & chip->pan[50];
2696 d += chip->chanout[12] & chip->pan[51];
2697 a += chip->chanout[13] & chip->pan[52];
2698 b += chip->chanout[13] & chip->pan[53];
2699 c += chip->chanout[13] & chip->pan[54];
2700 d += chip->chanout[13] & chip->pan[55];
2701 a += chip->chanout[14] & chip->pan[56];
2702 b += chip->chanout[14] & chip->pan[57];
2703 c += chip->chanout[14] & chip->pan[58];
2704 d += chip->chanout[14] & chip->pan[59];
2705
2706 a += chip->chanout[15] & chip->pan[60];
2707 b += chip->chanout[15] & chip->pan[61];
2708 c += chip->chanout[15] & chip->pan[62];
2709 d += chip->chanout[15] & chip->pan[63];
2710 a += chip->chanout[16] & chip->pan[64];
2711 b += chip->chanout[16] & chip->pan[65];
2712 c += chip->chanout[16] & chip->pan[66];
2713 d += chip->chanout[16] & chip->pan[67];
2714 a += chip->chanout[17] & chip->pan[68];
2715 b += chip->chanout[17] & chip->pan[69];
2716 c += chip->chanout[17] & chip->pan[70];
2717 d += chip->chanout[17] & chip->pan[71];
2718 #endif
2719 a >>= FINAL_SH;
2720 b >>= FINAL_SH;
2721 c >>= FINAL_SH;
2722 d >>= FINAL_SH;
2723
2724 /* limit check */
2725 //a = limit( a , MAXOUT, MINOUT );
2726 //b = limit( b , MAXOUT, MINOUT );
2727 //c = limit( c , MAXOUT, MINOUT );
2728 //d = limit( d , MAXOUT, MINOUT );
2729
2730 #ifdef SAVE_SAMPLE
2731 if (which==0)
2732 {
2733 SAVE_ALL_CHANNELS
2734 }
2735 #endif
2736
2737 /* store to sound buffer */
2738 ch_a[i] = a+c;
2739 ch_b[i] = b+d;
2740 //ch_c[i] = c;
2741 //ch_d[i] = d;
2742
2743 advance(chip);
2744 }
2745
2746 }
2747
2748