1 /**************************************************************************//**
2 * @file core_cm4.h
3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
4 * @version V3.00
5 * @date 03. February 2012
6 *
7 * @note
8 * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
9 *
10 * @par
11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
12 * processor based microcontrollers. This file can be freely distributed
13 * within development tools that are supporting such ARM based processors.
14 *
15 * @par
16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
21 *
22 ******************************************************************************/
23 #if defined ( __ICCARM__ )
24 #pragma system_include /* treat file as system include file for MISRA check */
25 #endif
26
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30
31 #ifndef __CORE_CM4_H_GENERIC
32 #define __CORE_CM4_H_GENERIC
33
34 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
35 CMSIS violates the following MISRA-C:2004 rules:
36
37 \li Required Rule 8.5, object/function definition in header file.<br>
38 Function definitions in header files are used to allow 'inlining'.
39
40 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
41 Unions are used for effective representation of core registers.
42
43 \li Advisory Rule 19.7, Function-like macro defined.<br>
44 Function-like macros are used to allow more efficient code.
45 */
46
47
48 /*******************************************************************************
49 * CMSIS definitions
50 ******************************************************************************/
51 /** \ingroup Cortex_M4
52 @{
53 */
54
55 /* CMSIS CM4 definitions */
56 #define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
57 #define __CM4_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
58 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
59 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
60
61 #define __CORTEX_M (0x04) /*!< Cortex-M Core */
62
63
64 #if defined ( __CC_ARM )
65 #define __ASM __asm /*!< asm keyword for ARM Compiler */
66 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
67 #define __STATIC_INLINE static __inline
68
69 #elif defined ( __ICCARM__ )
70 #define __ASM __asm /*!< asm keyword for IAR Compiler */
71 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
72 #define __STATIC_INLINE static inline
73
74 #elif defined ( __TMS470__ )
75 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
76 #define __STATIC_INLINE static inline
77
78 #elif defined ( __GNUC__ )
79 #define __ASM __asm /*!< asm keyword for GNU Compiler */
80 #define __INLINE inline /*!< inline keyword for GNU Compiler */
81 #define __STATIC_INLINE static inline
82
83 #elif defined ( __TASKING__ )
84 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
85 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
86 #define __STATIC_INLINE static inline
87
88 #endif
89
90 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
91 */
92 #if defined ( __CC_ARM )
93 #if defined __TARGET_FPU_VFP
94 #if (__FPU_PRESENT == 1)
95 #define __FPU_USED 1
96 #else
97 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
98 #define __FPU_USED 0
99 #endif
100 #else
101 #define __FPU_USED 0
102 #endif
103
104 #elif defined ( __ICCARM__ )
105 #if defined __ARMVFP__
106 #if (__FPU_PRESENT == 1)
107 #define __FPU_USED 1
108 #else
109 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
110 #define __FPU_USED 0
111 #endif
112 #else
113 #define __FPU_USED 0
114 #endif
115
116 #elif defined ( __TMS470__ )
117 #if defined __TI_VFP_SUPPORT__
118 #if (__FPU_PRESENT == 1)
119 #define __FPU_USED 1
120 #else
121 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
122 #define __FPU_USED 0
123 #endif
124 #else
125 #define __FPU_USED 0
126 #endif
127
128 #elif defined ( __GNUC__ )
129 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
130 #if (__FPU_PRESENT == 1)
131 #define __FPU_USED 1
132 #else
133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
134 #define __FPU_USED 0
135 #endif
136 #else
137 #define __FPU_USED 0
138 #endif
139
140 #elif defined ( __TASKING__ )
141 /* add preprocessor checks to define __FPU_USED */
142 #define __FPU_USED 0
143 #endif
144
145 #include <stdint.h> /* standard types definitions */
146 #include <core_cmInstr.h> /* Core Instruction Access */
147 #include <core_cmFunc.h> /* Core Function Access */
148 #include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
149
150 #endif /* __CORE_CM4_H_GENERIC */
151
152 #ifndef __CMSIS_GENERIC
153
154 #ifndef __CORE_CM4_H_DEPENDANT
155 #define __CORE_CM4_H_DEPENDANT
156
157 /* check device defines and use defaults */
158 #if defined __CHECK_DEVICE_DEFINES
159 #ifndef __CM4_REV
160 #define __CM4_REV 0x0000
161 #warning "__CM4_REV not defined in device header file; using default!"
162 #endif
163
164 #ifndef __FPU_PRESENT
165 #define __FPU_PRESENT 0
166 #warning "__FPU_PRESENT not defined in device header file; using default!"
167 #endif
168
169 #ifndef __MPU_PRESENT
170 #define __MPU_PRESENT 0
171 #warning "__MPU_PRESENT not defined in device header file; using default!"
172 #endif
173
174 #ifndef __NVIC_PRIO_BITS
175 #define __NVIC_PRIO_BITS 4
176 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
177 #endif
178
179 #ifndef __Vendor_SysTickConfig
180 #define __Vendor_SysTickConfig 0
181 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
182 #endif
183 #endif
184
185 /* IO definitions (access restrictions to peripheral registers) */
186 /**
187 \defgroup CMSIS_glob_defs CMSIS Global Defines
188
189 <strong>IO Type Qualifiers</strong> are used
190 \li to specify the access to peripheral variables.
191 \li for automatic generation of peripheral register debug information.
192 */
193 #ifdef __cplusplus
194 #define __I volatile /*!< Defines 'read only' permissions */
195 #else
196 #define __I volatile const /*!< Defines 'read only' permissions */
197 #endif
198 #define __O volatile /*!< Defines 'write only' permissions */
199 #define __IO volatile /*!< Defines 'read / write' permissions */
200
201 /*@} end of group Cortex_M4 */
202
203
204
205 /*******************************************************************************
206 * Register Abstraction
207 Core Register contain:
208 - Core Register
209 - Core NVIC Register
210 - Core SCB Register
211 - Core SysTick Register
212 - Core Debug Register
213 - Core MPU Register
214 - Core FPU Register
215 ******************************************************************************/
216 /** \defgroup CMSIS_core_register Defines and Type Definitions
217 \brief Type definitions and defines for Cortex-M processor based devices.
218 */
219
220 /** \ingroup CMSIS_core_register
221 \defgroup CMSIS_CORE Status and Control Registers
222 \brief Core Register type definitions.
223 @{
224 */
225
226 /** \brief Union type to access the Application Program Status Register (APSR).
227 */
228 typedef union
229 {
230 struct
231 {
232 #if (__CORTEX_M != 0x04)
233 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
234 #else
235 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
236 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
237 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
238 #endif
239 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
240 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
241 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
242 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
243 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
244 } b; /*!< Structure used for bit access */
245 uint32_t w; /*!< Type used for word access */
246 } APSR_Type;
247
248
249 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
250 */
251 typedef union
252 {
253 struct
254 {
255 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
256 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
257 } b; /*!< Structure used for bit access */
258 uint32_t w; /*!< Type used for word access */
259 } IPSR_Type;
260
261
262 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
263 */
264 typedef union
265 {
266 struct
267 {
268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
269 #if (__CORTEX_M != 0x04)
270 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
271 #else
272 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
273 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
274 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
275 #endif
276 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
277 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
278 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
279 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
280 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
281 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
282 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
283 } b; /*!< Structure used for bit access */
284 uint32_t w; /*!< Type used for word access */
285 } xPSR_Type;
286
287
288 /** \brief Union type to access the Control Registers (CONTROL).
289 */
290 typedef union
291 {
292 struct
293 {
294 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
295 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
296 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
297 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
298 } b; /*!< Structure used for bit access */
299 uint32_t w; /*!< Type used for word access */
300 } CONTROL_Type;
301
302 /*@} end of group CMSIS_CORE */
303
304
305 /** \ingroup CMSIS_core_register
306 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
307 \brief Type definitions for the NVIC Registers
308 @{
309 */
310
311 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
312 */
313 typedef struct
314 {
315 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
316 uint32_t RESERVED0[24];
317 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
318 uint32_t RSERVED1[24];
319 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
320 uint32_t RESERVED2[24];
321 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
322 uint32_t RESERVED3[24];
323 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
324 uint32_t RESERVED4[56];
325 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
326 uint32_t RESERVED5[644];
327 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
328 } NVIC_Type;
329
330 /* Software Triggered Interrupt Register Definitions */
331 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
332 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
333
334 /*@} end of group CMSIS_NVIC */
335
336
337 /** \ingroup CMSIS_core_register
338 \defgroup CMSIS_SCB System Control Block (SCB)
339 \brief Type definitions for the System Control Block Registers
340 @{
341 */
342
343 /** \brief Structure type to access the System Control Block (SCB).
344 */
345 typedef struct
346 {
347 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
348 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
349 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
350 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
351 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
352 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
353 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
354 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
355 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
356 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
357 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
358 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
359 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
360 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
361 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
362 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
363 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
364 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
365 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
366 uint32_t RESERVED0[5];
367 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
368 } SCB_Type;
369
370 /* SCB CPUID Register Definitions */
371 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
372 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
373
374 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
375 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
376
377 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
378 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
379
380 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
381 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
382
383 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
384 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
385
386 /* SCB Interrupt Control State Register Definitions */
387 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
388 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
389
390 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
391 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
392
393 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
394 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
395
396 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
397 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
398
399 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
400 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
401
402 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
403 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
404
405 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
406 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
407
408 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
409 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
410
411 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
412 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
413
414 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
415 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
416
417 /* SCB Vector Table Offset Register Definitions */
418 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
419 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
420
421 /* SCB Application Interrupt and Reset Control Register Definitions */
422 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
423 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
424
425 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
426 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
427
428 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
429 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
430
431 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
432 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
433
434 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
435 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
436
437 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
438 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
439
440 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
441 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
442
443 /* SCB System Control Register Definitions */
444 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
445 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
446
447 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
448 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
449
450 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
451 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
452
453 /* SCB Configuration Control Register Definitions */
454 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
455 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
456
457 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
458 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
459
460 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
461 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
462
463 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
464 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
465
466 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
467 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
468
469 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
470 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
471
472 /* SCB System Handler Control and State Register Definitions */
473 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
474 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
475
476 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
477 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
478
479 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
480 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
481
482 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
483 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
484
485 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
486 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
487
488 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
489 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
490
491 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
492 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
493
494 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
495 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
496
497 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
498 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
499
500 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
501 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
502
503 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
504 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
505
506 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
507 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
508
509 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
510 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
511
512 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
513 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
514
515 /* SCB Configurable Fault Status Registers Definitions */
516 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
517 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
518
519 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
520 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
521
522 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
523 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
524
525 /* SCB Hard Fault Status Registers Definitions */
526 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
527 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
528
529 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
530 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
531
532 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
533 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
534
535 /* SCB Debug Fault Status Register Definitions */
536 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
537 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
538
539 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
540 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
541
542 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
543 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
544
545 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
546 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
547
548 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
549 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
550
551 /*@} end of group CMSIS_SCB */
552
553
554 /** \ingroup CMSIS_core_register
555 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
556 \brief Type definitions for the System Control and ID Register not in the SCB
557 @{
558 */
559
560 /** \brief Structure type to access the System Control and ID Register not in the SCB.
561 */
562 typedef struct
563 {
564 uint32_t RESERVED0[1];
565 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
566 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
567 } SCnSCB_Type;
568
569 /* Interrupt Controller Type Register Definitions */
570 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
571 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
572
573 /* Auxiliary Control Register Definitions */
574 #define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
575 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
576
577 #define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
578 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
579
580 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
581 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
582
583 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
584 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
585
586 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
587 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
588
589 /*@} end of group CMSIS_SCnotSCB */
590
591
592 /** \ingroup CMSIS_core_register
593 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
594 \brief Type definitions for the System Timer Registers.
595 @{
596 */
597
598 /** \brief Structure type to access the System Timer (SysTick).
599 */
600 typedef struct
601 {
602 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
603 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
604 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
605 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
606 } SysTick_Type;
607
608 /* SysTick Control / Status Register Definitions */
609 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
610 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
611
612 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
613 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
614
615 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
616 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
617
618 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
619 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
620
621 /* SysTick Reload Register Definitions */
622 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
623 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
624
625 /* SysTick Current Register Definitions */
626 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
627 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
628
629 /* SysTick Calibration Register Definitions */
630 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
631 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
632
633 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
634 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
635
636 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
637 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
638
639 /*@} end of group CMSIS_SysTick */
640
641
642 /** \ingroup CMSIS_core_register
643 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
644 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
645 @{
646 */
647
648 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
649 */
650 typedef struct
651 {
652 __O union
653 {
654 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
655 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
656 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
657 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
658 uint32_t RESERVED0[864];
659 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
660 uint32_t RESERVED1[15];
661 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
662 uint32_t RESERVED2[15];
663 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
664 } ITM_Type;
665
666 /* ITM Trace Privilege Register Definitions */
667 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
668 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
669
670 /* ITM Trace Control Register Definitions */
671 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
672 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
673
674 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
675 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
676
677 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
678 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
679
680 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
681 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
682
683 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
684 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
685
686 #define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */
687 #define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */
688
689 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
690 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
691
692 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
693 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
694
695 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
696 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
697
698 /*@}*/ /* end of group CMSIS_ITM */
699
700
701 /** \ingroup CMSIS_core_register
702 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
703 \brief Type definitions for the Data Watchpoint and Trace (DWT)
704 @{
705 */
706
707 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
708 */
709 typedef struct
710 {
711 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
712 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
713 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
714 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
715 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
716 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
717 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
718 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
719 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
720 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
721 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
722 uint32_t RESERVED0[1];
723 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
724 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
725 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
726 uint32_t RESERVED1[1];
727 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
728 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
729 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
730 uint32_t RESERVED2[1];
731 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
732 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
733 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
734 } DWT_Type;
735
736 /* DWT Control Register Definitions */
737 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
738 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
739
740 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
741 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
742
743 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
744 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
745
746 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
747 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
748
749 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
750 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
751
752 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
753 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
754
755 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
756 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
757
758 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
759 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
760
761 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
762 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
763
764 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
765 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
766
767 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
768 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
769
770 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
771 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
772
773 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
774 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
775
776 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
777 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
778
779 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
780 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
781
782 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
783 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
784
785 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
786 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
787
788 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
789 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
790
791 /* DWT CPI Count Register Definitions */
792 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
793 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
794
795 /* DWT Exception Overhead Count Register Definitions */
796 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
797 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
798
799 /* DWT Sleep Count Register Definitions */
800 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
801 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
802
803 /* DWT LSU Count Register Definitions */
804 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
805 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
806
807 /* DWT Folded-instruction Count Register Definitions */
808 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
809 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
810
811 /* DWT Comparator Mask Register Definitions */
812 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
813 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
814
815 /* DWT Comparator Function Register Definitions */
816 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
817 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
818
819 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
820 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
821
822 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
823 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
824
825 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
826 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
827
828 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
829 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
830
831 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
832 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
833
834 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
835 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
836
837 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
838 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
839
840 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
841 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
842
843 /*@}*/ /* end of group CMSIS_DWT */
844
845
846 /** \ingroup CMSIS_core_register
847 \defgroup CMSIS_TPI Trace Port Interface (TPI)
848 \brief Type definitions for the Trace Port Interface (TPI)
849 @{
850 */
851
852 /** \brief Structure type to access the Trace Port Interface Register (TPI).
853 */
854 typedef struct
855 {
856 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
857 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
858 uint32_t RESERVED0[2];
859 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
860 uint32_t RESERVED1[55];
861 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
862 uint32_t RESERVED2[131];
863 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
864 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
865 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
866 uint32_t RESERVED3[759];
867 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
868 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
869 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
870 uint32_t RESERVED4[1];
871 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
872 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
873 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
874 uint32_t RESERVED5[39];
875 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
876 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
877 uint32_t RESERVED7[8];
878 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
879 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
880 } TPI_Type;
881
882 /* TPI Asynchronous Clock Prescaler Register Definitions */
883 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
884 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
885
886 /* TPI Selected Pin Protocol Register Definitions */
887 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
888 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
889
890 /* TPI Formatter and Flush Status Register Definitions */
891 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
892 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
893
894 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
895 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
896
897 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
898 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
899
900 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
901 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
902
903 /* TPI Formatter and Flush Control Register Definitions */
904 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
905 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
906
907 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
908 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
909
910 /* TPI TRIGGER Register Definitions */
911 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
912 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
913
914 /* TPI Integration ETM Data Register Definitions (FIFO0) */
915 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
916 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
917
918 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
919 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
920
921 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
922 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
923
924 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
925 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
926
927 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
928 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
929
930 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
931 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
932
933 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
934 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
935
936 /* TPI ITATBCTR2 Register Definitions */
937 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
938 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
939
940 /* TPI Integration ITM Data Register Definitions (FIFO1) */
941 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
942 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
943
944 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
945 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
946
947 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
948 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
949
950 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
951 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
952
953 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
954 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
955
956 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
957 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
958
959 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
960 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
961
962 /* TPI ITATBCTR0 Register Definitions */
963 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
964 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
965
966 /* TPI Integration Mode Control Register Definitions */
967 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
968 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
969
970 /* TPI DEVID Register Definitions */
971 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
972 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
973
974 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
975 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
976
977 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
978 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
979
980 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
981 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
982
983 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
984 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
985
986 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
987 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
988
989 /* TPI DEVTYPE Register Definitions */
990 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
991 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
992
993 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
994 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
995
996 /*@}*/ /* end of group CMSIS_TPI */
997
998
999 #if (__MPU_PRESENT == 1)
1000 /** \ingroup CMSIS_core_register
1001 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1002 \brief Type definitions for the Memory Protection Unit (MPU)
1003 @{
1004 */
1005
1006 /** \brief Structure type to access the Memory Protection Unit (MPU).
1007 */
1008 typedef struct
1009 {
1010 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1011 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1012 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
1013 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1014 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
1015 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
1016 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
1017 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
1018 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
1019 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
1020 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
1021 } MPU_Type;
1022
1023 /* MPU Type Register */
1024 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
1025 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1026
1027 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
1028 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1029
1030 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
1031 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
1032
1033 /* MPU Control Register */
1034 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
1035 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1036
1037 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
1038 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1039
1040 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
1041 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
1042
1043 /* MPU Region Number Register */
1044 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
1045 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
1046
1047 /* MPU Region Base Address Register */
1048 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
1049 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1050
1051 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
1052 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
1053
1054 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
1055 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
1056
1057 /* MPU Region Attribute and Size Register */
1058 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
1059 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1060
1061 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
1062 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1063
1064 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
1065 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1066
1067 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
1068 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
1069
1070 /*@} end of group CMSIS_MPU */
1071 #endif
1072
1073
1074 #if (__FPU_PRESENT == 1)
1075 /** \ingroup CMSIS_core_register
1076 \defgroup CMSIS_FPU Floating Point Unit (FPU)
1077 \brief Type definitions for the Floating Point Unit (FPU)
1078 @{
1079 */
1080
1081 /** \brief Structure type to access the Floating Point Unit (FPU).
1082 */
1083 typedef struct
1084 {
1085 uint32_t RESERVED0[1];
1086 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
1087 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
1088 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
1089 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
1090 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
1091 } FPU_Type;
1092
1093 /* Floating-Point Context Control Register */
1094 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
1095 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
1096
1097 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
1098 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
1099
1100 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
1101 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
1102
1103 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
1104 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
1105
1106 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
1107 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
1108
1109 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
1110 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
1111
1112 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
1113 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
1114
1115 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
1116 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
1117
1118 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
1119 #define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
1120
1121 /* Floating-Point Context Address Register */
1122 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
1123 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
1124
1125 /* Floating-Point Default Status Control Register */
1126 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
1127 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
1128
1129 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
1130 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
1131
1132 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
1133 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
1134
1135 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
1136 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
1137
1138 /* Media and FP Feature Register 0 */
1139 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
1140 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
1141
1142 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
1143 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
1144
1145 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
1146 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
1147
1148 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
1149 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
1150
1151 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
1152 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
1153
1154 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
1155 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
1156
1157 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
1158 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
1159
1160 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
1161 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
1162
1163 /* Media and FP Feature Register 1 */
1164 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
1165 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
1166
1167 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
1168 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
1169
1170 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
1171 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
1172
1173 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
1174 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
1175
1176 /*@} end of group CMSIS_FPU */
1177 #endif
1178
1179
1180 /** \ingroup CMSIS_core_register
1181 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1182 \brief Type definitions for the Core Debug Registers
1183 @{
1184 */
1185
1186 /** \brief Structure type to access the Core Debug Register (CoreDebug).
1187 */
1188 typedef struct
1189 {
1190 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1191 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1192 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1193 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1194 } CoreDebug_Type;
1195
1196 /* Debug Halting Control and Status Register */
1197 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
1198 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1199
1200 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
1201 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1202
1203 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1204 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1205
1206 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
1207 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1208
1209 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
1210 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1211
1212 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
1213 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1214
1215 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
1216 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1217
1218 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1219 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1220
1221 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
1222 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1223
1224 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
1225 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1226
1227 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
1228 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1229
1230 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1231 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1232
1233 /* Debug Core Register Selector Register */
1234 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
1235 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1236
1237 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
1238 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
1239
1240 /* Debug Exception and Monitor Control Register */
1241 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
1242 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1243
1244 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
1245 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1246
1247 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
1248 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1249
1250 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
1251 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1252
1253 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
1254 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1255
1256 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
1257 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1258
1259 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
1260 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1261
1262 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
1263 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1264
1265 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
1266 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1267
1268 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
1269 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1270
1271 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1272 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1273
1274 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
1275 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1276
1277 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
1278 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1279
1280 /*@} end of group CMSIS_CoreDebug */
1281
1282
1283 /** \ingroup CMSIS_core_register
1284 \defgroup CMSIS_core_base Core Definitions
1285 \brief Definitions for base addresses, unions, and structures.
1286 @{
1287 */
1288
1289 /* Memory mapping of Cortex-M4 Hardware */
1290 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1291 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1292 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1293 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1294 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1295 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1296 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1297 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1298
1299 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1300 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1301 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1302 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1303 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1304 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1305 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1306 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
1307
1308 #if (__MPU_PRESENT == 1)
1309 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1310 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1311 #endif
1312
1313 #if (__FPU_PRESENT == 1)
1314 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
1315 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
1316 #endif
1317
1318 /*@} */
1319
1320
1321
1322 /*******************************************************************************
1323 * Hardware Abstraction Layer
1324 Core Function Interface contains:
1325 - Core NVIC Functions
1326 - Core SysTick Functions
1327 - Core Debug Functions
1328 - Core Register Access Functions
1329 ******************************************************************************/
1330 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1331 */
1332
1333
1334
1335 /* ########################## NVIC functions #################################### */
1336 /** \ingroup CMSIS_Core_FunctionInterface
1337 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1338 \brief Functions that manage interrupts and exceptions via the NVIC.
1339 @{
1340 */
1341
1342 /** \brief Set Priority Grouping
1343
1344 The function sets the priority grouping field using the required unlock sequence.
1345 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1346 Only values from 0..7 are used.
1347 In case of a conflict between priority grouping and available
1348 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1349
1350 \param [in] PriorityGroup Priority grouping field.
1351 */
NVIC_SetPriorityGrouping(uint32_t PriorityGroup)1352 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1353 {
1354 uint32_t reg_value;
1355 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
1356
1357 reg_value = SCB->AIRCR; /* read old register configuration */
1358 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
1359 reg_value = (reg_value |
1360 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1361 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
1362 SCB->AIRCR = reg_value;
1363 }
1364
1365
1366 /** \brief Get Priority Grouping
1367
1368 The function reads the priority grouping field from the NVIC Interrupt Controller.
1369
1370 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1371 */
NVIC_GetPriorityGrouping(void)1372 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1373 {
1374 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
1375 }
1376
1377
1378 /** \brief Enable External Interrupt
1379
1380 The function enables a device-specific interrupt in the NVIC interrupt controller.
1381
1382 \param [in] IRQn External interrupt number. Value cannot be negative.
1383 */
NVIC_EnableIRQ(IRQn_Type IRQn)1384 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1385 {
1386 /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
1387 NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
1388 }
1389
1390
1391 /** \brief Disable External Interrupt
1392
1393 The function disables a device-specific interrupt in the NVIC interrupt controller.
1394
1395 \param [in] IRQn External interrupt number. Value cannot be negative.
1396 */
NVIC_DisableIRQ(IRQn_Type IRQn)1397 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1398 {
1399 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
1400 }
1401
1402
1403 /** \brief Get Pending Interrupt
1404
1405 The function reads the pending register in the NVIC and returns the pending bit
1406 for the specified interrupt.
1407
1408 \param [in] IRQn Interrupt number.
1409
1410 \return 0 Interrupt status is not pending.
1411 \return 1 Interrupt status is pending.
1412 */
NVIC_GetPendingIRQ(IRQn_Type IRQn)1413 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1414 {
1415 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
1416 }
1417
1418
1419 /** \brief Set Pending Interrupt
1420
1421 The function sets the pending bit of an external interrupt.
1422
1423 \param [in] IRQn Interrupt number. Value cannot be negative.
1424 */
NVIC_SetPendingIRQ(IRQn_Type IRQn)1425 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1426 {
1427 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
1428 }
1429
1430
1431 /** \brief Clear Pending Interrupt
1432
1433 The function clears the pending bit of an external interrupt.
1434
1435 \param [in] IRQn External interrupt number. Value cannot be negative.
1436 */
NVIC_ClearPendingIRQ(IRQn_Type IRQn)1437 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1438 {
1439 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
1440 }
1441
1442
1443 /** \brief Get Active Interrupt
1444
1445 The function reads the active register in NVIC and returns the active bit.
1446
1447 \param [in] IRQn Interrupt number.
1448
1449 \return 0 Interrupt status is not active.
1450 \return 1 Interrupt status is active.
1451 */
NVIC_GetActive(IRQn_Type IRQn)1452 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1453 {
1454 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
1455 }
1456
1457
1458 /** \brief Set Interrupt Priority
1459
1460 The function sets the priority of an interrupt.
1461
1462 \note The priority cannot be set for every core interrupt.
1463
1464 \param [in] IRQn Interrupt number.
1465 \param [in] priority Priority to set.
1466 */
NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)1467 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1468 {
1469 if(IRQn < 0) {
1470 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
1471 else {
1472 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
1473 }
1474
1475
1476 /** \brief Get Interrupt Priority
1477
1478 The function reads the priority of an interrupt. The interrupt
1479 number can be positive to specify an external (device specific)
1480 interrupt, or negative to specify an internal (core) interrupt.
1481
1482
1483 \param [in] IRQn Interrupt number.
1484 \return Interrupt Priority. Value is aligned automatically to the implemented
1485 priority bits of the microcontroller.
1486 */
NVIC_GetPriority(IRQn_Type IRQn)1487 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1488 {
1489
1490 if(IRQn < 0) {
1491 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
1492 else {
1493 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
1494 }
1495
1496
1497 /** \brief Encode Priority
1498
1499 The function encodes the priority for an interrupt with the given priority group,
1500 preemptive priority value, and subpriority value.
1501 In case of a conflict between priority grouping and available
1502 priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
1503
1504 \param [in] PriorityGroup Used priority group.
1505 \param [in] PreemptPriority Preemptive priority value (starting from 0).
1506 \param [in] SubPriority Subpriority value (starting from 0).
1507 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1508 */
NVIC_EncodePriority(uint32_t PriorityGroup,uint32_t PreemptPriority,uint32_t SubPriority)1509 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1510 {
1511 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1512 uint32_t PreemptPriorityBits;
1513 uint32_t SubPriorityBits;
1514
1515 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1516 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1517
1518 return (
1519 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
1520 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
1521 );
1522 }
1523
1524
1525 /** \brief Decode Priority
1526
1527 The function decodes an interrupt priority value with a given priority group to
1528 preemptive priority value and subpriority value.
1529 In case of a conflict between priority grouping and available
1530 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
1531
1532 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1533 \param [in] PriorityGroup Used priority group.
1534 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1535 \param [out] pSubPriority Subpriority value (starting from 0).
1536 */
NVIC_DecodePriority(uint32_t Priority,uint32_t PriorityGroup,uint32_t * pPreemptPriority,uint32_t * pSubPriority)1537 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
1538 {
1539 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1540 uint32_t PreemptPriorityBits;
1541 uint32_t SubPriorityBits;
1542
1543 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1544 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1545
1546 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
1547 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
1548 }
1549
1550
1551 /** \brief System Reset
1552
1553 The function initiates a system reset request to reset the MCU.
1554 */
NVIC_SystemReset(void)1555 __STATIC_INLINE void NVIC_SystemReset(void)
1556 {
1557 __DSB(); /* Ensure all outstanding memory accesses included
1558 buffered write are completed before reset */
1559 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1560 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1561 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
1562 __DSB(); /* Ensure completion of memory access */
1563 while(1); /* wait until reset */
1564 }
1565
1566 /*@} end of CMSIS_Core_NVICFunctions */
1567
1568
1569
1570 /* ################################## SysTick function ############################################ */
1571 /** \ingroup CMSIS_Core_FunctionInterface
1572 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1573 \brief Functions that configure the System.
1574 @{
1575 */
1576
1577 #if (__Vendor_SysTickConfig == 0)
1578
1579 /** \brief System Tick Configuration
1580
1581 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
1582 Counter is in free running mode to generate periodic interrupts.
1583
1584 \param [in] ticks Number of ticks between two interrupts.
1585
1586 \return 0 Function succeeded.
1587 \return 1 Function failed.
1588
1589 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1590 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
1591 must contain a vendor-specific implementation of this function.
1592
1593 */
SysTick_Config(uint32_t ticks)1594 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1595 {
1596 if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
1597
1598 SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
1599 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
1600 SysTick->VAL = 0; /* Load the SysTick Counter Value */
1601 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1602 SysTick_CTRL_TICKINT_Msk |
1603 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1604 return (0); /* Function successful */
1605 }
1606
1607 #endif
1608
1609 /*@} end of CMSIS_Core_SysTickFunctions */
1610
1611
1612
1613 /* ##################################### Debug In/Output function ########################################### */
1614 /** \ingroup CMSIS_Core_FunctionInterface
1615 \defgroup CMSIS_core_DebugFunctions ITM Functions
1616 \brief Functions that access the ITM debug interface.
1617 @{
1618 */
1619
1620 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
1621 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
1622
1623
1624 /** \brief ITM Send Character
1625
1626 The function transmits a character via the ITM channel 0, and
1627 \li Just returns when no debugger is connected that has booked the output.
1628 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
1629
1630 \param [in] ch Character to transmit.
1631
1632 \returns Character to transmit.
1633 */
ITM_SendChar(uint32_t ch)1634 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
1635 {
1636 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
1637 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
1638 {
1639 while (ITM->PORT[0].u32 == 0);
1640 ITM->PORT[0].u8 = (uint8_t) ch;
1641 }
1642 return (ch);
1643 }
1644
1645
1646 /** \brief ITM Receive Character
1647
1648 The function inputs a character via the external variable \ref ITM_RxBuffer.
1649
1650 \return Received character.
1651 \return -1 No character pending.
1652 */
ITM_ReceiveChar(void)1653 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
1654 int32_t ch = -1; /* no character available */
1655
1656 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
1657 ch = ITM_RxBuffer;
1658 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1659 }
1660
1661 return (ch);
1662 }
1663
1664
1665 /** \brief ITM Check Character
1666
1667 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
1668
1669 \return 0 No character available.
1670 \return 1 Character available.
1671 */
ITM_CheckChar(void)1672 __STATIC_INLINE int32_t ITM_CheckChar (void) {
1673
1674 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
1675 return (0); /* no character available */
1676 } else {
1677 return (1); /* character available */
1678 }
1679 }
1680
1681 /*@} end of CMSIS_core_DebugFunctions */
1682
1683 #endif /* __CORE_CM4_H_DEPENDANT */
1684
1685 #endif /* __CMSIS_GENERIC */
1686
1687 #ifdef __cplusplus
1688 }
1689 #endif
1690