1 /** 2 ****************************************************************************** 3 * @file stm32H7xx_hal_flash_ex.h 4 * @author MCD Application Team 5 * @brief Header file of FLASH HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32H7xx_HAL_FLASH_EX_H 22 #define STM32H7xx_HAL_FLASH_EX_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32h7xx_hal_def.h" 30 31 /** @addtogroup STM32H7xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup FLASHEx 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup FLASHEx_Exported_Types FLASH Exported Types 41 * @{ 42 */ 43 44 /** 45 * @brief FLASH Erase structure definition 46 */ 47 typedef struct 48 { 49 uint32_t TypeErase; /*!< Mass erase or sector Erase. 50 This parameter can be a value of @ref FLASHEx_Type_Erase */ 51 52 uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled. 53 This parameter must be a value of @ref FLASHEx_Banks */ 54 55 uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled 56 This parameter must be a value of @ref FLASH_Sectors */ 57 58 uint32_t NbSectors; /*!< Number of sectors to be erased. 59 This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/ 60 61 uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism 62 This parameter must be a value of @ref FLASHEx_Voltage_Range */ 63 64 } FLASH_EraseInitTypeDef; 65 66 67 /** 68 * @brief FLASH Option Bytes Program structure definition 69 */ 70 typedef struct 71 { 72 uint32_t OptionType; /*!< Option byte to be configured. 73 This parameter can be a value of @ref FLASHEx_Option_Type */ 74 75 uint32_t WRPState; /*!< Write protection activation or deactivation. 76 This parameter can be a value of @ref FLASHEx_WRP_State */ 77 78 uint32_t WRPSector; /*!< Specifies the sector(s) to be write protected. 79 The value of this parameter depend on device used within the same series */ 80 81 uint32_t RDPLevel; /*!< Set the read protection level. 82 This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ 83 84 uint32_t BORLevel; /*!< Set the BOR Level. 85 This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */ 86 87 uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). 88 This parameter can be a combination of @ref FLASHEx_OB_USER_Type */ 89 90 uint32_t USERConfig; /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY / 91 IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / IO_HSLV / SWAP_BANK_OPT */ 92 93 uint32_t Banks; /*!< Select banks for WRP , PCROP and secure area config . 94 This parameter must be a value of @ref FLASHEx_Banks */ 95 96 uint32_t PCROPConfig; /*!< specifies if the PCROP area shall be erased or not 97 when RDP level decreased from Level 1 to Level 0 or during a mass erase. 98 This parameter must be a value of @ref FLASHEx_OB_PCROP_RDP enumeration */ 99 100 uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP). 101 This parameter must be a value between begin and end of a bank */ 102 103 uint32_t PCROPEndAddr; /*!< PCROP End address (used for OPTIONBYTE_PCROP). 104 This parameter must be a value between PCROP Start address and end of a bank */ 105 106 uint32_t BootConfig; /*!< Specifies if the Boot Address to be configured BOOT_ADD0, BOOT_ADD1 107 or both. This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */ 108 109 uint32_t BootAddr0; /*!< Boot Address 0. 110 This parameter must be a value between begin and end of a bank */ 111 112 uint32_t BootAddr1; /*!< Boot Address 1. 113 This parameter must be a value between begin and end of a bank */ 114 #if defined(DUAL_CORE) 115 uint32_t CM4BootConfig; /*!< specifies if the CM4 boot Address to be configured BOOT_ADD0, BOOT_ADD1 116 or both. 117 This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */ 118 119 uint32_t CM4BootAddr0; /*!< CM4 Boot Address 0. 120 This parameter must be a value between begin and end of a bank */ 121 122 uint32_t CM4BootAddr1; /*!< CM4 Boot Address 1. 123 This parameter must be a value between begin and end of a bank */ 124 #endif /*DUAL_CORE*/ 125 126 uint32_t SecureAreaConfig; /*!< specifies if the bank secured area shall be erased or not 127 when RDP level decreased from Level 1 to Level 0 or during a mass erase. 128 This parameter must be a value of @ref FLASHEx_OB_SECURE_RDP enumeration */ 129 130 uint32_t SecureAreaStartAddr; /*!< Bank Secure area Start address. 131 This parameter must be a value between begin address and end address of bank1 */ 132 133 uint32_t SecureAreaEndAddr; /*!< Bank Secure area End address. 134 This parameter must be a value between Secure Area Start address and end address of a bank1 */ 135 136 } FLASH_OBProgramInitTypeDef; 137 138 /** 139 * @brief FLASH Erase structure definition 140 */ 141 typedef struct 142 { 143 uint32_t TypeCRC; /*!< CRC Selection Type. 144 This parameter can be a value of @ref FLASHEx_CRC_Selection_Type */ 145 146 uint32_t BurstSize; /*!< CRC Burst Size. 147 This parameter can be a value of @ref FLASHEx_CRC_Burst_Size */ 148 149 uint32_t Bank; /*!< Select bank where CRC computation is enabled. 150 This parameter must be FLASH_BANK_1 or FLASH_BANK_2 */ 151 152 uint32_t Sector; /*!< Initial FLASH sector from which starts the CRC computation 153 This parameter must be a value of @ref FLASH_Sectors */ 154 155 uint32_t NbSectors; /*!< Number of sectors to be computed. 156 This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/ 157 158 uint32_t CRCStartAddr; /*!< CRC Start address. 159 This parameter must be a value between begin address and end address of a bank */ 160 161 uint32_t CRCEndAddr; /*!< CRC End address. 162 This parameter must be a value between CRC Start address and end address of a bank */ 163 164 } FLASH_CRCInitTypeDef; 165 166 /** 167 * @} 168 */ 169 /* Exported constants --------------------------------------------------------*/ 170 171 /** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants 172 * @{ 173 */ 174 175 /** @defgroup FLASHEx_Type_Erase FLASH Type Erase 176 * @{ 177 */ 178 #define FLASH_TYPEERASE_SECTORS 0x00U /*!< Sectors erase only */ 179 #define FLASH_TYPEERASE_MASSERASE 0x01U /*!< Flash Mass erase activation */ 180 /** 181 * @} 182 */ 183 184 /** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range 185 * @{ 186 */ 187 #define FLASH_VOLTAGE_RANGE_1 0x00000000U /*!< Flash program/erase by 8 bits */ 188 #define FLASH_VOLTAGE_RANGE_2 FLASH_CR_PSIZE_0 /*!< Flash program/erase by 16 bits */ 189 #define FLASH_VOLTAGE_RANGE_3 FLASH_CR_PSIZE_1 /*!< Flash program/erase by 32 bits */ 190 #define FLASH_VOLTAGE_RANGE_4 FLASH_CR_PSIZE /*!< Flash program/erase by 64 bits */ 191 /** 192 * @} 193 */ 194 195 /** @defgroup FLASHEx_WRP_State FLASH WRP State 196 * @{ 197 */ 198 #define OB_WRPSTATE_DISABLE 0x00000000U /*!< Disable the write protection of the desired bank 1 sectors */ 199 #define OB_WRPSTATE_ENABLE 0x00000001U /*!< Enable the write protection of the desired bank 1 sectors */ 200 /** 201 * @} 202 */ 203 204 /** @defgroup FLASHEx_Option_Type FLASH Option Type 205 * @{ 206 */ 207 #define OPTIONBYTE_WRP 0x01U /*!< WRP option byte configuration */ 208 #define OPTIONBYTE_RDP 0x02U /*!< RDP option byte configuration */ 209 #define OPTIONBYTE_USER 0x04U /*!< USER option byte configuration */ 210 #define OPTIONBYTE_PCROP 0x08U /*!< PCROP option byte configuration */ 211 #define OPTIONBYTE_BOR 0x10U /*!< BOR option byte configuration */ 212 #define OPTIONBYTE_SECURE_AREA 0x20U /*!< secure area option byte configuration */ 213 #if defined(DUAL_CORE) 214 #define OPTIONBYTE_CM7_BOOTADD 0x40U /*!< CM7 BOOT ADD option byte configuration */ 215 #define OPTIONBYTE_CM4_BOOTADD 0x80U /*!< CM4 BOOT ADD option byte configuration */ 216 #define OPTIONBYTE_BOOTADD OPTIONBYTE_CM7_BOOTADD /*!< BOOT ADD option byte configuration */ 217 #else /* Single core*/ 218 #define OPTIONBYTE_BOOTADD 0x40U /*!< BOOT ADD option byte configuration */ 219 #endif /*DUAL_CORE*/ 220 /** 221 * @} 222 */ 223 224 /** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection 225 * @{ 226 */ 227 #define OB_RDP_LEVEL_0 0xAA00U 228 #define OB_RDP_LEVEL_1 0x5500U 229 #define OB_RDP_LEVEL_2 0xCC00U /*!< Warning: When enabling read protection level 2 230 it s no more possible to go back to level 1 or 0 */ 231 /** 232 * @} 233 */ 234 235 /** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog 236 * @{ 237 */ 238 #define OB_WWDG_SW 0x10U /*!< Software WWDG selected */ 239 #define OB_WWDG_HW 0x00U /*!< Hardware WWDG selected */ 240 /** 241 * @} 242 */ 243 244 245 /** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog 246 * @{ 247 */ 248 #define OB_IWDG_SW 0x20U /*!< Software IWDG selected */ 249 #define OB_IWDG_HW 0x00U /*!< Hardware IWDG selected */ 250 /** 251 * @} 252 */ 253 254 /** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP 255 * @{ 256 */ 257 #define OB_STOP_NO_RST 0x40U /*!< No reset generated when entering in STOP */ 258 #define OB_STOP_RST 0x00U /*!< Reset generated when entering in STOP */ 259 /** 260 * @} 261 */ 262 263 /** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY 264 * @{ 265 */ 266 #define OB_STDBY_NO_RST 0x80U /*!< No reset generated when entering in STANDBY */ 267 #define OB_STDBY_RST 0x00U /*!< Reset generated when entering in STANDBY */ 268 /** 269 * @} 270 */ 271 272 /** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP 273 * @{ 274 */ 275 #define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Freeze IWDG counter in STOP mode */ 276 #define OB_IWDG_STOP_ACTIVE FLASH_OPTSR_FZ_IWDG_STOP /*!< IWDG counter active in STOP mode */ 277 /** 278 * @} 279 */ 280 281 /** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY 282 * @{ 283 */ 284 #define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Freeze IWDG counter in STANDBY mode */ 285 #define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY /*!< IWDG counter active in STANDBY mode */ 286 /** 287 * @} 288 */ 289 290 /** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level 291 * @{ 292 */ 293 #define OB_BOR_LEVEL0 0x00000000U /*!< Reset level threshold is set to 1.6V */ 294 #define OB_BOR_LEVEL1 FLASH_OPTSR_BOR_LEV_0 /*!< Reset level threshold is set to 2.1V */ 295 #define OB_BOR_LEVEL2 FLASH_OPTSR_BOR_LEV_1 /*!< Reset level threshold is set to 2.4V */ 296 #define OB_BOR_LEVEL3 (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0) /*!< Reset level threshold is set to 2.7V */ 297 /** 298 * @} 299 */ 300 301 302 303 /** @defgroup FLASHEx_Boot_Address FLASH Boot Address 304 * @{ 305 */ 306 #define OB_BOOTADDR_ITCM_RAM 0x0000U /*!< Boot from ITCM RAM (0x00000000) */ 307 #define OB_BOOTADDR_SYSTEM 0x0040U /*!< Boot from System memory bootloader (0x00100000) */ 308 #define OB_BOOTADDR_ITCM_FLASH 0x0080U /*!< Boot from Flash on ITCM interface (0x00200000) */ 309 #define OB_BOOTADDR_AXIM_FLASH 0x2000U /*!< Boot from Flash on AXIM interface (0x08000000) */ 310 #define OB_BOOTADDR_DTCM_RAM 0x8000U /*!< Boot from DTCM RAM (0x20000000) */ 311 #define OB_BOOTADDR_SRAM1 0x8004U /*!< Boot from SRAM1 (0x20010000) */ 312 #define OB_BOOTADDR_SRAM2 0x8013U /*!< Boot from SRAM2 (0x2004C000) */ 313 /** 314 * @} 315 */ 316 317 /** @defgroup FLASH_Latency FLASH Latency 318 * @{ 319 */ 320 #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero Latency cycle */ 321 #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One Latency cycle */ 322 #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two Latency cycles */ 323 #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three Latency cycles */ 324 #define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four Latency cycles */ 325 #define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five Latency cycles */ 326 #define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six Latency cycles */ 327 #define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven Latency cycles */ 328 #define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight Latency cycle */ 329 #define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine Latency cycle */ 330 #define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten Latency cycles */ 331 #define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven Latency cycles */ 332 #define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve Latency cycles */ 333 #define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen Latency cycles */ 334 #define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen Latency cycles */ 335 #define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */ 336 /** 337 * @} 338 */ 339 340 /** @defgroup FLASHEx_Banks FLASH Banks 341 * @{ 342 */ 343 #define FLASH_BANK_1 0x01U /*!< Bank 1 */ 344 #define FLASH_BANK_2 0x02U /*!< Bank 2 */ 345 #define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */ 346 /** 347 * @} 348 */ 349 350 /** @defgroup FLASHEx_OB_PCROP_RDP FLASHEx OB PCROP RDP 351 * @{ 352 */ 353 #define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level 354 is decreased from Level 1 to Level 0 or during a mass erase */ 355 #define OB_PCROP_RDP_ERASE FLASH_PRAR_DMEP /*!< PCROP area is erased when the RDP level is 356 decreased from Level 1 to Level 0 (full mass erase) */ 357 358 /** 359 * @} 360 */ 361 362 /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection 363 * @{ 364 */ 365 #define OB_WRP_SECTOR_0 0x00000001U /*!< Write protection of Sector0 */ 366 #define OB_WRP_SECTOR_1 0x00000002U /*!< Write protection of Sector1 */ 367 #define OB_WRP_SECTOR_2 0x00000004U /*!< Write protection of Sector2 */ 368 #define OB_WRP_SECTOR_3 0x00000008U /*!< Write protection of Sector3 */ 369 #define OB_WRP_SECTOR_4 0x00000010U /*!< Write protection of Sector4 */ 370 #define OB_WRP_SECTOR_5 0x00000020U /*!< Write protection of Sector5 */ 371 #define OB_WRP_SECTOR_6 0x00000040U /*!< Write protection of Sector6 */ 372 #define OB_WRP_SECTOR_7 0x00000080U /*!< Write protection of Sector7 */ 373 #define OB_WRP_SECTOR_All 0x000000FFU /*!< Write protection of all Sectors */ 374 /** 375 * @} 376 */ 377 378 /** @defgroup FLASHEx_OB_SECURITY FLASHEx OB SECURITY 379 * @{ 380 */ 381 #define OB_SECURITY_DISABLE 0x00000000U /*!< security enabled */ 382 #define OB_SECURITY_ENABLE FLASH_OPTSR_SECURITY /*!< security disabled */ 383 /** 384 * @} 385 */ 386 387 /** @defgroup FLASHEx_OB_ST_RAM_SIZE FLASHEx OB ST RAM SIZE 388 * @{ 389 */ 390 #define OB_ST_RAM_SIZE_2KB 0x00000000U /*!< 2 Kbytes reserved to ST code */ 391 #define OB_ST_RAM_SIZE_4KB FLASH_OPTSR_ST_RAM_SIZE_0 /*!< 4 Kbytes reserved to ST code */ 392 #define OB_ST_RAM_SIZE_8KB FLASH_OPTSR_ST_RAM_SIZE_1 /*!< 8 Kbytes reserved to ST code */ 393 #define OB_ST_RAM_SIZE_16KB FLASH_OPTSR_ST_RAM_SIZE /*!< 16 Kbytes reserved to ST code */ 394 /** 395 * @} 396 */ 397 398 #if defined(DUAL_CORE) 399 /** @defgroup FLASHEx_OB_BCM7 FLASHEx OB BCM7 400 * @{ 401 */ 402 #define OB_BCM7_DISABLE 0x00000000U /*!< CM7 Boot disabled */ 403 #define OB_BCM7_ENABLE FLASH_OPTSR_BCM7 /*!< CM7 Boot enabled */ 404 405 /** 406 * @} 407 */ 408 409 /** @defgroup FLASHEx_OB_BCM4 FLASHEx OB BCM4 410 * @{ 411 */ 412 #define OB_BCM4_DISABLE 0x00000000U /*!< CM4 Boot disabled */ 413 #define OB_BCM4_ENABLE FLASH_OPTSR_BCM4 /*!< CM4 Boot enabled */ 414 /** 415 * @} 416 */ 417 #endif /*DUAL_CORE*/ 418 419 /** @defgroup FLASHEx_OB_IWDG1_SW FLASHEx OB IWDG1 SW 420 * @{ 421 */ 422 #define OB_IWDG1_SW FLASH_OPTSR_IWDG1_SW /*!< Hardware independent watchdog 1 */ 423 #define OB_IWDG1_HW 0x00000000U /*!< Software independent watchdog 1 */ 424 /** 425 * @} 426 */ 427 428 #if defined(DUAL_CORE) 429 /** @defgroup FLASHEx_OB_IWDG2_SW FLASHEx OB IWDG2 SW 430 * @{ 431 */ 432 #define OB_IWDG2_SW FLASH_OPTSR_IWDG2_SW /*!< Hardware independent watchdog 2*/ 433 #define OB_IWDG2_HW 0x00000000U /*!< Software independent watchdog 2*/ 434 /** 435 * @} 436 */ 437 #endif 438 439 /** @defgroup FLASHEx_OB_NRST_STOP_D1 FLASHEx OB NRST STOP D1 440 * @{ 441 */ 442 #define OB_STOP_RST_D1 0x00000000U /*!< Reset generated when entering the D1 to stop mode */ 443 #define OB_STOP_NO_RST_D1 FLASH_OPTSR_NRST_STOP_D1 /*!< No reset generated when entering the D1 to stop mode */ 444 /** 445 * @} 446 */ 447 448 /** @defgroup FLASHEx_OB_NRST_STDBY_D1 FLASHEx OB NRST STDBY D1 449 * @{ 450 */ 451 #define OB_STDBY_RST_D1 0x00000000U /*!< Reset generated when entering the D1 to standby mode */ 452 #define OB_STDBY_NO_RST_D1 FLASH_OPTSR_NRST_STBY_D1 /*!< No reset generated when entering the D1 to standby mode */ 453 /** 454 * @} 455 */ 456 457 #if defined(DUAL_CORE) 458 /** @defgroup FLASHEx_OB_NRST_STOP_D2 FLASHEx OB NRST STOP D2 459 * @{ 460 */ 461 #define OB_STOP_RST_D2 0x00000000U /*!< Reset generated when entering the D2 to stop mode */ 462 #define OB_STOP_NO_RST_D2 FLASH_OPTSR_NRST_STOP_D2 /*!< No reset generated when entering the D2 to stop mode */ 463 /** 464 * @} 465 */ 466 467 /** @defgroup FLASHEx_OB_NRST_STDBY_D2 FLASHEx OB NRST STDBY D2 468 * @{ 469 */ 470 #define OB_STDBY_RST_D2 0x00000000U /*!< Reset generated when entering the D2 to standby mode */ 471 #define OB_STDBY_NO_RST_D2 FLASH_OPTSR_NRST_STBY_D2 /*!< No reset generated when entering the D2 to standby mode */ 472 /** 473 * @} 474 */ 475 #endif 476 477 /** @defgroup FLASHEx_OB_SWAP_BANK FLASHEx OB SWAP BANK 478 * @{ 479 */ 480 #define OB_SWAP_BANK_DISABLE 0x00000000U /*!< Bank swap disabled */ 481 #define OB_SWAP_BANK_ENABLE FLASH_OPTSR_SWAP_BANK_OPT /*!< Bank swap enabled */ 482 /** 483 * @} 484 */ 485 486 /** @defgroup FLASHEx_OB_IOHSLV FLASHEx OB IOHSLV 487 * @{ 488 */ 489 #define OB_IOHSLV_DISABLE 0x00000000U /*!< IOHSLV disabled */ 490 #define OB_IOHSLV_ENABLE FLASH_OPTSR_IO_HSLV /*!< IOHSLV enabled */ 491 /** 492 * @} 493 */ 494 495 /** @defgroup FLASHEx_OB_BOOT_OPTION FLASHEx OB BOOT OPTION 496 * @{ 497 */ 498 #define OB_BOOT_ADD0 0x01U /*!< Select Boot Address 0 */ 499 #define OB_BOOT_ADD1 0x02U /*!< Select Boot Address 1 */ 500 #define OB_BOOT_ADD_BOTH 0x03U /*!< Select Boot Address 0 and 1 */ 501 /** 502 * @} 503 */ 504 505 /** @defgroup FLASHEx_OB_USER_Type FLASHEx OB USER Type 506 * @{ 507 */ 508 #define OB_USER_IWDG1_SW 0x0001U /*!< Independent watchdog selection */ 509 #define OB_USER_NRST_STOP_D1 0x0002U /*!< Reset when entering Stop mode selection*/ 510 #define OB_USER_NRST_STDBY_D1 0x0004U /*!< Reset when entering standby mode selection*/ 511 #define OB_USER_IWDG_STOP 0x0008U /*!< Independent watchdog counter freeze in stop mode */ 512 #define OB_USER_IWDG_STDBY 0x0010U /*!< Independent watchdog counter freeze in standby mode */ 513 #define OB_USER_ST_RAM_SIZE 0x0020U /*!< dedicated DTCM Ram size selection */ 514 #define OB_USER_SECURITY 0x0040U /*!< security selection */ 515 #define OB_USER_IOHSLV 0x0080U /*!< IO HSLV selection */ 516 #define OB_USER_SWAP_BANK 0x0100U /*!< Bank swap selection */ 517 #if defined (DUAL_CORE) 518 #define OB_USER_IWDG2_SW 0x0200U /*!< Window watchdog selection */ 519 #define OB_USER_BCM4 0x0400U /*!< CM4 boot selection */ 520 #define OB_USER_BCM7 0x0800U /*!< CM7 boot selection */ 521 #define OB_USER_NRST_STOP_D2 0x1000U /*!< Reset when entering Stop mode selection*/ 522 #define OB_USER_NRST_STDBY_D2 0x2000U /*!< Reset when entering standby mode selection*/ 523 #endif /*DUAL_CORE*/ 524 525 /** 526 * @} 527 */ 528 529 /** @defgroup FLASHEx_OB_SECURE_RDP FLASHEx OB SECURE RDP 530 * @{ 531 */ 532 #define OB_SECURE_RDP_NOT_ERASE 0x00000000U /*!< Secure area is not erased when the RDP level 533 is decreased from Level 1 to Level 0 or during a mass erase */ 534 #define OB_SECURE_RDP_ERASE FLASH_SCAR_DMES /*!< Secure area is erased when the RDP level is 535 decreased from Level 1 to Level 0 (full mass erase) */ 536 537 /** 538 * @} 539 */ 540 541 /** @defgroup FLASHEx_CRC_Selection_Type FLASH CRC Selection Type 542 * @{ 543 */ 544 #define FLASH_CRC_ADDR 0x00000000U /*!< CRC selection type by address */ 545 #define FLASH_CRC_SECTORS FLASH_CRCCR_CRC_BY_SECT /*!< CRC selection type by sectors */ 546 #define FLASH_CRC_BANK (FLASH_CRCCR_ALL_BANK | FLASH_CRCCR_CRC_BY_SECT) /*!< CRC selection type by bank */ 547 /** 548 * @} 549 */ 550 551 /** @defgroup FLASHEx_CRC_Burst_Size FLASH CRC Burst Size 552 * @{ 553 */ 554 #define FLASH_CRC_BURST_SIZE_4 0x00000000U /*!< Every burst has a size of 4 Flash words (256-bit) */ 555 #define FLASH_CRC_BURST_SIZE_16 FLASH_CRCCR_CRC_BURST_0 /*!< Every burst has a size of 16 Flash words (256-bit) */ 556 #define FLASH_CRC_BURST_SIZE_64 FLASH_CRCCR_CRC_BURST_1 /*!< Every burst has a size of 64 Flash words (256-bit) */ 557 #define FLASH_CRC_BURST_SIZE_256 FLASH_CRCCR_CRC_BURST /*!< Every burst has a size of 256 Flash words (256-bit) */ 558 /** 559 * @} 560 */ 561 562 /** @defgroup FLASHEx_Programming_Delay FLASH Programming Delay 563 * @{ 564 */ 565 #define FLASH_PROGRAMMING_DELAY_0 0x00000000U /*!< programming delay set for Flash running at 70 MHz or below */ 566 #define FLASH_PROGRAMMING_DELAY_1 FLASH_ACR_WRHIGHFREQ_0 /*!< programming delay set for Flash running between 70 MHz and 185 MHz */ 567 #define FLASH_PROGRAMMING_DELAY_2 FLASH_ACR_WRHIGHFREQ_1 /*!< programming delay set for Flash running between 185 MHz and 225 MHz */ 568 #define FLASH_PROGRAMMING_DELAY_3 FLASH_ACR_WRHIGHFREQ /*!< programming delay set for Flash at startup */ 569 /** 570 * @} 571 */ 572 573 /* Exported macro ------------------------------------------------------------*/ 574 /** @defgroup FLASHEx_Exported_Macros FLASH Exported Macros 575 * @{ 576 */ 577 /** 578 * @brief Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1) 579 * @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14]. 580 * @param __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB) 581 * @retval The FLASH Boot Base Adress 582 */ 583 #define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14U) 584 /** 585 * @} 586 */ 587 588 /** 589 * @brief Set the FLASH Program/Erase parallelism. 590 * @param __PSIZE__ FLASH Program/Erase parallelism 591 * This parameter can be a value of @ref FLASH_Program_Parallelism 592 * @param __BANK__: Flash bank (FLASH_BANK_1 or FLASH_BANK_2) 593 * @retval none 594 */ 595 #define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) (((__BANK__) == FLASH_BANK_1) ? \ 596 MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__)) : \ 597 MODIFY_REG(FLASH->CR2, FLASH_CR_PSIZE, (__PSIZE__))) 598 599 /** 600 * @brief Get the FLASH Program/Erase parallelism. 601 * @param __BANK__ Flash bank (FLASH_BANK_1 or FLASH_BANK_2) 602 * @retval FLASH Program/Erase parallelism 603 * This return value can be a value of @ref FLASH_Program_Parallelism 604 */ 605 #define __HAL_FLASH_GET_PSIZE(__BANK__) (((__BANK__) == FLASH_BANK_1) ? \ 606 READ_BIT((FLASH->CR1), FLASH_CR_PSIZE) : \ 607 READ_BIT((FLASH->CR2), FLASH_CR_PSIZE)) 608 609 /** 610 * @brief Set the FLASH Programming Delay. 611 * @param __DELAY__ FLASH Programming Delay 612 * This parameter can be a value of @ref FLASHEx_Programming_Delay 613 * @retval none 614 */ 615 #define __HAL_FLASH_SET_PROGRAM_DELAY(__DELAY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ, (__DELAY__)) 616 617 /** 618 * @brief Get the FLASH Programming Delay. 619 * @retval FLASH Programming Delay 620 * This return value can be a value of @ref FLASHEx_Programming_Delay 621 */ 622 #define __HAL_FLASH_GET_PROGRAM_DELAY() READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ) 623 624 /* Exported functions --------------------------------------------------------*/ 625 /** @addtogroup FLASHEx_Exported_Functions 626 * @{ 627 */ 628 629 /** @addtogroup FLASHEx_Exported_Functions_Group1 630 * @{ 631 */ 632 /* Extension Program operation functions *************************************/ 633 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError); 634 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); 635 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); 636 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); 637 638 HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void); 639 HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void); 640 HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void); 641 HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void); 642 643 HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result); 644 645 /** 646 * @} 647 */ 648 649 /** 650 * @} 651 */ 652 /* Private types -------------------------------------------------------------*/ 653 /* Private variables ---------------------------------------------------------*/ 654 /* Private constants ---------------------------------------------------------*/ 655 /* Private macros ------------------------------------------------------------*/ 656 /** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros 657 * @{ 658 */ 659 660 /** @defgroup FLASHEx_IS_FLASH_Definitions FLASHEx Private macros to check input parameters 661 * @{ 662 */ 663 664 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_SECTORS) || \ 665 ((VALUE) == FLASH_TYPEERASE_MASSERASE)) 666 667 #define IS_VOLTAGERANGE(RANGE) (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \ 668 ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \ 669 ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \ 670 ((RANGE) == FLASH_VOLTAGE_RANGE_4)) 671 672 #define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || \ 673 ((VALUE) == OB_WRPSTATE_ENABLE)) 674 #if defined(DUAL_CORE) 675 #define IS_OPTIONBYTE(VALUE) (((VALUE) <= 0x3FFFU) && ((VALUE) != 0U)) 676 #else 677 #define IS_OPTIONBYTE(VALUE) (((VALUE) <= 0x01FFU) && ((VALUE) != 0U)) 678 #endif /*DUAL_CORE*/ 679 680 #define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013U) 681 682 #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ 683 ((LEVEL) == OB_RDP_LEVEL_1) ||\ 684 ((LEVEL) == OB_RDP_LEVEL_2)) 685 686 #define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW)) 687 688 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW)) 689 690 #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST)) 691 692 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST)) 693 694 #define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE)) 695 696 #define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE)) 697 698 #define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL0) || ((LEVEL) == OB_BOR_LEVEL1) || \ 699 ((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3)) 700 701 #define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \ 702 ((LATENCY) == FLASH_LATENCY_1) || \ 703 ((LATENCY) == FLASH_LATENCY_2) || \ 704 ((LATENCY) == FLASH_LATENCY_3) || \ 705 ((LATENCY) == FLASH_LATENCY_4) || \ 706 ((LATENCY) == FLASH_LATENCY_5) || \ 707 ((LATENCY) == FLASH_LATENCY_6) || \ 708 ((LATENCY) == FLASH_LATENCY_7) || \ 709 ((LATENCY) == FLASH_LATENCY_8) || \ 710 ((LATENCY) == FLASH_LATENCY_9) || \ 711 ((LATENCY) == FLASH_LATENCY_10) || \ 712 ((LATENCY) == FLASH_LATENCY_11) || \ 713 ((LATENCY) == FLASH_LATENCY_12) || \ 714 ((LATENCY) == FLASH_LATENCY_13) || \ 715 ((LATENCY) == FLASH_LATENCY_14) || \ 716 ((LATENCY) == FLASH_LATENCY_15)) 717 718 #define IS_FLASH_SECTOR(SECTOR) ((SECTOR) < FLASH_SECTOR_TOTAL) 719 720 #define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U)) 721 722 #define IS_OB_PCROP_RDP(CONFIG) (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \ 723 ((CONFIG) == OB_PCROP_RDP_ERASE)) 724 725 #define IS_OB_SECURE_RDP(CONFIG) (((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \ 726 ((CONFIG) == OB_SECURE_RDP_ERASE)) 727 728 #define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE)) 729 730 #define IS_OB_USER_IOHSLV(VALUE) (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE)) 731 732 #define IS_OB_IWDG1_SOURCE(SOURCE) (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW)) 733 #if defined(DUAL_CORE) 734 #define IS_OB_IWDG2_SOURCE(SOURCE) (((SOURCE) == OB_IWDG2_SW) || ((SOURCE) == OB_IWDG2_HW)) 735 #endif /*DUAL_CORE*/ 736 #define IS_OB_STOP_D1_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1)) 737 738 #define IS_OB_STDBY_D1_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1)) 739 740 #define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE)) 741 742 #define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE)) 743 744 #define IS_OB_USER_ST_RAM_SIZE(VALUE) (((VALUE) == OB_ST_RAM_SIZE_2KB) || ((VALUE) == OB_ST_RAM_SIZE_4KB) || \ 745 ((VALUE) == OB_ST_RAM_SIZE_8KB) || ((VALUE) == OB_ST_RAM_SIZE_16KB)) 746 747 #define IS_OB_USER_SECURITY(VALUE) (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE)) 748 749 #if defined(DUAL_CORE) 750 #define IS_OB_USER_BCM4(VALUE) (((VALUE) == OB_BCM4_DISABLE) || ((VALUE) == OB_BCM4_ENABLE)) 751 752 #define IS_OB_USER_BCM7(VALUE) (((VALUE) == OB_BCM7_DISABLE) || ((VALUE) == OB_BCM7_ENABLE)) 753 754 #define IS_OB_STOP_D2_RESET(VALUE) (((VALUE) == OB_STOP_NO_RST_D2) || ((VALUE) == OB_STOP_RST_D2)) 755 756 #define IS_OB_STDBY_D2_RESET(VALUE) (((VALUE) == OB_STDBY_NO_RST_D2) || ((VALUE) == OB_STDBY_RST_D2)) 757 #endif /*DUAL_CORE*/ 758 #if defined(DUAL_CORE) 759 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x3FFFU) && ((TYPE) != 0U)) 760 #else 761 #define IS_OB_USER_TYPE(TYPE) (((TYPE) <= (uint32_t)0x73FU) && ((TYPE) != 0U)) 762 #endif 763 764 #define IS_OB_BOOT_ADD_OPTION(VALUE) (((VALUE) == OB_BOOT_ADD0) || \ 765 ((VALUE) == OB_BOOT_ADD1) || \ 766 ((VALUE) == OB_BOOT_ADD_BOTH)) 767 768 #define IS_FLASH_TYPECRC(VALUE) (((VALUE) == FLASH_CRC_ADDR) || \ 769 ((VALUE) == FLASH_CRC_SECTORS) || \ 770 ((VALUE) == FLASH_CRC_BANK)) 771 /** 772 * @} 773 */ 774 775 /** 776 * @} 777 */ 778 779 /* Private functions ---------------------------------------------------------*/ 780 /** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions 781 * @{ 782 */ 783 void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange); 784 /** 785 * @} 786 */ 787 788 /** 789 * @} 790 */ 791 792 /** 793 * @} 794 */ 795 796 /** 797 * @} 798 */ 799 800 #ifdef __cplusplus 801 } 802 #endif 803 804 #endif /* STM32H7xx_HAL_FLASH_EX_H */ 805 806 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 807