1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_dmamux.h
4 * @author MCD Application Team
5 * @brief Header file of DMAMUX LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_LL_DMAMUX_H
22 #define STM32H7xx_LL_DMAMUX_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx.h"
30
31 /** @addtogroup STM32H7xx_LL_Driver
32 * @{
33 */
34
35 #if defined (DMAMUX1) || defined (DMAMUX2)
36
37 /** @defgroup DMAMUX_LL DMAMUX
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants
45 * @{
46 */
47 /* Define used to get DMAMUX CCR register size */
48 #define DMAMUX_CCR_SIZE 0x00000004U
49
50 /* Define used to get DMAMUX RGCR register size */
51 #define DMAMUX_RGCR_SIZE 0x00000004U
52
53 /* Define used to get DMAMUX RequestGenerator offset */
54 #define DMAMUX_REQ_GEN_OFFSET (DMAMUX1_RequestGenerator0_BASE - DMAMUX1_BASE)
55 /* Define used to get DMAMUX Channel Status offset */
56 #define DMAMUX_CH_STATUS_OFFSET (DMAMUX1_ChannelStatus_BASE - DMAMUX1_BASE)
57 /* Define used to get DMAMUX RequestGenerator status offset */
58 #define DMAMUX_REQ_GEN_STATUS_OFFSET (DMAMUX1_RequestGenStatus_BASE - DMAMUX1_BASE)
59
60 /**
61 * @}
62 */
63
64 /* Private macros ------------------------------------------------------------*/
65 /* Exported types ------------------------------------------------------------*/
66 /* Exported constants --------------------------------------------------------*/
67 /** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants
68 * @{
69 */
70 /** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines
71 * @brief Flags defines which can be used with LL_DMAMUX_WriteReg function
72 * @{
73 */
74 #define LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0 /*!< Synchronization Event Overrun Flag Channel 0 */
75 #define LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1 /*!< Synchronization Event Overrun Flag Channel 1 */
76 #define LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2 /*!< Synchronization Event Overrun Flag Channel 2 */
77 #define LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3 /*!< Synchronization Event Overrun Flag Channel 3 */
78 #define LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4 /*!< Synchronization Event Overrun Flag Channel 4 */
79 #define LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5 /*!< Synchronization Event Overrun Flag Channel 5 */
80 #define LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6 /*!< Synchronization Event Overrun Flag Channel 6 */
81 #define LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7 /*!< Synchronization Event Overrun Flag Channel 7 */
82 #define LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8 /*!< Synchronization Event Overrun Flag Channel 8 */
83 #define LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9 /*!< Synchronization Event Overrun Flag Channel 9 */
84 #define LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10 /*!< Synchronization Event Overrun Flag Channel 10 */
85 #define LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11 /*!< Synchronization Event Overrun Flag Channel 11 */
86 #define LL_DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12 /*!< Synchronization Event Overrun Flag Channel 12 */
87 #define LL_DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13 /*!< Synchronization Event Overrun Flag Channel 13 */
88 #define LL_DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14 /*!< Synchronization Event Overrun Flag Channel 14 */
89 #define LL_DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15 /*!< Synchronization Event Overrun Flag Channel 15 */
90 #define LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0 /*!< Request Generator 0 Trigger Event Overrun Flag */
91 #define LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1 /*!< Request Generator 1 Trigger Event Overrun Flag */
92 #define LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2 /*!< Request Generator 2 Trigger Event Overrun Flag */
93 #define LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3 /*!< Request Generator 3 Trigger Event Overrun Flag */
94 #define LL_DMAMUX_RGCFR_RGCOF4 DMAMUX_RGCFR_COF4 /*!< Request Generator 4 Trigger Event Overrun Flag */
95 #define LL_DMAMUX_RGCFR_RGCOF5 DMAMUX_RGCFR_COF5 /*!< Request Generator 5 Trigger Event Overrun Flag */
96 #define LL_DMAMUX_RGCFR_RGCOF6 DMAMUX_RGCFR_COF6 /*!< Request Generator 6 Trigger Event Overrun Flag */
97 #define LL_DMAMUX_RGCFR_RGCOF7 DMAMUX_RGCFR_COF7 /*!< Request Generator 7 Trigger Event Overrun Flag */
98 /**
99 * @}
100 */
101
102 /** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines
103 * @brief Flags defines which can be used with LL_DMAMUX_ReadReg function
104 * @{
105 */
106 #define LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0 /*!< Synchronization Event Overrun Flag Channel 0 */
107 #define LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1 /*!< Synchronization Event Overrun Flag Channel 1 */
108 #define LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2 /*!< Synchronization Event Overrun Flag Channel 2 */
109 #define LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3 /*!< Synchronization Event Overrun Flag Channel 3 */
110 #define LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4 /*!< Synchronization Event Overrun Flag Channel 4 */
111 #define LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5 /*!< Synchronization Event Overrun Flag Channel 5 */
112 #define LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6 /*!< Synchronization Event Overrun Flag Channel 6 */
113 #define LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7 /*!< Synchronization Event Overrun Flag Channel 7 */
114 #define LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8 /*!< Synchronization Event Overrun Flag Channel 8 */
115 #define LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9 /*!< Synchronization Event Overrun Flag Channel 9 */
116 #define LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10 /*!< Synchronization Event Overrun Flag Channel 10 */
117 #define LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11 /*!< Synchronization Event Overrun Flag Channel 11 */
118 #define LL_DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12 /*!< Synchronization Event Overrun Flag Channel 12 */
119 #define LL_DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13 /*!< Synchronization Event Overrun Flag Channel 13 */
120 #define LL_DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14 /*!< Synchronization Event Overrun Flag Channel 14 */
121 #define LL_DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15 /*!< Synchronization Event Overrun Flag Channel 15 */
122 #define LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0 /*!< Request Generator 0 Trigger Event Overrun Flag */
123 #define LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1 /*!< Request Generator 1 Trigger Event Overrun Flag */
124 #define LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2 /*!< Request Generator 2 Trigger Event Overrun Flag */
125 #define LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3 /*!< Request Generator 3 Trigger Event Overrun Flag */
126 #define LL_DMAMUX_RGSR_RGOF4 DMAMUX_RGSR_OF4 /*!< Request Generator 4 Trigger Event Overrun Flag */
127 #define LL_DMAMUX_RGSR_RGOF5 DMAMUX_RGSR_OF5 /*!< Request Generator 5 Trigger Event Overrun Flag */
128 #define LL_DMAMUX_RGSR_RGOF6 DMAMUX_RGSR_OF6 /*!< Request Generator 6 Trigger Event Overrun Flag */
129 #define LL_DMAMUX_RGSR_RGOF7 DMAMUX_RGSR_OF7 /*!< Request Generator 7 Trigger Event Overrun Flag */
130 /**
131 * @}
132 */
133
134 /** @defgroup DMAMUX_LL_EC_IT IT Defines
135 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions
136 * @{
137 */
138 #define LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE /*!< Synchronization Event Overrun Interrupt */
139 #define LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE /*!< Request Generation Trigger Event Overrun Interrupt */
140 /**
141 * @}
142 */
143
144 /** @defgroup DMAMUX_Request_selection DMAMUX Request selection
145 * @brief DMA Request selection
146 * @{
147 */
148 /* D2 Domain : DMAMUX1 requests */
149 #define LL_DMAMUX1_REQ_MEM2MEM 0U /*!< memory to memory transfer */
150 #define LL_DMAMUX1_REQ_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */
151 #define LL_DMAMUX1_REQ_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */
152 #define LL_DMAMUX1_REQ_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */
153 #define LL_DMAMUX1_REQ_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */
154 #define LL_DMAMUX1_REQ_GENERATOR4 5U /*!< DMAMUX1 request generator 4 */
155 #define LL_DMAMUX1_REQ_GENERATOR5 6U /*!< DMAMUX1 request generator 5 */
156 #define LL_DMAMUX1_REQ_GENERATOR6 7U /*!< DMAMUX1 request generator 6 */
157 #define LL_DMAMUX1_REQ_GENERATOR7 8U /*!< DMAMUX1 request generator 7 */
158 #define LL_DMAMUX1_REQ_ADC1 9U /*!< DMAMUX1 ADC1 request */
159 #define LL_DMAMUX1_REQ_ADC2 10U /*!< DMAMUX1 ADC2 request */
160 #define LL_DMAMUX1_REQ_TIM1_CH1 11U /*!< DMAMUX1 TIM1 CH1 request */
161 #define LL_DMAMUX1_REQ_TIM1_CH2 12U /*!< DMAMUX1 TIM1 CH2 request */
162 #define LL_DMAMUX1_REQ_TIM1_CH3 13U /*!< DMAMUX1 TIM1 CH3 request */
163 #define LL_DMAMUX1_REQ_TIM1_CH4 14U /*!< DMAMUX1 TIM1 CH4 request */
164 #define LL_DMAMUX1_REQ_TIM1_UP 15U /*!< DMAMUX1 TIM1 UP request */
165 #define LL_DMAMUX1_REQ_TIM1_TRIG 16U /*!< DMAMUX1 TIM1 TRIG request */
166 #define LL_DMAMUX1_REQ_TIM1_COM 17U /*!< DMAMUX1 TIM1 COM request */
167 #define LL_DMAMUX1_REQ_TIM2_CH1 18U /*!< DMAMUX1 TIM2 CH1 request */
168 #define LL_DMAMUX1_REQ_TIM2_CH2 19U /*!< DMAMUX1 TIM2 CH2 request */
169 #define LL_DMAMUX1_REQ_TIM2_CH3 20U /*!< DMAMUX1 TIM2 CH3 request */
170 #define LL_DMAMUX1_REQ_TIM2_CH4 21U /*!< DMAMUX1 TIM2 CH4 request */
171 #define LL_DMAMUX1_REQ_TIM2_UP 22U /*!< DMAMUX1 TIM2 UP request */
172 #define LL_DMAMUX1_REQ_TIM3_CH1 23U /*!< DMAMUX1 TIM3 CH1 request */
173 #define LL_DMAMUX1_REQ_TIM3_CH2 24U /*!< DMAMUX1 TIM3 CH2 request */
174 #define LL_DMAMUX1_REQ_TIM3_CH3 25U /*!< DMAMUX1 TIM3 CH3 request */
175 #define LL_DMAMUX1_REQ_TIM3_CH4 26U /*!< DMAMUX1 TIM3 CH4 request */
176 #define LL_DMAMUX1_REQ_TIM3_UP 27U /*!< DMAMUX1 TIM3 UP request */
177 #define LL_DMAMUX1_REQ_TIM3_TRIG 28U /*!< DMAMUX1 TIM3 TRIG request */
178 #define LL_DMAMUX1_REQ_TIM4_CH1 29U /*!< DMAMUX1 TIM4 CH1 request */
179 #define LL_DMAMUX1_REQ_TIM4_CH2 30U /*!< DMAMUX1 TIM4 CH2 request */
180 #define LL_DMAMUX1_REQ_TIM4_CH3 31U /*!< DMAMUX1 TIM4 CH3 request */
181 #define LL_DMAMUX1_REQ_TIM4_UP 32U /*!< DMAMUX1 TIM4 UP request */
182 #define LL_DMAMUX1_REQ_I2C1_RX 33U /*!< DMAMUX1 I2C1 RX request */
183 #define LL_DMAMUX1_REQ_I2C1_TX 34U /*!< DMAMUX1 I2C1 TX request */
184 #define LL_DMAMUX1_REQ_I2C2_RX 35U /*!< DMAMUX1 I2C2 RX request */
185 #define LL_DMAMUX1_REQ_I2C2_TX 36U /*!< DMAMUX1 I2C2 TX request */
186 #define LL_DMAMUX1_REQ_SPI1_RX 37U /*!< DMAMUX1 SPI1 RX request */
187 #define LL_DMAMUX1_REQ_SPI1_TX 38U /*!< DMAMUX1 SPI1 TX request */
188 #define LL_DMAMUX1_REQ_SPI2_RX 39U /*!< DMAMUX1 SPI2 RX request */
189 #define LL_DMAMUX1_REQ_SPI2_TX 40U /*!< DMAMUX1 SPI2 TX request */
190 #define LL_DMAMUX1_REQ_USART1_RX 41U /*!< DMAMUX1 USART1 RX request */
191 #define LL_DMAMUX1_REQ_USART1_TX 42U /*!< DMAMUX1 USART1 TX request */
192 #define LL_DMAMUX1_REQ_USART2_RX 43U /*!< DMAMUX1 USART2 RX request */
193 #define LL_DMAMUX1_REQ_USART2_TX 44U /*!< DMAMUX1 USART2 TX request */
194 #define LL_DMAMUX1_REQ_USART3_RX 45U /*!< DMAMUX1 USART3 RX request */
195 #define LL_DMAMUX1_REQ_USART3_TX 46U /*!< DMAMUX1 USART3 TX request */
196 #define LL_DMAMUX1_REQ_TIM8_CH1 47U /*!< DMAMUX1 TIM8 CH1 request */
197 #define LL_DMAMUX1_REQ_TIM8_CH2 48U /*!< DMAMUX1 TIM8 CH2 request */
198 #define LL_DMAMUX1_REQ_TIM8_CH3 49U /*!< DMAMUX1 TIM8 CH3 request */
199 #define LL_DMAMUX1_REQ_TIM8_CH4 50U /*!< DMAMUX1 TIM8 CH4 request */
200 #define LL_DMAMUX1_REQ_TIM8_UP 51U /*!< DMAMUX1 TIM8 UP request */
201 #define LL_DMAMUX1_REQ_TIM8_TRIG 52U /*!< DMAMUX1 TIM8 TRIG request */
202 #define LL_DMAMUX1_REQ_TIM8_COM 53U /*!< DMAMUX1 TIM8 COM request */
203 #define LL_DMAMUX1_REQ_TIM5_CH1 55U /*!< DMAMUX1 TIM5 CH1 request */
204 #define LL_DMAMUX1_REQ_TIM5_CH2 56U /*!< DMAMUX1 TIM5 CH2 request */
205 #define LL_DMAMUX1_REQ_TIM5_CH3 57U /*!< DMAMUX1 TIM5 CH3 request */
206 #define LL_DMAMUX1_REQ_TIM5_CH4 58U /*!< DMAMUX1 TIM5 CH4 request */
207 #define LL_DMAMUX1_REQ_TIM5_UP 59U /*!< DMAMUX1 TIM5 UP request */
208 #define LL_DMAMUX1_REQ_TIM5_TRIG 60U /*!< DMAMUX1 TIM5 TRIG request */
209 #define LL_DMAMUX1_REQ_SPI3_RX 61U /*!< DMAMUX1 SPI3 RX request */
210 #define LL_DMAMUX1_REQ_SPI3_TX 62U /*!< DMAMUX1 SPI3 TX request */
211 #define LL_DMAMUX1_REQ_UART4_RX 63U /*!< DMAMUX1 UART4 RX request */
212 #define LL_DMAMUX1_REQ_UART4_TX 64U /*!< DMAMUX1 UART4 TX request */
213 #define LL_DMAMUX1_REQ_UART5_RX 65U /*!< DMAMUX1 UART5 RX request */
214 #define LL_DMAMUX1_REQ_UART5_TX 66U /*!< DMAMUX1 UART5 TX request */
215 #define LL_DMAMUX1_REQ_DAC1_CH1 67U /*!< DMAMUX1 DAC1 Channel 1 request */
216 #define LL_DMAMUX1_REQ_DAC1_CH2 68U /*!< DMAMUX1 DAC1 Channel 2 request */
217 #define LL_DMAMUX1_REQ_TIM6_UP 69U /*!< DMAMUX1 TIM6 UP request */
218 #define LL_DMAMUX1_REQ_TIM7_UP 70U /*!< DMAMUX1 TIM7 UP request */
219 #define LL_DMAMUX1_REQ_USART6_RX 71U /*!< DMAMUX1 USART6 RX request */
220 #define LL_DMAMUX1_REQ_USART6_TX 72U /*!< DMAMUX1 USART6 TX request */
221 #define LL_DMAMUX1_REQ_I2C3_RX 73U /*!< DMAMUX1 I2C3 RX request */
222 #define LL_DMAMUX1_REQ_I2C3_TX 74U /*!< DMAMUX1 I2C3 TX request */
223 #define LL_DMAMUX1_REQ_DCMI 75U /*!< DMAMUX1 DCMI request */
224 #define LL_DMAMUX1_REQ_CRYP_IN 76U /*!< DMAMUX1 CRYP IN request */
225 #define LL_DMAMUX1_REQ_CRYP_OUT 77U /*!< DMAMUX1 CRYP OUT request */
226 #define LL_DMAMUX1_REQ_HASH_IN 78U /*!< DMAMUX1 HASH IN request */
227 #define LL_DMAMUX1_REQ_UART7_RX 79U /*!< DMAMUX1 UART7 RX request */
228 #define LL_DMAMUX1_REQ_UART7_TX 80U /*!< DMAMUX1 UART7 TX request */
229 #define LL_DMAMUX1_REQ_UART8_RX 81U /*!< DMAMUX1 UART8 RX request */
230 #define LL_DMAMUX1_REQ_UART8_TX 82U /*!< DMAMUX1 UART8 TX request */
231 #define LL_DMAMUX1_REQ_SPI4_RX 83U /*!< DMAMUX1 SPI4 RX request */
232 #define LL_DMAMUX1_REQ_SPI4_TX 84U /*!< DMAMUX1 SPI4 TX request */
233 #define LL_DMAMUX1_REQ_SPI5_RX 85U /*!< DMAMUX1 SPI5 RX request */
234 #define LL_DMAMUX1_REQ_SPI5_TX 86U /*!< DMAMUX1 SPI5 TX request */
235 #define LL_DMAMUX1_REQ_SAI1_A 87U /*!< DMAMUX1 SAI1 A request */
236 #define LL_DMAMUX1_REQ_SAI1_B 88U /*!< DMAMUX1 SAI1 B request */
237 #define LL_DMAMUX1_REQ_SAI2_A 89U /*!< DMAMUX1 SAI2 A request */
238 #define LL_DMAMUX1_REQ_SAI2_B 90U /*!< DMAMUX1 SAI2 B request */
239 #define LL_DMAMUX1_REQ_SWPMI_RX 91U /*!< DMAMUX1 SWPMI RX request */
240 #define LL_DMAMUX1_REQ_SWPMI_TX 92U /*!< DMAMUX1 SWPMI TX request */
241 #define LL_DMAMUX1_REQ_SPDIF_RX_DT 93U /*!< DMAMUX1 SPDIF RXDT request*/
242 #define LL_DMAMUX1_REQ_SPDIF_RX_CS 94U /*!< DMAMUX1 SPDIF RXCS request*/
243 #define LL_DMAMUX1_REQ_HRTIM_MASTER 95U /*!< DMAMUX1 HRTIM1 Master request 1 */
244 #define LL_DMAMUX1_REQ_HRTIM_TIMER_A 96U /*!< DMAMUX1 HRTIM1 TimerA request 2 */
245 #define LL_DMAMUX1_REQ_HRTIM_TIMER_B 97U /*!< DMAMUX1 HRTIM1 TimerB request 3 */
246 #define LL_DMAMUX1_REQ_HRTIM_TIMER_C 98U /*!< DMAMUX1 HRTIM1 TimerC request 4 */
247 #define LL_DMAMUX1_REQ_HRTIM_TIMER_D 99U /*!< DMAMUX1 HRTIM1 TimerD request 5 */
248 #define LL_DMAMUX1_REQ_HRTIM_TIMER_E 100U /*!< DMAMUX1 HRTIM1 TimerE request 6 */
249 #define LL_DMAMUX1_REQ_DFSDM1_FLT0 101U /*!< DMAMUX1 DFSDM Filter0 request */
250 #define LL_DMAMUX1_REQ_DFSDM1_FLT1 102U /*!< DMAMUX1 DFSDM Filter1 request */
251 #define LL_DMAMUX1_REQ_DFSDM1_FLT2 103U /*!< DMAMUX1 DFSDM Filter2 request */
252 #define LL_DMAMUX1_REQ_DFSDM1_FLT3 104U /*!< DMAMUX1 DFSDM Filter3 request */
253 #define LL_DMAMUX1_REQ_TIM15_CH1 105U /*!< DMAMUX1 TIM15 CH1 request */
254 #define LL_DMAMUX1_REQ_TIM15_UP 106U /*!< DMAMUX1 TIM15 UP request */
255 #define LL_DMAMUX1_REQ_TIM15_TRIG 107U /*!< DMAMUX1 TIM15 TRIG request */
256 #define LL_DMAMUX1_REQ_TIM15_COM 108U /*!< DMAMUX1 TIM15 COM request */
257 #define LL_DMAMUX1_REQ_TIM16_CH1 109U /*!< DMAMUX1 TIM16 CH1 request */
258 #define LL_DMAMUX1_REQ_TIM16_UP 110U /*!< DMAMUX1 TIM16 UP request */
259 #define LL_DMAMUX1_REQ_TIM17_CH1 111U /*!< DMAMUX1 TIM17 CH1 request */
260 #define LL_DMAMUX1_REQ_TIM17_UP 112U /*!< DMAMUX1 TIM17 UP request */
261 #define LL_DMAMUX1_REQ_SAI3_A 113U /*!< DMAMUX1 SAI3 A request */
262 #define LL_DMAMUX1_REQ_SAI3_B 114U /*!< DMAMUX1 SAI3 B request */
263 #define LL_DMAMUX1_REQ_ADC3 115U /*!< DMAMUX1 ADC3 request */
264 /* D3 Domain : DMAMUX2 requests */
265 #define LL_DMAMUX2_REQ_MEM2MEM 0U /*!< memory to memory transfer */
266 #define LL_DMAMUX2_REQ_GENERATOR0 1U /*!< DMAMUX2 request generator 0 */
267 #define LL_DMAMUX2_REQ_GENERATOR1 2U /*!< DMAMUX2 request generator 1 */
268 #define LL_DMAMUX2_REQ_GENERATOR2 3U /*!< DMAMUX2 request generator 2 */
269 #define LL_DMAMUX2_REQ_GENERATOR3 4U /*!< DMAMUX2 request generator 3 */
270 #define LL_DMAMUX2_REQ_GENERATOR4 5U /*!< DMAMUX2 request generator 4 */
271 #define LL_DMAMUX2_REQ_GENERATOR5 6U /*!< DMAMUX2 request generator 5 */
272 #define LL_DMAMUX2_REQ_GENERATOR6 7U /*!< DMAMUX2 request generator 6 */
273 #define LL_DMAMUX2_REQ_GENERATOR7 8U /*!< DMAMUX2 request generator 7 */
274 #define LL_DMAMUX2_REQ_LPUART1_RX 9U /*!< DMAMUX2 LP_UART1_RX request */
275 #define LL_DMAMUX2_REQ_LPUART1_TX 10U /*!< DMAMUX2 LP_UART1_TX request */
276 #define LL_DMAMUX2_REQ_SPI6_RX 11U /*!< DMAMUX2 SPI6 RX request */
277 #define LL_DMAMUX2_REQ_SPI6_TX 12U /*!< DMAMUX2 SPI6 TX request */
278 #define LL_DMAMUX2_REQ_I2C4_RX 13U /*!< DMAMUX2 I2C4 RX request */
279 #define LL_DMAMUX2_REQ_I2C4_TX 14U /*!< DMAMUX2 I2C4 TX request */
280 #define LL_DMAMUX2_REQ_SAI4_A 15U /*!< DMAMUX2 SAI4 A request */
281 #define LL_DMAMUX2_REQ_SAI4_B 16U /*!< DMAMUX2 SAI4 B request */
282 #define LL_DMAMUX2_REQ_ADC3 17U /*!< DMAMUX2 ADC3 request */
283 /**
284 * @}
285 */
286
287
288 /** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel
289 * @{
290 */
291 #define LL_DMAMUX_CHANNEL_0 0x00000000U /*!< DMAMUX1 Channel 0 connected to DMA1 Channel 0 , DMAMUX2 Channel 0 connected to BDMA Channel 0 */
292 #define LL_DMAMUX_CHANNEL_1 0x00000001U /*!< DMAMUX1 Channel 1 connected to DMA1 Channel 1 , DMAMUX2 Channel 1 connected to BDMA Channel 1 */
293 #define LL_DMAMUX_CHANNEL_2 0x00000002U /*!< DMAMUX1 Channel 2 connected to DMA1 Channel 2 , DMAMUX2 Channel 2 connected to BDMA Channel 2 */
294 #define LL_DMAMUX_CHANNEL_3 0x00000003U /*!< DMAMUX1 Channel 3 connected to DMA1 Channel 3 , DMAMUX2 Channel 3 connected to BDMA Channel 3 */
295 #define LL_DMAMUX_CHANNEL_4 0x00000004U /*!< DMAMUX1 Channel 4 connected to DMA1 Channel 4 , DMAMUX2 Channel 4 connected to BDMA Channel 4 */
296 #define LL_DMAMUX_CHANNEL_5 0x00000005U /*!< DMAMUX1 Channel 5 connected to DMA1 Channel 5 , DMAMUX2 Channel 5 connected to BDMA Channel 5 */
297 #define LL_DMAMUX_CHANNEL_6 0x00000006U /*!< DMAMUX1 Channel 6 connected to DMA1 Channel 6 , DMAMUX2 Channel 6 connected to BDMA Channel 6 */
298 #define LL_DMAMUX_CHANNEL_7 0x00000007U /*!< DMAMUX1 Channel 7 connected to DMA1 Channel 7 , DMAMUX2 Channel 7 connected to BDMA Channel 7 */
299 #define LL_DMAMUX_CHANNEL_8 0x00000008U /*!< DMAMUX1 Channel 8 connected to DMA2 Channel 0 */
300 #define LL_DMAMUX_CHANNEL_9 0x00000009U /*!< DMAMUX1 Channel 9 connected to DMA2 Channel 1 */
301 #define LL_DMAMUX_CHANNEL_10 0x0000000AU /*!< DMAMUX1 Channel 10 connected to DMA2 Channel 2 */
302 #define LL_DMAMUX_CHANNEL_11 0x0000000BU /*!< DMAMUX1 Channel 11 connected to DMA2 Channel 3 */
303 #define LL_DMAMUX_CHANNEL_12 0x0000000CU /*!< DMAMUX1 Channel 12 connected to DMA2 Channel 4 */
304 #define LL_DMAMUX_CHANNEL_13 0x0000000DU /*!< DMAMUX1 Channel 13 connected to DMA2 Channel 5 */
305 #define LL_DMAMUX_CHANNEL_14 0x0000000EU /*!< DMAMUX1 Channel 14 connected to DMA2 Channel 6 */
306 #define LL_DMAMUX_CHANNEL_15 0x0000000FU /*!< DMAMUX1 Channel 15 connected to DMA2 Channel 7 */
307 /**
308 * @}
309 */
310
311 /** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity
312 * @{
313 */
314 #define LL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< All requests are blocked */
315 #define LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0 /*!< Synchronization on event on rising edge */
316 #define LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1 /*!< Synchronization on event on falling edge */
317 #define LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */
318 /**
319 * @}
320 */
321
322 /** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event
323 * @{
324 */
325 #define LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 0x00000000U /*!< D2 Domain synchronization Signal is DMAMUX1 Channel0 Event */
326 #define LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 0x01000000U /*!< D2 Domain synchronization Signal is DMAMUX1 Channel1 Event */
327 #define LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 0x02000000U /*!< D2 Domain synchronization Signal is DMAMUX1 Channel2 Event */
328 #define LL_DMAMUX1_SYNC_LPTIM1_OUT 0x03000000U /*!< D2 Domain synchronization Signal is LPTIM1 OUT */
329 #define LL_DMAMUX1_SYNC_LPTIM2_OUT 0x04000000U /*!< D2 Domain synchronization Signal is LPTIM2 OUT */
330 #define LL_DMAMUX1_SYNC_LPTIM3_OUT 0x05000000U /*!< D2 Domain synchronization Signal is LPTIM3 OUT */
331 #define LL_DMAMUX1_SYNC_EXTI0 0x06000000U /*!< D2 Domain synchronization Signal is EXTI0 IT */
332 #define LL_DMAMUX1_SYNC_TIM12_TRGO 0x07000000U /*!< D2 Domain synchronization Signal is TIM12 TRGO */
333
334 #define LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT 0x00000000U /*!< D3 Domain synchronization Signal is DMAMUX2 Channel0 Event */
335 #define LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT 0x01000000U /*!< D3 Domain synchronization Signal is DMAMUX2 Channel1 Event */
336 #define LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT 0x02000000U /*!< D3 Domain synchronization Signal is DMAMUX2 Channel2 Event */
337 #define LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT 0x03000000U /*!< D3 Domain synchronization Signal is DMAMUX2 Channel3 Event */
338 #define LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT 0x04000000U /*!< D3 Domain synchronization Signal is DMAMUX2 Channel4 Event */
339 #define LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT 0x05000000U /*!< D3 Domain synchronization Signal is DMAMUX2 Channel5 Event */
340 #define LL_DMAMUX2_SYNC_LPUART1_RX_WKUP 0x06000000U /*!< D3 Domain synchronization Signal is LPUART1 RX Wakeup */
341 #define LL_DMAMUX2_SYNC_LPUART1_TX_WKUP 0x07000000U /*!< D3 Domain synchronization Signal is LPUART1 TX Wakeup */
342 #define LL_DMAMUX2_SYNC_LPTIM2_OUT 0x08000000U /*!< D3 Domain synchronization Signal is LPTIM2 output */
343 #define LL_DMAMUX2_SYNC_LPTIM3_OUT 0x09000000U /*!< D3 Domain synchronization Signal is LPTIM3 output */
344 #define LL_DMAMUX2_SYNC_I2C4_WKUP 0x0A000000U /*!< D3 Domain synchronization Signal is I2C4 Wakeup */
345 #define LL_DMAMUX2_SYNC_SPI6_WKUP 0x0B000000U /*!< D3 Domain synchronization Signal is SPI6 Wakeup */
346 #define LL_DMAMUX2_SYNC_COMP1_OUT 0x0C000000U /*!< D3 Domain synchronization Signal is Comparator 1 output */
347 #define LL_DMAMUX2_SYNC_RTC_WKUP 0x0D000000U /*!< D3 Domain synchronization Signal is RTC Wakeup */
348 #define LL_DMAMUX2_SYNC_EXTI0 0x0E000000U /*!< D3 Domain synchronization Signal is EXTI0 IT */
349 #define LL_DMAMUX2_SYNC_EXTI2 0x0F000000U /*!< D3 Domain synchronization Signal is EXTI2 IT */
350
351 /**
352 * @}
353 */
354
355 /** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel
356 * @{
357 */
358 #define LL_DMAMUX_REQ_GEN_0 0x00000000U
359 #define LL_DMAMUX_REQ_GEN_1 0x00000001U
360 #define LL_DMAMUX_REQ_GEN_2 0x00000002U
361 #define LL_DMAMUX_REQ_GEN_3 0x00000003U
362 #define LL_DMAMUX_REQ_GEN_4 0x00000004U
363 #define LL_DMAMUX_REQ_GEN_5 0x00000005U
364 #define LL_DMAMUX_REQ_GEN_6 0x00000006U
365 #define LL_DMAMUX_REQ_GEN_7 0x00000007U
366 /**
367 * @}
368 */
369
370 /** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity
371 * @{
372 */
373 #define LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< No external DMA request generation */
374 #define LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0 /*!< External DMA request generation on event on rising edge */
375 #define LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1 /*!< External DMA request generation on event on falling edge */
376 #define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1) /*!< External DMA request generation on rising and falling edge */
377 /**
378 * @}
379 */
380
381 /** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation
382 * @{
383 */
384 #define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 0U /*!< D2 domain Request generator Signal is DMAMUX1 Channel0 Event */
385 #define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 1U /*!< D2 domain Request generator Signal is DMAMUX1 Channel1 Event */
386 #define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 2U /*!< D2 domain Request generator Signal is DMAMUX1 Channel2 Event */
387 #define LL_DMAMUX1_REQ_GEN_LPTIM1_OUT 3U /*!< D2 domain Request generator Signal is LPTIM1 OUT */
388 #define LL_DMAMUX1_REQ_GEN_LPTIM2_OUT 4U /*!< D2 domain Request generator Signal is LPTIM2 OUT */
389 #define LL_DMAMUX1_REQ_GEN_LPTIM3_OUT 5U /*!< D2 domain Request generator Signal is LPTIM3 OUT */
390 #define LL_DMAMUX1_REQ_GEN_EXTI0 6U /*!< D2 domain Request generator Signal is EXTI0 IT */
391 #define LL_DMAMUX1_REQ_GEN_TIM12_TRGO 7U /*!< D2 domain Request generator Signal is TIM12 TRGO */
392
393 #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 0U /*!< D3 domain Request generator Signal is DMAMUX2 Channel0 Event */
394 #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 1U /*!< D3 domain Request generator Signal is DMAMUX2 Channel1 Event */
395 #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 2U /*!< D3 domain Request generator Signal is DMAMUX2 Channel2 Event */
396 #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 3U /*!< D3 domain Request generator Signal is DMAMUX2 Channel3 Event */
397 #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 4U /*!< D3 domain Request generator Signal is DMAMUX2 Channel4 Event */
398 #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 5U /*!< D3 domain Request generator Signal is DMAMUX2 Channel5 Event */
399 #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 6U /*!< D3 domain Request generator Signal is DMAMUX2 Channel6 Event */
400 #define LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 7U /*!< D3 domain Request generator Signal is LPUART1 RX Wakeup */
401 #define LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 8U /*!< D3 domain Request generator Signal is LPUART1 TX Wakeup */
402 #define LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 9U /*!< D3 domain Request generator Signal is LPTIM2 Wakeup */
403 #define LL_DMAMUX2_REQ_GEN_LPTIM2_OUT 10U /*!< D3 domain Request generator Signal is LPTIM2 OUT */
404 #define LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 11U /*!< D3 domain Request generator Signal is LPTIM3 Wakeup */
405 #define LL_DMAMUX2_REQ_GEN_LPTIM3_OUT 12U /*!< D3 domain Request generator Signal is LPTIM3 OUT */
406 #define LL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 13U /*!< D3 domain Request generator Signal is LPTIM4 Wakeup */
407 #define LL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 14U /*!< D3 domain Request generator Signal is LPTIM5 Wakeup */
408 #define LL_DMAMUX2_REQ_GEN_I2C4_WKUP 15U /*!< D3 domain Request generator Signal is I2C4 Wakeup */
409 #define LL_DMAMUX2_REQ_GEN_SPI6_WKUP 16U /*!< D3 domain Request generator Signal is SPI6 Wakeup */
410 #define LL_DMAMUX2_REQ_GEN_COMP1_OUT 17U /*!< D3 domain Request generator Signal is Comparator 1 output */
411 #define LL_DMAMUX2_REQ_GEN_COMP2_OUT 18U /*!< D3 domain Request generator Signal is Comparator 2 output */
412 #define LL_DMAMUX2_REQ_GEN_RTC_WKUP 19U /*!< D3 domain Request generator Signal is RTC Wakeup */
413 #define LL_DMAMUX2_REQ_GEN_EXTI0 20U /*!< D3 domain Request generator Signal is EXTI0 */
414 #define LL_DMAMUX2_REQ_GEN_EXTI2 21U /*!< D3 domain Request generator Signal is EXTI2 */
415 #define LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 22U /*!< D3 domain Request generator Signal is I2C4 IT Event */
416 #define LL_DMAMUX2_REQ_GEN_SPI6_IT 23U /*!< D3 domain Request generator Signal is SPI6 IT */
417 #define LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 24U /*!< D3 domain Request generator Signal is LPUART1 Tx IT */
418 #define LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 25U /*!< D3 domain Request generator Signal is LPUART1 Rx IT */
419 #define LL_DMAMUX2_REQ_GEN_ADC3_IT 26U /*!< D3 domain Request generator Signal is ADC3 IT */
420 #define LL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 27U /*!< D3 domain Request generator Signal is ADC3 Analog Watchdog 1 output */
421 #define LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 28U /*!< D3 domain Request generator Signal is BDMA Channel 0 IT */
422 #define LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 29U /*!< D3 domain Request generator Signal is BDMA Channel 1 IT */
423 /**
424 * @}
425 */
426
427 /**
428 * @}
429 */
430
431 /* Exported macro ------------------------------------------------------------*/
432 /** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros
433 * @{
434 */
435
436 /** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros
437 * @{
438 */
439 /**
440 * @brief Write a value in DMAMUX register
441 * @param __INSTANCE__ DMAMUX Instance
442 * @param __REG__ Register to be written
443 * @param __VALUE__ Value to be written in the register
444 * @retval None
445 */
446 #define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
447
448 /**
449 * @brief Read a value in DMAMUX register
450 * @param __INSTANCE__ DMAMUX Instance
451 * @param __REG__ Register to be read
452 * @retval Register value
453 */
454 #define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
455 /**
456 * @}
457 */
458
459 /**
460 * @}
461 */
462
463 /* Exported functions --------------------------------------------------------*/
464 /** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions
465 * @{
466 */
467
468 /** @defgroup DMAMUX_LL_EF_Configuration Configuration
469 * @{
470 */
471 /**
472 * @brief Set DMAMUX request ID for DMAMUX Channel x.
473 * @note DMAMUX1 channel 0 to 7 are mapped to DMA1 channel 0 to 7.
474 * DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7.
475 * DMAMUX2 channel 0 to 7 are mapped to BDMA channel 0 to 7.
476 * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_SetRequestID
477 * @param DMAMUXx DMAMUXx Instance
478 * @param Channel This parameter can be one of the following values:
479 * @arg @ref LL_DMAMUX_CHANNEL_0
480 * @arg @ref LL_DMAMUX_CHANNEL_1
481 * @arg @ref LL_DMAMUX_CHANNEL_2
482 * @arg @ref LL_DMAMUX_CHANNEL_3
483 * @arg @ref LL_DMAMUX_CHANNEL_4
484 * @arg @ref LL_DMAMUX_CHANNEL_5
485 * @arg @ref LL_DMAMUX_CHANNEL_6
486 * @arg @ref LL_DMAMUX_CHANNEL_7
487 * @arg @ref LL_DMAMUX_CHANNEL_8
488 * @arg @ref LL_DMAMUX_CHANNEL_9
489 * @arg @ref LL_DMAMUX_CHANNEL_10
490 * @arg @ref LL_DMAMUX_CHANNEL_11
491 * @arg @ref LL_DMAMUX_CHANNEL_12
492 * @arg @ref LL_DMAMUX_CHANNEL_13
493 * @arg @ref LL_DMAMUX_CHANNEL_14
494 * @arg @ref LL_DMAMUX_CHANNEL_15
495 * @param Request This parameter can be one of the following values:
496 * @arg @ref LL_DMAMUX1_REQ_MEM2MEM
497 * @arg @ref LL_DMAMUX1_REQ_GENERATOR0
498 * @arg @ref LL_DMAMUX1_REQ_GENERATOR1
499 * @arg @ref LL_DMAMUX1_REQ_GENERATOR2
500 * @arg @ref LL_DMAMUX1_REQ_GENERATOR3
501 * @arg @ref LL_DMAMUX1_REQ_GENERATOR4
502 * @arg @ref LL_DMAMUX1_REQ_GENERATOR5
503 * @arg @ref LL_DMAMUX1_REQ_GENERATOR6
504 * @arg @ref LL_DMAMUX1_REQ_GENERATOR7
505 * @arg @ref LL_DMAMUX1_REQ_ADC1
506 * @arg @ref LL_DMAMUX1_REQ_ADC2
507 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
508 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
509 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
510 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
511 * @arg @ref LL_DMAMUX1_REQ_TIM1_UP
512 * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
513 * @arg @ref LL_DMAMUX1_REQ_TIM1_COM
514 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
515 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
516 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
517 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
518 * @arg @ref LL_DMAMUX1_REQ_TIM2_UP
519 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
520 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
521 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
522 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
523 * @arg @ref LL_DMAMUX1_REQ_TIM3_UP
524 * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
525 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
526 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
527 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
528 * @arg @ref LL_DMAMUX1_REQ_TIM4_UP
529 * @arg @ref LL_DMAMUX1_REQ_I2C1_RX
530 * @arg @ref LL_DMAMUX1_REQ_I2C1_TX
531 * @arg @ref LL_DMAMUX1_REQ_I2C2_RX
532 * @arg @ref LL_DMAMUX1_REQ_I2C2_TX
533 * @arg @ref LL_DMAMUX1_REQ_SPI1_RX
534 * @arg @ref LL_DMAMUX1_REQ_SPI1_TX
535 * @arg @ref LL_DMAMUX1_REQ_SPI2_RX
536 * @arg @ref LL_DMAMUX1_REQ_SPI2_TX
537 * @arg @ref LL_DMAMUX1_REQ_USART1_RX
538 * @arg @ref LL_DMAMUX1_REQ_USART1_TX
539 * @arg @ref LL_DMAMUX1_REQ_USART2_RX
540 * @arg @ref LL_DMAMUX1_REQ_USART2_TX
541 * @arg @ref LL_DMAMUX1_REQ_USART3_RX
542 * @arg @ref LL_DMAMUX1_REQ_USART3_TX
543 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
544 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
545 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
546 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
547 * @arg @ref LL_DMAMUX1_REQ_TIM8_UP
548 * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
549 * @arg @ref LL_DMAMUX1_REQ_TIM8_COM
550 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
551 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
552 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
553 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
554 * @arg @ref LL_DMAMUX1_REQ_TIM5_UP
555 * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
556 * @arg @ref LL_DMAMUX1_REQ_SPI3_RX
557 * @arg @ref LL_DMAMUX1_REQ_SPI3_TX
558 * @arg @ref LL_DMAMUX1_REQ_UART4_RX
559 * @arg @ref LL_DMAMUX1_REQ_UART4_TX
560 * @arg @ref LL_DMAMUX1_REQ_UART5_RX
561 * @arg @ref LL_DMAMUX1_REQ_UART5_TX
562 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
563 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
564 * @arg @ref LL_DMAMUX1_REQ_TIM6_UP
565 * @arg @ref LL_DMAMUX1_REQ_TIM7_UP
566 * @arg @ref LL_DMAMUX1_REQ_USART6_RX
567 * @arg @ref LL_DMAMUX1_REQ_USART6_TX
568 * @arg @ref LL_DMAMUX1_REQ_I2C3_RX
569 * @arg @ref LL_DMAMUX1_REQ_I2C3_TX
570 * @arg @ref LL_DMAMUX1_REQ_DCMI
571 * @arg @ref LL_DMAMUX1_REQ_CRYP_IN
572 * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
573 * @arg @ref LL_DMAMUX1_REQ_HASH_IN
574 * @arg @ref LL_DMAMUX1_REQ_UART7_RX
575 * @arg @ref LL_DMAMUX1_REQ_UART7_TX
576 * @arg @ref LL_DMAMUX1_REQ_UART8_RX
577 * @arg @ref LL_DMAMUX1_REQ_UART8_TX
578 * @arg @ref LL_DMAMUX1_REQ_SPI4_RX
579 * @arg @ref LL_DMAMUX1_REQ_SPI4_TX
580 * @arg @ref LL_DMAMUX1_REQ_SPI5_RX
581 * @arg @ref LL_DMAMUX1_REQ_SPI5_TX
582 * @arg @ref LL_DMAMUX1_REQ_SAI1_A
583 * @arg @ref LL_DMAMUX1_REQ_SAI1_B
584 * @arg @ref LL_DMAMUX1_REQ_SAI2_A
585 * @arg @ref LL_DMAMUX1_REQ_SAI2_B
586 * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
587 * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
588 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
589 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
590 * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER
591 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A
592 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B
593 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C
594 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D
595 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E
596 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
597 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
598 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
599 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
600 * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
601 * @arg @ref LL_DMAMUX1_REQ_TIM15_UP
602 * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
603 * @arg @ref LL_DMAMUX1_REQ_TIM15_COM
604 * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
605 * @arg @ref LL_DMAMUX1_REQ_TIM16_UP
606 * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
607 * @arg @ref LL_DMAMUX1_REQ_TIM17_UP
608 * @arg @ref LL_DMAMUX1_REQ_SAI3_A
609 * @arg @ref LL_DMAMUX1_REQ_SAI3_B
610 * @arg @ref LL_DMAMUX1_REQ_ADC3
611 * @arg @ref LL_DMAMUX2_REQ_MEM2MEM
612 * @arg @ref LL_DMAMUX2_REQ_GENERATOR0
613 * @arg @ref LL_DMAMUX2_REQ_GENERATOR1
614 * @arg @ref LL_DMAMUX2_REQ_GENERATOR2
615 * @arg @ref LL_DMAMUX2_REQ_GENERATOR3
616 * @arg @ref LL_DMAMUX2_REQ_GENERATOR4
617 * @arg @ref LL_DMAMUX2_REQ_GENERATOR5
618 * @arg @ref LL_DMAMUX2_REQ_GENERATOR6
619 * @arg @ref LL_DMAMUX2_REQ_GENERATOR7
620 * @arg @ref LL_DMAMUX2_REQ_LPUART1_RX
621 * @arg @ref LL_DMAMUX2_REQ_LPUART1_TX
622 * @arg @ref LL_DMAMUX2_REQ_SPI6_RX
623 * @arg @ref LL_DMAMUX2_REQ_SPI6_TX
624 * @arg @ref LL_DMAMUX2_REQ_I2C4_RX
625 * @arg @ref LL_DMAMUX2_REQ_I2C4_TX
626 * @arg @ref LL_DMAMUX2_REQ_SAI4_A
627 * @arg @ref LL_DMAMUX2_REQ_SAI4_B
628 * @arg @ref LL_DMAMUX2_REQ_ADC3
629 * @retval None
630 */
LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel,uint32_t Request)631 __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
632 {
633 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
634
635 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
636 }
637
638 /**
639 * @brief Get DMAMUX request ID for DMAMUX Channel x.
640 * @note DMAMUX1 channel 0 to 7 are mapped to DMA1 channel 0 to 7.
641 * DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7.
642 * DMAMUX2 channel 0 to 7 are mapped to BDMA channel 0 to 7.
643 * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_GetRequestID
644 * @param DMAMUXx DMAMUXx Instance
645 * @param Channel This parameter can be one of the following values:
646 * @arg @ref LL_DMAMUX_CHANNEL_0
647 * @arg @ref LL_DMAMUX_CHANNEL_1
648 * @arg @ref LL_DMAMUX_CHANNEL_2
649 * @arg @ref LL_DMAMUX_CHANNEL_3
650 * @arg @ref LL_DMAMUX_CHANNEL_4
651 * @arg @ref LL_DMAMUX_CHANNEL_5
652 * @arg @ref LL_DMAMUX_CHANNEL_6
653 * @arg @ref LL_DMAMUX_CHANNEL_7
654 * @arg @ref LL_DMAMUX_CHANNEL_8
655 * @arg @ref LL_DMAMUX_CHANNEL_9
656 * @arg @ref LL_DMAMUX_CHANNEL_10
657 * @arg @ref LL_DMAMUX_CHANNEL_11
658 * @arg @ref LL_DMAMUX_CHANNEL_12
659 * @arg @ref LL_DMAMUX_CHANNEL_13
660 * @arg @ref LL_DMAMUX_CHANNEL_14
661 * @arg @ref LL_DMAMUX_CHANNEL_15
662 * @retval Returned value can be one of the following values:
663 * @arg @ref LL_DMAMUX1_REQ_MEM2MEM
664 * @arg @ref LL_DMAMUX1_REQ_GENERATOR0
665 * @arg @ref LL_DMAMUX1_REQ_GENERATOR1
666 * @arg @ref LL_DMAMUX1_REQ_GENERATOR2
667 * @arg @ref LL_DMAMUX1_REQ_GENERATOR3
668 * @arg @ref LL_DMAMUX1_REQ_GENERATOR4
669 * @arg @ref LL_DMAMUX1_REQ_GENERATOR5
670 * @arg @ref LL_DMAMUX1_REQ_GENERATOR6
671 * @arg @ref LL_DMAMUX1_REQ_GENERATOR7
672 * @arg @ref LL_DMAMUX1_REQ_ADC1
673 * @arg @ref LL_DMAMUX1_REQ_ADC2
674 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
675 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
676 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
677 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
678 * @arg @ref LL_DMAMUX1_REQ_TIM1_UP
679 * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
680 * @arg @ref LL_DMAMUX1_REQ_TIM1_COM
681 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
682 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
683 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
684 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
685 * @arg @ref LL_DMAMUX1_REQ_TIM2_UP
686 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
687 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
688 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
689 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
690 * @arg @ref LL_DMAMUX1_REQ_TIM3_UP
691 * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
692 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
693 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
694 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
695 * @arg @ref LL_DMAMUX1_REQ_TIM4_UP
696 * @arg @ref LL_DMAMUX1_REQ_I2C1_RX
697 * @arg @ref LL_DMAMUX1_REQ_I2C1_TX
698 * @arg @ref LL_DMAMUX1_REQ_I2C2_RX
699 * @arg @ref LL_DMAMUX1_REQ_I2C2_TX
700 * @arg @ref LL_DMAMUX1_REQ_SPI1_RX
701 * @arg @ref LL_DMAMUX1_REQ_SPI1_TX
702 * @arg @ref LL_DMAMUX1_REQ_SPI2_RX
703 * @arg @ref LL_DMAMUX1_REQ_SPI2_TX
704 * @arg @ref LL_DMAMUX1_REQ_USART1_RX
705 * @arg @ref LL_DMAMUX1_REQ_USART1_TX
706 * @arg @ref LL_DMAMUX1_REQ_USART2_RX
707 * @arg @ref LL_DMAMUX1_REQ_USART2_TX
708 * @arg @ref LL_DMAMUX1_REQ_USART3_RX
709 * @arg @ref LL_DMAMUX1_REQ_USART3_TX
710 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
711 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
712 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
713 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
714 * @arg @ref LL_DMAMUX1_REQ_TIM8_UP
715 * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
716 * @arg @ref LL_DMAMUX1_REQ_TIM8_COM
717 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
718 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
719 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
720 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
721 * @arg @ref LL_DMAMUX1_REQ_TIM5_UP
722 * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
723 * @arg @ref LL_DMAMUX1_REQ_SPI3_RX
724 * @arg @ref LL_DMAMUX1_REQ_SPI3_TX
725 * @arg @ref LL_DMAMUX1_REQ_UART4_RX
726 * @arg @ref LL_DMAMUX1_REQ_UART4_TX
727 * @arg @ref LL_DMAMUX1_REQ_UART5_RX
728 * @arg @ref LL_DMAMUX1_REQ_UART5_TX
729 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
730 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
731 * @arg @ref LL_DMAMUX1_REQ_TIM6_UP
732 * @arg @ref LL_DMAMUX1_REQ_TIM7_UP
733 * @arg @ref LL_DMAMUX1_REQ_USART6_RX
734 * @arg @ref LL_DMAMUX1_REQ_USART6_TX
735 * @arg @ref LL_DMAMUX1_REQ_I2C3_RX
736 * @arg @ref LL_DMAMUX1_REQ_I2C3_TX
737 * @arg @ref LL_DMAMUX1_REQ_DCMI
738 * @arg @ref LL_DMAMUX1_REQ_CRYP_IN
739 * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
740 * @arg @ref LL_DMAMUX1_REQ_HASH_IN
741 * @arg @ref LL_DMAMUX1_REQ_UART7_RX
742 * @arg @ref LL_DMAMUX1_REQ_UART7_TX
743 * @arg @ref LL_DMAMUX1_REQ_UART8_RX
744 * @arg @ref LL_DMAMUX1_REQ_UART8_TX
745 * @arg @ref LL_DMAMUX1_REQ_SPI4_RX
746 * @arg @ref LL_DMAMUX1_REQ_SPI4_TX
747 * @arg @ref LL_DMAMUX1_REQ_SPI5_RX
748 * @arg @ref LL_DMAMUX1_REQ_SPI5_TX
749 * @arg @ref LL_DMAMUX1_REQ_SAI1_A
750 * @arg @ref LL_DMAMUX1_REQ_SAI1_B
751 * @arg @ref LL_DMAMUX1_REQ_SAI2_A
752 * @arg @ref LL_DMAMUX1_REQ_SAI2_B
753 * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
754 * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
755 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
756 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
757 * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER
758 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A
759 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B
760 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C
761 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D
762 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E
763 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
764 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
765 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
766 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
767 * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
768 * @arg @ref LL_DMAMUX1_REQ_TIM15_UP
769 * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
770 * @arg @ref LL_DMAMUX1_REQ_TIM15_COM
771 * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
772 * @arg @ref LL_DMAMUX1_REQ_TIM16_UP
773 * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
774 * @arg @ref LL_DMAMUX1_REQ_TIM17_UP
775 * @arg @ref LL_DMAMUX1_REQ_SAI3_A
776 * @arg @ref LL_DMAMUX1_REQ_SAI3_B
777 * @arg @ref LL_DMAMUX1_REQ_ADC3
778 * @arg @ref LL_DMAMUX2_REQ_MEM2MEM
779 * @arg @ref LL_DMAMUX2_REQ_GENERATOR0
780 * @arg @ref LL_DMAMUX2_REQ_GENERATOR1
781 * @arg @ref LL_DMAMUX2_REQ_GENERATOR2
782 * @arg @ref LL_DMAMUX2_REQ_GENERATOR3
783 * @arg @ref LL_DMAMUX2_REQ_GENERATOR4
784 * @arg @ref LL_DMAMUX2_REQ_GENERATOR5
785 * @arg @ref LL_DMAMUX2_REQ_GENERATOR6
786 * @arg @ref LL_DMAMUX2_REQ_GENERATOR7
787 * @arg @ref LL_DMAMUX2_REQ_LPUART1_RX
788 * @arg @ref LL_DMAMUX2_REQ_LPUART1_TX
789 * @arg @ref LL_DMAMUX2_REQ_SPI6_RX
790 * @arg @ref LL_DMAMUX2_REQ_SPI6_TX
791 * @arg @ref LL_DMAMUX2_REQ_I2C4_RX
792 * @arg @ref LL_DMAMUX2_REQ_I2C4_TX
793 * @arg @ref LL_DMAMUX2_REQ_SAI4_A
794 * @arg @ref LL_DMAMUX2_REQ_SAI4_B
795 * @arg @ref LL_DMAMUX2_REQ_ADC3
796 */
LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)797 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
798 {
799 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
800
801 return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
802 }
803
804 /**
805 * @brief Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
806 * @rmtoll CxCR NBREQ LL_DMAMUX_SetSyncRequestNb
807 * @param DMAMUXx DMAMUXx Instance
808 * @param Channel This parameter can be one of the following values:
809 * @arg @ref LL_DMAMUX_CHANNEL_0
810 * @arg @ref LL_DMAMUX_CHANNEL_1
811 * @arg @ref LL_DMAMUX_CHANNEL_2
812 * @arg @ref LL_DMAMUX_CHANNEL_3
813 * @arg @ref LL_DMAMUX_CHANNEL_4
814 * @arg @ref LL_DMAMUX_CHANNEL_5
815 * @arg @ref LL_DMAMUX_CHANNEL_6
816 * @arg @ref LL_DMAMUX_CHANNEL_7
817 * @arg @ref LL_DMAMUX_CHANNEL_8
818 * @arg @ref LL_DMAMUX_CHANNEL_9
819 * @arg @ref LL_DMAMUX_CHANNEL_10
820 * @arg @ref LL_DMAMUX_CHANNEL_11
821 * @arg @ref LL_DMAMUX_CHANNEL_12
822 * @arg @ref LL_DMAMUX_CHANNEL_13
823 * @arg @ref LL_DMAMUX_CHANNEL_14
824 * @arg @ref LL_DMAMUX_CHANNEL_15
825 * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
826 * @retval None
827 */
LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel,uint32_t RequestNb)828 __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
829 {
830 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
831
832 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ, (RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos);
833 }
834
835 /**
836 * @brief Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
837 * @rmtoll CxCR NBREQ LL_DMAMUX_GetSyncRequestNb
838 * @param DMAMUXx DMAMUXx Instance
839 * @param Channel This parameter can be one of the following values:
840 * @arg @ref LL_DMAMUX_CHANNEL_0
841 * @arg @ref LL_DMAMUX_CHANNEL_1
842 * @arg @ref LL_DMAMUX_CHANNEL_2
843 * @arg @ref LL_DMAMUX_CHANNEL_3
844 * @arg @ref LL_DMAMUX_CHANNEL_4
845 * @arg @ref LL_DMAMUX_CHANNEL_5
846 * @arg @ref LL_DMAMUX_CHANNEL_6
847 * @arg @ref LL_DMAMUX_CHANNEL_7
848 * @arg @ref LL_DMAMUX_CHANNEL_8
849 * @arg @ref LL_DMAMUX_CHANNEL_9
850 * @arg @ref LL_DMAMUX_CHANNEL_10
851 * @arg @ref LL_DMAMUX_CHANNEL_11
852 * @arg @ref LL_DMAMUX_CHANNEL_12
853 * @arg @ref LL_DMAMUX_CHANNEL_13
854 * @arg @ref LL_DMAMUX_CHANNEL_14
855 * @arg @ref LL_DMAMUX_CHANNEL_15
856 * @retval Between Min_Data = 1 and Max_Data = 32
857 */
LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)858 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
859 {
860 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
861
862 return (uint32_t)((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ) >> DMAMUX_CxCR_NBREQ_Pos) + 1U);
863 }
864
865 /**
866 * @brief Set the polarity of the signal on which the DMA request is synchronized.
867 * @rmtoll CxCR SPOL LL_DMAMUX_SetSyncPolarity
868 * @param DMAMUXx DMAMUXx Instance
869 * @param Channel This parameter can be one of the following values:
870 * @arg @ref LL_DMAMUX_CHANNEL_0
871 * @arg @ref LL_DMAMUX_CHANNEL_1
872 * @arg @ref LL_DMAMUX_CHANNEL_2
873 * @arg @ref LL_DMAMUX_CHANNEL_3
874 * @arg @ref LL_DMAMUX_CHANNEL_4
875 * @arg @ref LL_DMAMUX_CHANNEL_5
876 * @arg @ref LL_DMAMUX_CHANNEL_6
877 * @arg @ref LL_DMAMUX_CHANNEL_7
878 * @arg @ref LL_DMAMUX_CHANNEL_8
879 * @arg @ref LL_DMAMUX_CHANNEL_9
880 * @arg @ref LL_DMAMUX_CHANNEL_10
881 * @arg @ref LL_DMAMUX_CHANNEL_11
882 * @arg @ref LL_DMAMUX_CHANNEL_12
883 * @arg @ref LL_DMAMUX_CHANNEL_13
884 * @arg @ref LL_DMAMUX_CHANNEL_14
885 * @arg @ref LL_DMAMUX_CHANNEL_15
886 * @param Polarity This parameter can be one of the following values:
887 * @arg @ref LL_DMAMUX_SYNC_NO_EVENT
888 * @arg @ref LL_DMAMUX_SYNC_POL_RISING
889 * @arg @ref LL_DMAMUX_SYNC_POL_FALLING
890 * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
891 * @retval None
892 */
LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel,uint32_t Polarity)893 __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
894 {
895 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
896
897 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL, Polarity);
898 }
899
900 /**
901 * @brief Get the polarity of the signal on which the DMA request is synchronized.
902 * @rmtoll CxCR SPOL LL_DMAMUX_GetSyncPolarity
903 * @param DMAMUXx DMAMUXx Instance
904 * @param Channel This parameter can be one of the following values:
905 * @arg @ref LL_DMAMUX_CHANNEL_0
906 * @arg @ref LL_DMAMUX_CHANNEL_1
907 * @arg @ref LL_DMAMUX_CHANNEL_2
908 * @arg @ref LL_DMAMUX_CHANNEL_3
909 * @arg @ref LL_DMAMUX_CHANNEL_4
910 * @arg @ref LL_DMAMUX_CHANNEL_5
911 * @arg @ref LL_DMAMUX_CHANNEL_6
912 * @arg @ref LL_DMAMUX_CHANNEL_7
913 * @arg @ref LL_DMAMUX_CHANNEL_8
914 * @arg @ref LL_DMAMUX_CHANNEL_9
915 * @arg @ref LL_DMAMUX_CHANNEL_10
916 * @arg @ref LL_DMAMUX_CHANNEL_11
917 * @arg @ref LL_DMAMUX_CHANNEL_12
918 * @arg @ref LL_DMAMUX_CHANNEL_13
919 * @arg @ref LL_DMAMUX_CHANNEL_14
920 * @arg @ref LL_DMAMUX_CHANNEL_15
921 * @retval Returned value can be one of the following values:
922 * @arg @ref LL_DMAMUX_SYNC_NO_EVENT
923 * @arg @ref LL_DMAMUX_SYNC_POL_RISING
924 * @arg @ref LL_DMAMUX_SYNC_POL_FALLING
925 * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
926 */
LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)927 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
928 {
929 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
930
931 return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL));
932 }
933
934 /**
935 * @brief Enable the Event Generation on DMAMUX channel x.
936 * @rmtoll CxCR EGE LL_DMAMUX_EnableEventGeneration
937 * @param DMAMUXx DMAMUXx Instance
938 * @param Channel This parameter can be one of the following values:
939 * @arg @ref LL_DMAMUX_CHANNEL_0
940 * @arg @ref LL_DMAMUX_CHANNEL_1
941 * @arg @ref LL_DMAMUX_CHANNEL_2
942 * @arg @ref LL_DMAMUX_CHANNEL_3
943 * @arg @ref LL_DMAMUX_CHANNEL_4
944 * @arg @ref LL_DMAMUX_CHANNEL_5
945 * @arg @ref LL_DMAMUX_CHANNEL_6
946 * @arg @ref LL_DMAMUX_CHANNEL_7
947 * @arg @ref LL_DMAMUX_CHANNEL_8
948 * @arg @ref LL_DMAMUX_CHANNEL_9
949 * @arg @ref LL_DMAMUX_CHANNEL_10
950 * @arg @ref LL_DMAMUX_CHANNEL_11
951 * @arg @ref LL_DMAMUX_CHANNEL_12
952 * @arg @ref LL_DMAMUX_CHANNEL_13
953 * @arg @ref LL_DMAMUX_CHANNEL_14
954 * @arg @ref LL_DMAMUX_CHANNEL_15
955 * @retval None
956 */
LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)957 __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
958 {
959 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
960
961 SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE);
962 }
963
964 /**
965 * @brief Disable the Event Generation on DMAMUX channel x.
966 * @rmtoll CxCR EGE LL_DMAMUX_DisableEventGeneration
967 * @param DMAMUXx DMAMUXx Instance
968 * @param Channel This parameter can be one of the following values:
969 * @arg @ref LL_DMAMUX_CHANNEL_0
970 * @arg @ref LL_DMAMUX_CHANNEL_1
971 * @arg @ref LL_DMAMUX_CHANNEL_2
972 * @arg @ref LL_DMAMUX_CHANNEL_3
973 * @arg @ref LL_DMAMUX_CHANNEL_4
974 * @arg @ref LL_DMAMUX_CHANNEL_5
975 * @arg @ref LL_DMAMUX_CHANNEL_6
976 * @arg @ref LL_DMAMUX_CHANNEL_7
977 * @arg @ref LL_DMAMUX_CHANNEL_8
978 * @arg @ref LL_DMAMUX_CHANNEL_9
979 * @arg @ref LL_DMAMUX_CHANNEL_10
980 * @arg @ref LL_DMAMUX_CHANNEL_11
981 * @arg @ref LL_DMAMUX_CHANNEL_12
982 * @arg @ref LL_DMAMUX_CHANNEL_13
983 * @arg @ref LL_DMAMUX_CHANNEL_14
984 * @arg @ref LL_DMAMUX_CHANNEL_15
985 * @retval None
986 */
LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)987 __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
988 {
989 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
990
991 CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE);
992 }
993
994 /**
995 * @brief Check if the Event Generation on DMAMUX channel x is enabled or disabled.
996 * @rmtoll CxCR EGE LL_DMAMUX_IsEnabledEventGeneration
997 * @param DMAMUXx DMAMUXx Instance
998 * @param Channel This parameter can be one of the following values:
999 * @arg @ref LL_DMAMUX_CHANNEL_0
1000 * @arg @ref LL_DMAMUX_CHANNEL_1
1001 * @arg @ref LL_DMAMUX_CHANNEL_2
1002 * @arg @ref LL_DMAMUX_CHANNEL_3
1003 * @arg @ref LL_DMAMUX_CHANNEL_4
1004 * @arg @ref LL_DMAMUX_CHANNEL_5
1005 * @arg @ref LL_DMAMUX_CHANNEL_6
1006 * @arg @ref LL_DMAMUX_CHANNEL_7
1007 * @arg @ref LL_DMAMUX_CHANNEL_8
1008 * @arg @ref LL_DMAMUX_CHANNEL_9
1009 * @arg @ref LL_DMAMUX_CHANNEL_10
1010 * @arg @ref LL_DMAMUX_CHANNEL_11
1011 * @arg @ref LL_DMAMUX_CHANNEL_12
1012 * @arg @ref LL_DMAMUX_CHANNEL_13
1013 * @arg @ref LL_DMAMUX_CHANNEL_14
1014 * @arg @ref LL_DMAMUX_CHANNEL_15
1015 * @retval State of bit (1 or 0).
1016 */
LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)1017 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1018 {
1019 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1020
1021 return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL);
1022 }
1023
1024 /**
1025 * @brief Enable the synchronization mode.
1026 * @rmtoll CxCR SE LL_DMAMUX_EnableSync
1027 * @param DMAMUXx DMAMUXx Instance
1028 * @param Channel This parameter can be one of the following values:
1029 * @arg @ref LL_DMAMUX_CHANNEL_0
1030 * @arg @ref LL_DMAMUX_CHANNEL_1
1031 * @arg @ref LL_DMAMUX_CHANNEL_2
1032 * @arg @ref LL_DMAMUX_CHANNEL_3
1033 * @arg @ref LL_DMAMUX_CHANNEL_4
1034 * @arg @ref LL_DMAMUX_CHANNEL_5
1035 * @arg @ref LL_DMAMUX_CHANNEL_6
1036 * @arg @ref LL_DMAMUX_CHANNEL_7
1037 * @arg @ref LL_DMAMUX_CHANNEL_8
1038 * @arg @ref LL_DMAMUX_CHANNEL_9
1039 * @arg @ref LL_DMAMUX_CHANNEL_10
1040 * @arg @ref LL_DMAMUX_CHANNEL_11
1041 * @arg @ref LL_DMAMUX_CHANNEL_12
1042 * @arg @ref LL_DMAMUX_CHANNEL_13
1043 * @arg @ref LL_DMAMUX_CHANNEL_14
1044 * @arg @ref LL_DMAMUX_CHANNEL_15
1045 * @retval None
1046 */
LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)1047 __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1048 {
1049 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1050
1051 SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE);
1052 }
1053
1054 /**
1055 * @brief Disable the synchronization mode.
1056 * @rmtoll CxCR SE LL_DMAMUX_DisableSync
1057 * @param DMAMUXx DMAMUXx Instance
1058 * @param Channel This parameter can be one of the following values:
1059 * @arg @ref LL_DMAMUX_CHANNEL_0
1060 * @arg @ref LL_DMAMUX_CHANNEL_1
1061 * @arg @ref LL_DMAMUX_CHANNEL_2
1062 * @arg @ref LL_DMAMUX_CHANNEL_3
1063 * @arg @ref LL_DMAMUX_CHANNEL_4
1064 * @arg @ref LL_DMAMUX_CHANNEL_5
1065 * @arg @ref LL_DMAMUX_CHANNEL_6
1066 * @arg @ref LL_DMAMUX_CHANNEL_7
1067 * @arg @ref LL_DMAMUX_CHANNEL_8
1068 * @arg @ref LL_DMAMUX_CHANNEL_9
1069 * @arg @ref LL_DMAMUX_CHANNEL_10
1070 * @arg @ref LL_DMAMUX_CHANNEL_11
1071 * @arg @ref LL_DMAMUX_CHANNEL_12
1072 * @arg @ref LL_DMAMUX_CHANNEL_13
1073 * @arg @ref LL_DMAMUX_CHANNEL_14
1074 * @arg @ref LL_DMAMUX_CHANNEL_15
1075 * @retval None
1076 */
LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)1077 __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1078 {
1079 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1080
1081 CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE);
1082 }
1083
1084 /**
1085 * @brief Check if the synchronization mode is enabled or disabled.
1086 * @rmtoll CxCR SE LL_DMAMUX_IsEnabledSync
1087 * @param DMAMUXx DMAMUXx Instance
1088 * @param Channel This parameter can be one of the following values:
1089 * @arg @ref LL_DMAMUX_CHANNEL_0
1090 * @arg @ref LL_DMAMUX_CHANNEL_1
1091 * @arg @ref LL_DMAMUX_CHANNEL_2
1092 * @arg @ref LL_DMAMUX_CHANNEL_3
1093 * @arg @ref LL_DMAMUX_CHANNEL_4
1094 * @arg @ref LL_DMAMUX_CHANNEL_5
1095 * @arg @ref LL_DMAMUX_CHANNEL_6
1096 * @arg @ref LL_DMAMUX_CHANNEL_7
1097 * @arg @ref LL_DMAMUX_CHANNEL_8
1098 * @arg @ref LL_DMAMUX_CHANNEL_9
1099 * @arg @ref LL_DMAMUX_CHANNEL_10
1100 * @arg @ref LL_DMAMUX_CHANNEL_11
1101 * @arg @ref LL_DMAMUX_CHANNEL_12
1102 * @arg @ref LL_DMAMUX_CHANNEL_13
1103 * @arg @ref LL_DMAMUX_CHANNEL_14
1104 * @arg @ref LL_DMAMUX_CHANNEL_15
1105 * @retval State of bit (1 or 0).
1106 */
LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)1107 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1108 {
1109 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1110
1111 return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL);
1112 }
1113
1114 /**
1115 * @brief Set DMAMUX synchronization ID on DMAMUX Channel x.
1116 * @rmtoll CxCR SYNC_ID LL_DMAMUX_SetSyncID
1117 * @param DMAMUXx DMAMUXx Instance
1118 * @param Channel This parameter can be one of the following values:
1119 * @arg @ref LL_DMAMUX_CHANNEL_0
1120 * @arg @ref LL_DMAMUX_CHANNEL_1
1121 * @arg @ref LL_DMAMUX_CHANNEL_2
1122 * @arg @ref LL_DMAMUX_CHANNEL_3
1123 * @arg @ref LL_DMAMUX_CHANNEL_4
1124 * @arg @ref LL_DMAMUX_CHANNEL_5
1125 * @arg @ref LL_DMAMUX_CHANNEL_6
1126 * @arg @ref LL_DMAMUX_CHANNEL_7
1127 * @arg @ref LL_DMAMUX_CHANNEL_8
1128 * @arg @ref LL_DMAMUX_CHANNEL_9
1129 * @arg @ref LL_DMAMUX_CHANNEL_10
1130 * @arg @ref LL_DMAMUX_CHANNEL_11
1131 * @arg @ref LL_DMAMUX_CHANNEL_12
1132 * @arg @ref LL_DMAMUX_CHANNEL_13
1133 * @arg @ref LL_DMAMUX_CHANNEL_14
1134 * @arg @ref LL_DMAMUX_CHANNEL_15
1135 * @param SyncID This parameter can be one of the following values:
1136 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
1137 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
1138 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
1139 * @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT
1140 * @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT
1141 * @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT
1142 * @arg @ref LL_DMAMUX1_SYNC_EXTI0
1143 * @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO
1144 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT
1145 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT
1146 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT
1147 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT
1148 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT
1149 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT
1150 * @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP
1151 * @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP
1152 * @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT
1153 * @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT
1154 * @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP
1155 * @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP
1156 * @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT
1157 * @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP
1158 * @arg @ref LL_DMAMUX2_SYNC_EXTI0
1159 * @arg @ref LL_DMAMUX2_SYNC_EXTI2
1160 * @retval None
1161 */
LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel,uint32_t SyncID)1162 __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
1163 {
1164 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1165
1166 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID, SyncID);
1167 }
1168
1169 /**
1170 * @brief Get DMAMUX synchronization ID on DMAMUX Channel x.
1171 * @rmtoll CxCR SYNC_ID LL_DMAMUX_GetSyncID
1172 * @param DMAMUXx DMAMUXx Instance
1173 * @param Channel This parameter can be one of the following values:
1174 * @arg @ref LL_DMAMUX_CHANNEL_0
1175 * @arg @ref LL_DMAMUX_CHANNEL_1
1176 * @arg @ref LL_DMAMUX_CHANNEL_2
1177 * @arg @ref LL_DMAMUX_CHANNEL_3
1178 * @arg @ref LL_DMAMUX_CHANNEL_4
1179 * @arg @ref LL_DMAMUX_CHANNEL_5
1180 * @arg @ref LL_DMAMUX_CHANNEL_6
1181 * @arg @ref LL_DMAMUX_CHANNEL_7
1182 * @arg @ref LL_DMAMUX_CHANNEL_8
1183 * @arg @ref LL_DMAMUX_CHANNEL_9
1184 * @arg @ref LL_DMAMUX_CHANNEL_10
1185 * @arg @ref LL_DMAMUX_CHANNEL_11
1186 * @arg @ref LL_DMAMUX_CHANNEL_12
1187 * @arg @ref LL_DMAMUX_CHANNEL_13
1188 * @arg @ref LL_DMAMUX_CHANNEL_14
1189 * @arg @ref LL_DMAMUX_CHANNEL_15
1190 * @retval Returned value can be one of the following values:
1191 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
1192 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
1193 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
1194 * @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT
1195 * @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT
1196 * @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT
1197 * @arg @ref LL_DMAMUX1_SYNC_EXTI0
1198 * @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO
1199 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT
1200 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT
1201 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT
1202 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT
1203 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT
1204 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT
1205 * @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP
1206 * @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP
1207 * @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT
1208 * @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT
1209 * @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP
1210 * @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP
1211 * @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT
1212 * @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP
1213 * @arg @ref LL_DMAMUX2_SYNC_EXTI0
1214 * @arg @ref LL_DMAMUX2_SYNC_EXTI2
1215 */
LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)1216 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1217 {
1218 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1219
1220 return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID));
1221 }
1222
1223 /**
1224 * @brief Enable the Request Generator.
1225 * @rmtoll RGxCR GE LL_DMAMUX_EnableRequestGen
1226 * @param DMAMUXx DMAMUXx Instance
1227 * @param RequestGenChannel This parameter can be one of the following values:
1228 * @arg @ref LL_DMAMUX_REQ_GEN_0
1229 * @arg @ref LL_DMAMUX_REQ_GEN_1
1230 * @arg @ref LL_DMAMUX_REQ_GEN_2
1231 * @arg @ref LL_DMAMUX_REQ_GEN_3
1232 * @arg @ref LL_DMAMUX_REQ_GEN_4
1233 * @arg @ref LL_DMAMUX_REQ_GEN_5
1234 * @arg @ref LL_DMAMUX_REQ_GEN_6
1235 * @arg @ref LL_DMAMUX_REQ_GEN_7
1236 * @retval None
1237 */
LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1238 __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1239 {
1240 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1241
1242 SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE);
1243 }
1244
1245 /**
1246 * @brief Disable the Request Generator.
1247 * @rmtoll RGxCR GE LL_DMAMUX_DisableRequestGen
1248 * @param DMAMUXx DMAMUXx Instance
1249 * @param RequestGenChannel This parameter can be one of the following values:
1250 * @arg @ref LL_DMAMUX_REQ_GEN_0
1251 * @arg @ref LL_DMAMUX_REQ_GEN_1
1252 * @arg @ref LL_DMAMUX_REQ_GEN_2
1253 * @arg @ref LL_DMAMUX_REQ_GEN_3
1254 * @retval None
1255 */
LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1256 __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1257 {
1258 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1259
1260 CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE);
1261 }
1262
1263 /**
1264 * @brief Check if the Request Generator is enabled or disabled.
1265 * @rmtoll RGxCR GE LL_DMAMUX_IsEnabledRequestGen
1266 * @param DMAMUXx DMAMUXx Instance
1267 * @param RequestGenChannel This parameter can be one of the following values:
1268 * @arg @ref LL_DMAMUX_REQ_GEN_0
1269 * @arg @ref LL_DMAMUX_REQ_GEN_1
1270 * @arg @ref LL_DMAMUX_REQ_GEN_2
1271 * @arg @ref LL_DMAMUX_REQ_GEN_3
1272 * @arg @ref LL_DMAMUX_REQ_GEN_4
1273 * @arg @ref LL_DMAMUX_REQ_GEN_5
1274 * @arg @ref LL_DMAMUX_REQ_GEN_6
1275 * @arg @ref LL_DMAMUX_REQ_GEN_7
1276 * @retval State of bit (1 or 0).
1277 */
LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1278 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1279 {
1280 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1281
1282 return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL);
1283 }
1284
1285 /**
1286 * @brief Set the polarity of the signal on which the DMA request is generated.
1287 * @rmtoll RGxCR GPOL LL_DMAMUX_SetRequestGenPolarity
1288 * @param DMAMUXx DMAMUXx Instance
1289 * @param RequestGenChannel This parameter can be one of the following values:
1290 * @arg @ref LL_DMAMUX_REQ_GEN_0
1291 * @arg @ref LL_DMAMUX_REQ_GEN_1
1292 * @arg @ref LL_DMAMUX_REQ_GEN_2
1293 * @arg @ref LL_DMAMUX_REQ_GEN_3
1294 * @arg @ref LL_DMAMUX_REQ_GEN_4
1295 * @arg @ref LL_DMAMUX_REQ_GEN_5
1296 * @arg @ref LL_DMAMUX_REQ_GEN_6
1297 * @arg @ref LL_DMAMUX_REQ_GEN_7
1298 * @param Polarity This parameter can be one of the following values:
1299 * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
1300 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
1301 * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
1302 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
1303 * @retval None
1304 */
LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel,uint32_t Polarity)1305 __STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity)
1306 {
1307 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1308
1309 MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL, Polarity);
1310 }
1311
1312 /**
1313 * @brief Get the polarity of the signal on which the DMA request is generated.
1314 * @rmtoll RGxCR GPOL LL_DMAMUX_GetRequestGenPolarity
1315 * @param DMAMUXx DMAMUXx Instance
1316 * @param RequestGenChannel This parameter can be one of the following values:
1317 * @arg @ref LL_DMAMUX_REQ_GEN_0
1318 * @arg @ref LL_DMAMUX_REQ_GEN_1
1319 * @arg @ref LL_DMAMUX_REQ_GEN_2
1320 * @arg @ref LL_DMAMUX_REQ_GEN_3
1321 * @arg @ref LL_DMAMUX_REQ_GEN_4
1322 * @arg @ref LL_DMAMUX_REQ_GEN_5
1323 * @arg @ref LL_DMAMUX_REQ_GEN_6
1324 * @arg @ref LL_DMAMUX_REQ_GEN_7
1325 * @retval Returned value can be one of the following values:
1326 * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
1327 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
1328 * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
1329 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
1330 */
LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1331 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1332 {
1333 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1334
1335 return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL));
1336 }
1337
1338 /**
1339 * @brief Set the number of DMA request that will be autorized after a generation event.
1340 * @note This field can only be written when Generator is disabled.
1341 * @rmtoll RGxCR GNBREQ LL_DMAMUX_SetGenRequestNb
1342 * @param DMAMUXx DMAMUXx Instance
1343 * @param RequestGenChannel This parameter can be one of the following values:
1344 * @arg @ref LL_DMAMUX_REQ_GEN_0
1345 * @arg @ref LL_DMAMUX_REQ_GEN_1
1346 * @arg @ref LL_DMAMUX_REQ_GEN_2
1347 * @arg @ref LL_DMAMUX_REQ_GEN_3
1348 * @arg @ref LL_DMAMUX_REQ_GEN_4
1349 * @arg @ref LL_DMAMUX_REQ_GEN_5
1350 * @arg @ref LL_DMAMUX_REQ_GEN_6
1351 * @arg @ref LL_DMAMUX_REQ_GEN_7
1352 * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
1353 * @retval None
1354 */
LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel,uint32_t RequestNb)1355 __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb)
1356 {
1357 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1358
1359 MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos);
1360 }
1361
1362 /**
1363 * @brief Get the number of DMA request that will be autorized after a generation event.
1364 * @rmtoll RGxCR GNBREQ LL_DMAMUX_GetGenRequestNb
1365 * @param DMAMUXx DMAMUXx Instance
1366 * @param RequestGenChannel This parameter can be one of the following values:
1367 * @arg @ref LL_DMAMUX_REQ_GEN_0
1368 * @arg @ref LL_DMAMUX_REQ_GEN_1
1369 * @arg @ref LL_DMAMUX_REQ_GEN_2
1370 * @arg @ref LL_DMAMUX_REQ_GEN_3
1371 * @arg @ref LL_DMAMUX_REQ_GEN_4
1372 * @arg @ref LL_DMAMUX_REQ_GEN_5
1373 * @arg @ref LL_DMAMUX_REQ_GEN_6
1374 * @arg @ref LL_DMAMUX_REQ_GEN_7
1375 * @retval Between Min_Data = 1 and Max_Data = 32
1376 */
LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1377 __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1378 {
1379 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1380
1381 return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U);
1382 }
1383
1384 /**
1385 * @brief Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.
1386 * @rmtoll RGxCR SIG_ID LL_DMAMUX_SetRequestSignalID
1387 * @param DMAMUXx DMAMUXx Instance
1388 * @param RequestGenChannel This parameter can be one of the following values:
1389 * @arg @ref LL_DMAMUX_REQ_GEN_0
1390 * @arg @ref LL_DMAMUX_REQ_GEN_1
1391 * @arg @ref LL_DMAMUX_REQ_GEN_2
1392 * @arg @ref LL_DMAMUX_REQ_GEN_3
1393 * @arg @ref LL_DMAMUX_REQ_GEN_4
1394 * @arg @ref LL_DMAMUX_REQ_GEN_5
1395 * @arg @ref LL_DMAMUX_REQ_GEN_6
1396 * @arg @ref LL_DMAMUX_REQ_GEN_7
1397 * @param RequestSignalID This parameter can be one of the following values:
1398 * @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
1399 * @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
1400 * @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
1401 * @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM1_OUT
1402 * @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM2_OUT
1403 * @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM3_OUT
1404 * @arg @ref LL_DMAMUX1_REQ_GEN_EXTI0
1405 * @arg @ref LL_DMAMUX1_REQ_GEN_TIM12_TRGO
1406 * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
1407 * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
1408 * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
1409 * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
1410 * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
1411 * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
1412 * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
1413 * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
1414 * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
1415 * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
1416 * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM2_OUT
1417 * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
1418 * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM3_OUT
1419 * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
1420 * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
1421 * @arg @ref LL_DMAMUX2_REQ_GEN_I2C4_WKUP
1422 * @arg @ref LL_DMAMUX2_REQ_GEN_SPI6_WKUP
1423 * @arg @ref LL_DMAMUX2_REQ_GEN_COMP1_OUT
1424 * @arg @ref LL_DMAMUX2_REQ_GEN_COMP2_OUT
1425 * @arg @ref LL_DMAMUX2_REQ_GEN_RTC_WKUP
1426 * @arg @ref LL_DMAMUX2_REQ_GEN_EXTI0
1427 * @arg @ref LL_DMAMUX2_REQ_GEN_EXTI2
1428 * @arg @ref LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
1429 * @arg @ref LL_DMAMUX2_REQ_GEN_SPI6_IT
1430 * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
1431 * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
1432 * @arg @ref LL_DMAMUX2_REQ_GEN_ADC3_IT
1433 * @arg @ref LL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
1434 * @arg @ref LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
1435 * @arg @ref LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
1436 * @retval None
1437 */
LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel,uint32_t RequestSignalID)1438 __STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID)
1439 {
1440 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1441
1442 MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID);
1443 }
1444
1445 /**
1446 * @brief Get DMAMUX external Request Signal ID set on DMAMUX Channel x.
1447 * @rmtoll RGxCR SIG_ID LL_DMAMUX_GetRequestSignalID
1448 * @param DMAMUXx DMAMUXx Instance
1449 * @param RequestGenChannel This parameter can be one of the following values:
1450 * @arg @ref LL_DMAMUX_REQ_GEN_0
1451 * @arg @ref LL_DMAMUX_REQ_GEN_1
1452 * @arg @ref LL_DMAMUX_REQ_GEN_2
1453 * @arg @ref LL_DMAMUX_REQ_GEN_3
1454 * @arg @ref LL_DMAMUX_REQ_GEN_4
1455 * @arg @ref LL_DMAMUX_REQ_GEN_5
1456 * @arg @ref LL_DMAMUX_REQ_GEN_6
1457 * @arg @ref LL_DMAMUX_REQ_GEN_7
1458 * @retval Returned value can be one of the following values:
1459 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
1460 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
1461 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
1462 * @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT
1463 * @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT
1464 * @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT
1465 * @arg @ref LL_DMAMUX1_SYNC_EXTI0
1466 * @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO
1467 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT
1468 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT
1469 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT
1470 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT
1471 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT
1472 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT
1473 * @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP
1474 * @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP
1475 * @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT
1476 * @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT
1477 * @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP
1478 * @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP
1479 * @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT
1480 * @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP
1481 * @arg @ref LL_DMAMUX2_SYNC_EXTI0
1482 * @arg @ref LL_DMAMUX2_SYNC_EXTI2
1483 */
LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)1484 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1485 {
1486 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1487
1488 return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID));
1489 }
1490
1491 /**
1492 * @}
1493 */
1494
1495 /** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management
1496 * @{
1497 */
1498
1499 /**
1500 * @brief Get Synchronization Event Overrun Flag Channel 0.
1501 * @rmtoll CSR SOF0 LL_DMAMUX_IsActiveFlag_SO0
1502 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1503 * @retval State of bit (1 or 0).
1504 */
LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef * DMAMUXx)1505 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
1506 {
1507 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1508
1509 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL);
1510 }
1511
1512 /**
1513 * @brief Get Synchronization Event Overrun Flag Channel 1.
1514 * @rmtoll CSR SOF1 LL_DMAMUX_IsActiveFlag_SO1
1515 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1516 * @retval State of bit (1 or 0).
1517 */
LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef * DMAMUXx)1518 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
1519 {
1520 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1521
1522 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL);
1523 }
1524
1525 /**
1526 * @brief Get Synchronization Event Overrun Flag Channel 2.
1527 * @rmtoll CSR SOF2 LL_DMAMUX_IsActiveFlag_SO2
1528 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1529 * @retval State of bit (1 or 0).
1530 */
LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef * DMAMUXx)1531 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
1532 {
1533 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1534
1535 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL);
1536 }
1537
1538 /**
1539 * @brief Get Synchronization Event Overrun Flag Channel 3.
1540 * @rmtoll CSR SOF3 LL_DMAMUX_IsActiveFlag_SO3
1541 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1542 * @retval State of bit (1 or 0).
1543 */
LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef * DMAMUXx)1544 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
1545 {
1546 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1547
1548 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL);
1549 }
1550
1551 /**
1552 * @brief Get Synchronization Event Overrun Flag Channel 4.
1553 * @rmtoll CSR SOF4 LL_DMAMUX_IsActiveFlag_SO4
1554 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1555 * @retval State of bit (1 or 0).
1556 */
LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef * DMAMUXx)1557 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
1558 {
1559 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1560
1561 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL);
1562 }
1563
1564 /**
1565 * @brief Get Synchronization Event Overrun Flag Channel 5.
1566 * @rmtoll CSR SOF5 LL_DMAMUX_IsActiveFlag_SO5
1567 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1568 * @retval State of bit (1 or 0).
1569 */
LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef * DMAMUXx)1570 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
1571 {
1572 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1573
1574 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL);
1575 }
1576
1577 /**
1578 * @brief Get Synchronization Event Overrun Flag Channel 6.
1579 * @rmtoll CSR SOF6 LL_DMAMUX_IsActiveFlag_SO6
1580 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1581 * @retval State of bit (1 or 0).
1582 */
LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef * DMAMUXx)1583 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
1584 {
1585 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1586
1587 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL);
1588 }
1589
1590 /**
1591 * @brief Get Synchronization Event Overrun Flag Channel 7.
1592 * @rmtoll CSR SOF7 LL_DMAMUX_IsActiveFlag_SO7
1593 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1594 * @retval State of bit (1 or 0).
1595 */
LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef * DMAMUXx)1596 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
1597 {
1598 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1599
1600 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL);
1601 }
1602
1603 /**
1604 * @brief Get Synchronization Event Overrun Flag Channel 8.
1605 * @rmtoll CSR SOF8 LL_DMAMUX_IsActiveFlag_SO8
1606 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1607 * @retval State of bit (1 or 0).
1608 */
LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef * DMAMUXx)1609 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
1610 {
1611 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1612
1613 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL);
1614 }
1615
1616 /**
1617 * @brief Get Synchronization Event Overrun Flag Channel 9.
1618 * @rmtoll CSR SOF9 LL_DMAMUX_IsActiveFlag_SO9
1619 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1620 * @retval State of bit (1 or 0).
1621 */
LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef * DMAMUXx)1622 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
1623 {
1624 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1625
1626 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL);
1627 }
1628
1629 /**
1630 * @brief Get Synchronization Event Overrun Flag Channel 10.
1631 * @rmtoll CSR SOF10 LL_DMAMUX_IsActiveFlag_SO10
1632 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1633 * @retval State of bit (1 or 0).
1634 */
LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef * DMAMUXx)1635 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
1636 {
1637 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1638
1639 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL);
1640 }
1641
1642 /**
1643 * @brief Get Synchronization Event Overrun Flag Channel 11.
1644 * @rmtoll CSR SOF11 LL_DMAMUX_IsActiveFlag_SO11
1645 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1646 * @retval State of bit (1 or 0).
1647 */
LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef * DMAMUXx)1648 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
1649 {
1650 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1651
1652 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL);
1653 }
1654
1655 /**
1656 * @brief Get Synchronization Event Overrun Flag Channel 12.
1657 * @rmtoll CSR SOF12 LL_DMAMUX_IsActiveFlag_SO12
1658 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1659 * @retval State of bit (1 or 0).
1660 */
LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef * DMAMUXx)1661 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
1662 {
1663 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1664
1665 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL);
1666 }
1667
1668 /**
1669 * @brief Get Synchronization Event Overrun Flag Channel 13.
1670 * @rmtoll CSR SOF13 LL_DMAMUX_IsActiveFlag_SO13
1671 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1672 * @retval State of bit (1 or 0).
1673 */
LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef * DMAMUXx)1674 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
1675 {
1676 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1677
1678 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL);
1679 }
1680
1681 /**
1682 * @brief Get Synchronization Event Overrun Flag Channel 14.
1683 * @rmtoll CSR SOF14 LL_DMAMUX_IsActiveFlag_SO14
1684 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1685 * @retval State of bit (1 or 0).
1686 */
LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef * DMAMUXx)1687 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
1688 {
1689 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1690
1691 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF14) == (DMAMUX_CSR_SOF14)) ? 1UL : 0UL);
1692 }
1693
1694 /**
1695 * @brief Get Synchronization Event Overrun Flag Channel 15.
1696 * @rmtoll CSR SOF15 LL_DMAMUX_IsActiveFlag_SO15
1697 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1698 * @retval State of bit (1 or 0).
1699 */
LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef * DMAMUXx)1700 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
1701 {
1702 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1703
1704 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF15) == (DMAMUX_CSR_SOF15)) ? 1UL : 0UL);
1705 }
1706
1707 /**
1708 * @brief Get Request Generator 0 Trigger Event Overrun Flag.
1709 * @rmtoll RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0
1710 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1711 * @retval State of bit (1 or 0).
1712 */
LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef * DMAMUXx)1713 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
1714 {
1715 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1716
1717 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL);
1718 }
1719
1720 /**
1721 * @brief Get Request Generator 1 Trigger Event Overrun Flag.
1722 * @rmtoll RGSR OF1 LL_DMAMUX_IsActiveFlag_RGO1
1723 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1724 * @retval State of bit (1 or 0).
1725 */
LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef * DMAMUXx)1726 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
1727 {
1728 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1729
1730 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL);
1731 }
1732
1733 /**
1734 * @brief Get Request Generator 2 Trigger Event Overrun Flag.
1735 * @rmtoll RGSR OF2 LL_DMAMUX_IsActiveFlag_RGO2
1736 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1737 * @retval State of bit (1 or 0).
1738 */
LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef * DMAMUXx)1739 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
1740 {
1741 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1742
1743 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL);
1744 }
1745
1746 /**
1747 * @brief Get Request Generator 3 Trigger Event Overrun Flag.
1748 * @rmtoll RGSR OF3 LL_DMAMUX_IsActiveFlag_RGO3
1749 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1750 * @retval State of bit (1 or 0).
1751 */
LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef * DMAMUXx)1752 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
1753 {
1754 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1755
1756 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL);
1757 }
1758
1759 /**
1760 * @brief Get Request Generator 4 Trigger Event Overrun Flag.
1761 * @rmtoll RGSR OF4 LL_DMAMUX_IsActiveFlag_RGO4
1762 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1763 * @retval State of bit (1 or 0).
1764 */
LL_DMAMUX_IsActiveFlag_RGO4(DMAMUX_Channel_TypeDef * DMAMUXx)1765 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx)
1766 {
1767 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1768
1769 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF4) == (DMAMUX_RGSR_OF4)) ? 1UL : 0UL);
1770 }
1771
1772 /**
1773 * @brief Get Request Generator 5 Trigger Event Overrun Flag.
1774 * @rmtoll RGSR OF5 LL_DMAMUX_IsActiveFlag_RGO5
1775 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1776 * @retval State of bit (1 or 0).
1777 */
LL_DMAMUX_IsActiveFlag_RGO5(DMAMUX_Channel_TypeDef * DMAMUXx)1778 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx)
1779 {
1780 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1781
1782 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF5) == (DMAMUX_RGSR_OF5)) ? 1UL : 0UL);
1783 }
1784
1785 /**
1786 * @brief Get Request Generator 6 Trigger Event Overrun Flag.
1787 * @rmtoll RGSR OF6 LL_DMAMUX_IsActiveFlag_RGO6
1788 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1789 * @retval State of bit (1 or 0).
1790 */
LL_DMAMUX_IsActiveFlag_RGO6(DMAMUX_Channel_TypeDef * DMAMUXx)1791 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx)
1792 {
1793 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1794
1795 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF6) == (DMAMUX_RGSR_OF6)) ? 1UL : 0UL);
1796 }
1797
1798 /**
1799 * @brief Get Request Generator 7 Trigger Event Overrun Flag.
1800 * @rmtoll RGSR OF7 LL_DMAMUX_IsActiveFlag_RGO7
1801 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1802 * @retval State of bit (1 or 0).
1803 */
LL_DMAMUX_IsActiveFlag_RGO7(DMAMUX_Channel_TypeDef * DMAMUXx)1804 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx)
1805 {
1806 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1807
1808 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF7) == (DMAMUX_RGSR_OF7)) ? 1UL : 0UL);
1809 }
1810
1811 /**
1812 * @brief Clear Synchronization Event Overrun Flag Channel 0.
1813 * @rmtoll CFR CSOF0 LL_DMAMUX_ClearFlag_SO0
1814 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1815 * @retval None
1816 */
LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef * DMAMUXx)1817 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
1818 {
1819 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1820
1821 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF0);
1822 }
1823
1824 /**
1825 * @brief Clear Synchronization Event Overrun Flag Channel 1.
1826 * @rmtoll CFR CSOF1 LL_DMAMUX_ClearFlag_SO1
1827 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1828 * @retval None
1829 */
LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef * DMAMUXx)1830 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
1831 {
1832 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1833
1834 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF1);
1835 }
1836
1837 /**
1838 * @brief Clear Synchronization Event Overrun Flag Channel 2.
1839 * @rmtoll CFR CSOF2 LL_DMAMUX_ClearFlag_SO2
1840 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1841 * @retval None
1842 */
LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef * DMAMUXx)1843 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
1844 {
1845 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1846
1847 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF2);
1848 }
1849
1850 /**
1851 * @brief Clear Synchronization Event Overrun Flag Channel 3.
1852 * @rmtoll CFR CSOF3 LL_DMAMUX_ClearFlag_SO3
1853 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1854 * @retval None
1855 */
LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef * DMAMUXx)1856 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
1857 {
1858 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1859
1860 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF3);
1861 }
1862
1863 /**
1864 * @brief Clear Synchronization Event Overrun Flag Channel 4.
1865 * @rmtoll CFR CSOF4 LL_DMAMUX_ClearFlag_SO4
1866 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1867 * @retval None
1868 */
LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef * DMAMUXx)1869 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
1870 {
1871 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1872
1873 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF4);
1874 }
1875
1876 /**
1877 * @brief Clear Synchronization Event Overrun Flag Channel 5.
1878 * @rmtoll CFR CSOF5 LL_DMAMUX_ClearFlag_SO5
1879 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1880 * @retval None
1881 */
LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef * DMAMUXx)1882 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
1883 {
1884 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1885
1886 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF5);
1887 }
1888
1889 /**
1890 * @brief Clear Synchronization Event Overrun Flag Channel 6.
1891 * @rmtoll CFR CSOF6 LL_DMAMUX_ClearFlag_SO6
1892 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1893 * @retval None
1894 */
LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef * DMAMUXx)1895 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
1896 {
1897 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1898
1899 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF6);
1900 }
1901
1902 /**
1903 * @brief Clear Synchronization Event Overrun Flag Channel 7.
1904 * @rmtoll CFR CSOF7 LL_DMAMUX_ClearFlag_SO7
1905 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1906 * @retval None
1907 */
LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef * DMAMUXx)1908 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
1909 {
1910 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1911
1912 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF7);
1913 }
1914
1915 /**
1916 * @brief Clear Synchronization Event Overrun Flag Channel 8.
1917 * @rmtoll CFR CSOF8 LL_DMAMUX_ClearFlag_SO8
1918 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1919 * @retval None
1920 */
LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef * DMAMUXx)1921 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
1922 {
1923 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1924
1925 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF8);
1926 }
1927
1928 /**
1929 * @brief Clear Synchronization Event Overrun Flag Channel 9.
1930 * @rmtoll CFR CSOF9 LL_DMAMUX_ClearFlag_SO9
1931 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1932 * @retval None
1933 */
LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef * DMAMUXx)1934 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
1935 {
1936 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1937
1938 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF9);
1939 }
1940
1941 /**
1942 * @brief Clear Synchronization Event Overrun Flag Channel 10.
1943 * @rmtoll CFR CSOF10 LL_DMAMUX_ClearFlag_SO10
1944 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1945 * @retval None
1946 */
LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef * DMAMUXx)1947 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
1948 {
1949 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1950
1951 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF10);
1952 }
1953
1954 /**
1955 * @brief Clear Synchronization Event Overrun Flag Channel 11.
1956 * @rmtoll CFR CSOF11 LL_DMAMUX_ClearFlag_SO11
1957 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1958 * @retval None
1959 */
LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef * DMAMUXx)1960 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
1961 {
1962 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1963
1964 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF11);
1965 }
1966
1967 /**
1968 * @brief Clear Synchronization Event Overrun Flag Channel 12.
1969 * @rmtoll CFR CSOF12 LL_DMAMUX_ClearFlag_SO12
1970 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1971 * @retval None
1972 */
LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef * DMAMUXx)1973 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
1974 {
1975 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1976
1977 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF12);
1978 }
1979
1980 /**
1981 * @brief Clear Synchronization Event Overrun Flag Channel 13.
1982 * @rmtoll CFR CSOF13 LL_DMAMUX_ClearFlag_SO13
1983 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1984 * @retval None
1985 */
LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef * DMAMUXx)1986 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
1987 {
1988 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1989
1990 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF13);
1991 }
1992
1993 /**
1994 * @brief Clear Synchronization Event Overrun Flag Channel 14.
1995 * @rmtoll CFR CSOF14 LL_DMAMUX_ClearFlag_SO14
1996 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1997 * @retval None
1998 */
LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef * DMAMUXx)1999 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
2000 {
2001 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2002
2003 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF14);
2004 }
2005
2006 /**
2007 * @brief Clear Synchronization Event Overrun Flag Channel 15.
2008 * @rmtoll CFR CSOF15 LL_DMAMUX_ClearFlag_SO15
2009 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2010 * @retval None
2011 */
LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef * DMAMUXx)2012 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
2013 {
2014 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2015
2016 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF15);
2017 }
2018
2019 /**
2020 * @brief Clear Request Generator 0 Trigger Event Overrun Flag.
2021 * @rmtoll RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0
2022 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2023 * @retval None
2024 */
LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef * DMAMUXx)2025 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
2026 {
2027 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2028
2029 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF0);
2030 }
2031
2032 /**
2033 * @brief Clear Request Generator 1 Trigger Event Overrun Flag.
2034 * @rmtoll RGCFR COF1 LL_DMAMUX_ClearFlag_RGO1
2035 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2036 * @retval None
2037 */
LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef * DMAMUXx)2038 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
2039 {
2040 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2041
2042 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF1);
2043 }
2044
2045 /**
2046 * @brief Clear Request Generator 2 Trigger Event Overrun Flag.
2047 * @rmtoll RGCFR COF2 LL_DMAMUX_ClearFlag_RGO2
2048 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2049 * @retval None
2050 */
LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef * DMAMUXx)2051 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
2052 {
2053 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2054
2055 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF2);
2056 }
2057
2058 /**
2059 * @brief Clear Request Generator 3 Trigger Event Overrun Flag.
2060 * @rmtoll RGCFR COF3 LL_DMAMUX_ClearFlag_RGO3
2061 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2062 * @retval None
2063 */
LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef * DMAMUXx)2064 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
2065 {
2066 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2067
2068 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF3);
2069 }
2070
2071 /**
2072 * @brief Clear Request Generator 4 Trigger Event Overrun Flag.
2073 * @rmtoll RGCFR COF4 LL_DMAMUX_ClearFlag_RGO4
2074 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2075 * @retval None
2076 */
LL_DMAMUX_ClearFlag_RGO4(DMAMUX_Channel_TypeDef * DMAMUXx)2077 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx)
2078 {
2079 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2080
2081 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF4);
2082 }
2083
2084 /**
2085 * @brief Clear Request Generator 5 Trigger Event Overrun Flag.
2086 * @rmtoll RGCFR COF5 LL_DMAMUX_ClearFlag_RGO5
2087 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2088 * @retval None
2089 */
LL_DMAMUX_ClearFlag_RGO5(DMAMUX_Channel_TypeDef * DMAMUXx)2090 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx)
2091 {
2092 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2093
2094 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF5);
2095 }
2096
2097 /**
2098 * @brief Clear Request Generator 6 Trigger Event Overrun Flag.
2099 * @rmtoll RGCFR COF6 LL_DMAMUX_ClearFlag_RGO6
2100 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2101 * @retval None
2102 */
LL_DMAMUX_ClearFlag_RGO6(DMAMUX_Channel_TypeDef * DMAMUXx)2103 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx)
2104 {
2105 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2106
2107 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF6);
2108 }
2109
2110 /**
2111 * @brief Clear Request Generator 7 Trigger Event Overrun Flag.
2112 * @rmtoll RGCFR COF7 LL_DMAMUX_ClearFlag_RGO7
2113 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2114 * @retval None
2115 */
LL_DMAMUX_ClearFlag_RGO7(DMAMUX_Channel_TypeDef * DMAMUXx)2116 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx)
2117 {
2118 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2119
2120 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF7);
2121 }
2122
2123 /**
2124 * @}
2125 */
2126
2127 /** @defgroup DMAMUX_LL_EF_IT_Management IT_Management
2128 * @{
2129 */
2130
2131 /**
2132 * @brief Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
2133 * @rmtoll CxCR SOIE LL_DMAMUX_EnableIT_SO
2134 * @param DMAMUXx DMAMUXx Instance
2135 * @param Channel This parameter can be one of the following values:
2136 * @arg @ref LL_DMAMUX_CHANNEL_0
2137 * @arg @ref LL_DMAMUX_CHANNEL_1
2138 * @arg @ref LL_DMAMUX_CHANNEL_2
2139 * @arg @ref LL_DMAMUX_CHANNEL_3
2140 * @arg @ref LL_DMAMUX_CHANNEL_4
2141 * @arg @ref LL_DMAMUX_CHANNEL_5
2142 * @arg @ref LL_DMAMUX_CHANNEL_6
2143 * @arg @ref LL_DMAMUX_CHANNEL_7
2144 * @arg @ref LL_DMAMUX_CHANNEL_8
2145 * @arg @ref LL_DMAMUX_CHANNEL_9
2146 * @arg @ref LL_DMAMUX_CHANNEL_10
2147 * @arg @ref LL_DMAMUX_CHANNEL_11
2148 * @arg @ref LL_DMAMUX_CHANNEL_12
2149 * @arg @ref LL_DMAMUX_CHANNEL_13
2150 * @arg @ref LL_DMAMUX_CHANNEL_14
2151 * @arg @ref LL_DMAMUX_CHANNEL_15
2152 * @retval None
2153 */
LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)2154 __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
2155 {
2156 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2157
2158 SET_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE);
2159 }
2160
2161 /**
2162 * @brief Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
2163 * @rmtoll CxCR SOIE LL_DMAMUX_DisableIT_SO
2164 * @param DMAMUXx DMAMUXx Instance
2165 * @param Channel This parameter can be one of the following values:
2166 * @arg @ref LL_DMAMUX_CHANNEL_0
2167 * @arg @ref LL_DMAMUX_CHANNEL_1
2168 * @arg @ref LL_DMAMUX_CHANNEL_2
2169 * @arg @ref LL_DMAMUX_CHANNEL_3
2170 * @arg @ref LL_DMAMUX_CHANNEL_4
2171 * @arg @ref LL_DMAMUX_CHANNEL_5
2172 * @arg @ref LL_DMAMUX_CHANNEL_6
2173 * @arg @ref LL_DMAMUX_CHANNEL_7
2174 * @arg @ref LL_DMAMUX_CHANNEL_8
2175 * @arg @ref LL_DMAMUX_CHANNEL_9
2176 * @arg @ref LL_DMAMUX_CHANNEL_10
2177 * @arg @ref LL_DMAMUX_CHANNEL_11
2178 * @arg @ref LL_DMAMUX_CHANNEL_12
2179 * @arg @ref LL_DMAMUX_CHANNEL_13
2180 * @arg @ref LL_DMAMUX_CHANNEL_14
2181 * @arg @ref LL_DMAMUX_CHANNEL_15
2182 * @retval None
2183 */
LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)2184 __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
2185 {
2186 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2187
2188 CLEAR_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE);
2189 }
2190
2191 /**
2192 * @brief Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
2193 * @rmtoll CxCR SOIE LL_DMAMUX_IsEnabledIT_SO
2194 * @param DMAMUXx DMAMUXx Instance
2195 * @param Channel This parameter can be one of the following values:
2196 * @arg @ref LL_DMAMUX_CHANNEL_0
2197 * @arg @ref LL_DMAMUX_CHANNEL_1
2198 * @arg @ref LL_DMAMUX_CHANNEL_2
2199 * @arg @ref LL_DMAMUX_CHANNEL_3
2200 * @arg @ref LL_DMAMUX_CHANNEL_4
2201 * @arg @ref LL_DMAMUX_CHANNEL_5
2202 * @arg @ref LL_DMAMUX_CHANNEL_6
2203 * @arg @ref LL_DMAMUX_CHANNEL_7
2204 * @arg @ref LL_DMAMUX_CHANNEL_8
2205 * @arg @ref LL_DMAMUX_CHANNEL_9
2206 * @arg @ref LL_DMAMUX_CHANNEL_10
2207 * @arg @ref LL_DMAMUX_CHANNEL_11
2208 * @arg @ref LL_DMAMUX_CHANNEL_12
2209 * @arg @ref LL_DMAMUX_CHANNEL_13
2210 * @arg @ref LL_DMAMUX_CHANNEL_14
2211 * @arg @ref LL_DMAMUX_CHANNEL_15
2212 * @retval State of bit (1 or 0).
2213 */
LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t Channel)2214 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
2215 {
2216 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2217
2218 return (READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SOIE));
2219 }
2220
2221 /**
2222 * @brief Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
2223 * @rmtoll RGxCR OIE LL_DMAMUX_EnableIT_RGO
2224 * @param DMAMUXx DMAMUXx Instance
2225 * @param RequestGenChannel This parameter can be one of the following values:
2226 * @arg @ref LL_DMAMUX_REQ_GEN_0
2227 * @arg @ref LL_DMAMUX_REQ_GEN_1
2228 * @arg @ref LL_DMAMUX_REQ_GEN_2
2229 * @arg @ref LL_DMAMUX_REQ_GEN_3
2230 * @arg @ref LL_DMAMUX_REQ_GEN_4
2231 * @arg @ref LL_DMAMUX_REQ_GEN_5
2232 * @arg @ref LL_DMAMUX_REQ_GEN_6
2233 * @arg @ref LL_DMAMUX_REQ_GEN_7
2234 * @retval None
2235 */
LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)2236 __STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
2237 {
2238 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2239
2240 SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE);
2241 }
2242
2243 /**
2244 * @brief Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
2245 * @rmtoll RGxCR OIE LL_DMAMUX_DisableIT_RGO
2246 * @param DMAMUXx DMAMUXx Instance
2247 * @param RequestGenChannel This parameter can be one of the following values:
2248 * @arg @ref LL_DMAMUX_REQ_GEN_0
2249 * @arg @ref LL_DMAMUX_REQ_GEN_1
2250 * @arg @ref LL_DMAMUX_REQ_GEN_2
2251 * @arg @ref LL_DMAMUX_REQ_GEN_3
2252 * @arg @ref LL_DMAMUX_REQ_GEN_4
2253 * @arg @ref LL_DMAMUX_REQ_GEN_5
2254 * @arg @ref LL_DMAMUX_REQ_GEN_6
2255 * @arg @ref LL_DMAMUX_REQ_GEN_7
2256 * @retval None
2257 */
LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)2258 __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
2259 {
2260 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2261
2262 CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE);
2263 }
2264
2265 /**
2266 * @brief Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
2267 * @rmtoll RGxCR OIE LL_DMAMUX_IsEnabledIT_RGO
2268 * @param DMAMUXx DMAMUXx Instance
2269 * @param RequestGenChannel This parameter can be one of the following values:
2270 * @arg @ref LL_DMAMUX_REQ_GEN_0
2271 * @arg @ref LL_DMAMUX_REQ_GEN_1
2272 * @arg @ref LL_DMAMUX_REQ_GEN_2
2273 * @arg @ref LL_DMAMUX_REQ_GEN_3
2274 * @arg @ref LL_DMAMUX_REQ_GEN_4
2275 * @arg @ref LL_DMAMUX_REQ_GEN_5
2276 * @arg @ref LL_DMAMUX_REQ_GEN_6
2277 * @arg @ref LL_DMAMUX_REQ_GEN_7
2278 * @retval State of bit (1 or 0).
2279 */
LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef * DMAMUXx,uint32_t RequestGenChannel)2280 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
2281 {
2282 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2283
2284 return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL);
2285 }
2286
2287 /**
2288 * @}
2289 */
2290
2291 /**
2292 * @}
2293 */
2294
2295 /**
2296 * @}
2297 */
2298
2299 #endif /* DMAMUX1 || DMAMUX2 */
2300
2301 /**
2302 * @}
2303 */
2304
2305 #ifdef __cplusplus
2306 }
2307 #endif
2308
2309 #endif /* __STM32H7xx_LL_DMAMUX_H */
2310
2311 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
2312