1 /**************************************************************************//**
2 * @file core_cm0.h
3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
4 * @version V3.00
5 * @date 27. January 2012
6 *
7 * @note
8 * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
9 *
10 * @par
11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
12 * processor based microcontrollers. This file can be freely distributed
13 * within development tools that are supporting such ARM based processors.
14 *
15 * @par
16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
21 *
22 ******************************************************************************/
23 #if defined ( __ICCARM__ )
24 #pragma system_include /* treat file as system include file for MISRA check */
25 #endif
26
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30
31 #ifndef __CORE_CM0_H_GENERIC
32 #define __CORE_CM0_H_GENERIC
33
34 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
35 CMSIS violates the following MISRA-C:2004 rules:
36
37 \li Required Rule 8.5, object/function definition in header file.<br>
38 Function definitions in header files are used to allow 'inlining'.
39
40 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
41 Unions are used for effective representation of core registers.
42
43 \li Advisory Rule 19.7, Function-like macro defined.<br>
44 Function-like macros are used to allow more efficient code.
45 */
46
47
48 /*******************************************************************************
49 * CMSIS definitions
50 ******************************************************************************/
51 /** \ingroup Cortex_M0
52 @{
53 */
54
55 /* CMSIS CM0 definitions */
56 #define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
57 #define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
58 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
59 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
60
61 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
62
63
64 #if defined ( __CC_ARM )
65 #define __ASM __asm /*!< asm keyword for ARM Compiler */
66 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
67 #define __STATIC_INLINE static __inline
68
69 #elif defined ( __ICCARM__ )
70 #define __ASM __asm /*!< asm keyword for IAR Compiler */
71 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
72 #define __STATIC_INLINE static inline
73
74 #elif defined ( __GNUC__ )
75 #define __ASM __asm /*!< asm keyword for GNU Compiler */
76 #define __INLINE inline /*!< inline keyword for GNU Compiler */
77 #define __STATIC_INLINE static inline
78
79 #elif defined ( __TASKING__ )
80 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
81 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
82 #define __STATIC_INLINE static inline
83
84 #endif
85
86 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
87 */
88 #define __FPU_USED 0
89
90 #if defined ( __CC_ARM )
91 #if defined __TARGET_FPU_VFP
92 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
93 #endif
94
95 #elif defined ( __ICCARM__ )
96 #if defined __ARMVFP__
97 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
98 #endif
99
100 #elif defined ( __GNUC__ )
101 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
102 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
103 #endif
104
105 #elif defined ( __TASKING__ )
106 /* add preprocessor checks */
107 #endif
108
109 #include <stdint.h> /* standard types definitions */
110 #include <core_cmInstr.h> /* Core Instruction Access */
111 #include <core_cmFunc.h> /* Core Function Access */
112
113 #endif /* __CORE_CM0_H_GENERIC */
114
115 #ifndef __CMSIS_GENERIC
116
117 #ifndef __CORE_CM0_H_DEPENDANT
118 #define __CORE_CM0_H_DEPENDANT
119
120 /* check device defines and use defaults */
121 #if defined __CHECK_DEVICE_DEFINES
122 #ifndef __CM0_REV
123 #define __CM0_REV 0x0000
124 #warning "__CM0_REV not defined in device header file; using default!"
125 #endif
126
127 #ifndef __NVIC_PRIO_BITS
128 #define __NVIC_PRIO_BITS 2
129 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
130 #endif
131
132 #ifndef __Vendor_SysTickConfig
133 #define __Vendor_SysTickConfig 0
134 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
135 #endif
136 #endif
137
138 /* IO definitions (access restrictions to peripheral registers) */
139 /**
140 \defgroup CMSIS_glob_defs CMSIS Global Defines
141
142 <strong>IO Type Qualifiers</strong> are used
143 \li to specify the access to peripheral variables.
144 \li for automatic generation of peripheral register debug information.
145 */
146 #ifdef __cplusplus
147 #define __I volatile /*!< Defines 'read only' permissions */
148 #else
149 #define __I volatile const /*!< Defines 'read only' permissions */
150 #endif
151 #define __O volatile /*!< Defines 'write only' permissions */
152 #define __IO volatile /*!< Defines 'read / write' permissions */
153
154 /*@} end of group Cortex_M0 */
155
156
157
158 /*******************************************************************************
159 * Register Abstraction
160 Core Register contain:
161 - Core Register
162 - Core NVIC Register
163 - Core SCB Register
164 - Core SysTick Register
165 ******************************************************************************/
166 /** \defgroup CMSIS_core_register Defines and Type Definitions
167 \brief Type definitions and defines for Cortex-M processor based devices.
168 */
169
170 /** \ingroup CMSIS_core_register
171 \defgroup CMSIS_CORE Status and Control Registers
172 \brief Core Register type definitions.
173 @{
174 */
175
176 /** \brief Union type to access the Application Program Status Register (APSR).
177 */
178 typedef union
179 {
180 struct
181 {
182 #if (__CORTEX_M != 0x04)
183 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
184 #else
185 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
186 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
187 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
188 #endif
189 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
190 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
191 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
192 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
193 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
194 } b; /*!< Structure used for bit access */
195 uint32_t w; /*!< Type used for word access */
196 } APSR_Type;
197
198
199 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
200 */
201 typedef union
202 {
203 struct
204 {
205 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
206 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
207 } b; /*!< Structure used for bit access */
208 uint32_t w; /*!< Type used for word access */
209 } IPSR_Type;
210
211
212 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
213 */
214 typedef union
215 {
216 struct
217 {
218 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
219 #if (__CORTEX_M != 0x04)
220 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
221 #else
222 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
223 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
224 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
225 #endif
226 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
227 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
228 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
229 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
230 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
231 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
232 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
233 } b; /*!< Structure used for bit access */
234 uint32_t w; /*!< Type used for word access */
235 } xPSR_Type;
236
237
238 /** \brief Union type to access the Control Registers (CONTROL).
239 */
240 typedef union
241 {
242 struct
243 {
244 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
245 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
246 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
247 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
248 } b; /*!< Structure used for bit access */
249 uint32_t w; /*!< Type used for word access */
250 } CONTROL_Type;
251
252 /*@} end of group CMSIS_CORE */
253
254
255 /** \ingroup CMSIS_core_register
256 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
257 \brief Type definitions for the NVIC Registers
258 @{
259 */
260
261 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
262 */
263 typedef struct
264 {
265 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
266 uint32_t RESERVED0[31];
267 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
268 uint32_t RSERVED1[31];
269 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
270 uint32_t RESERVED2[31];
271 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
272 uint32_t RESERVED3[31];
273 uint32_t RESERVED4[64];
274 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
275 } NVIC_Type;
276
277 /*@} end of group CMSIS_NVIC */
278
279
280 /** \ingroup CMSIS_core_register
281 \defgroup CMSIS_SCB System Control Block (SCB)
282 \brief Type definitions for the System Control Block Registers
283 @{
284 */
285
286 /** \brief Structure type to access the System Control Block (SCB).
287 */
288 typedef struct
289 {
290 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
291 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
292 uint32_t RESERVED0;
293 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
294 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
295 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
296 uint32_t RESERVED1;
297 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
298 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
299 } SCB_Type;
300
301 /* SCB CPUID Register Definitions */
302 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
303 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
304
305 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
306 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
307
308 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
309 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
310
311 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
312 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
313
314 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
315 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
316
317 /* SCB Interrupt Control State Register Definitions */
318 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
319 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
320
321 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
322 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
323
324 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
325 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
326
327 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
328 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
329
330 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
331 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
332
333 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
334 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
335
336 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
337 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
338
339 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
340 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
341
342 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
343 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
344
345 /* SCB Application Interrupt and Reset Control Register Definitions */
346 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
347 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
348
349 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
350 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
351
352 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
353 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
354
355 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
356 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
357
358 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
359 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
360
361 /* SCB System Control Register Definitions */
362 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
363 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
364
365 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
366 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
367
368 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
369 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
370
371 /* SCB Configuration Control Register Definitions */
372 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
373 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
374
375 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
376 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
377
378 /* SCB System Handler Control and State Register Definitions */
379 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
380 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
381
382 /*@} end of group CMSIS_SCB */
383
384
385 /** \ingroup CMSIS_core_register
386 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
387 \brief Type definitions for the System Timer Registers.
388 @{
389 */
390
391 /** \brief Structure type to access the System Timer (SysTick).
392 */
393 typedef struct
394 {
395 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
396 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
397 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
398 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
399 } SysTick_Type;
400
401 /* SysTick Control / Status Register Definitions */
402 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
403 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
404
405 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
406 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
407
408 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
409 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
410
411 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
412 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
413
414 /* SysTick Reload Register Definitions */
415 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
416 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
417
418 /* SysTick Current Register Definitions */
419 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
420 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
421
422 /* SysTick Calibration Register Definitions */
423 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
424 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
425
426 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
427 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
428
429 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
430 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
431
432 /*@} end of group CMSIS_SysTick */
433
434
435 /** \ingroup CMSIS_core_register
436 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
437 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
438 are only accessible over DAP and not via processor. Therefore
439 they are not covered by the Cortex-M0 header file.
440 @{
441 */
442 /*@} end of group CMSIS_CoreDebug */
443
444
445 /** \ingroup CMSIS_core_register
446 \defgroup CMSIS_core_base Core Definitions
447 \brief Definitions for base addresses, unions, and structures.
448 @{
449 */
450
451 /* Memory mapping of Cortex-M0 Hardware */
452 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
453 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
454 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
455 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
456
457 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
458 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
459 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
460
461
462 /*@} */
463
464
465
466 /*******************************************************************************
467 * Hardware Abstraction Layer
468 Core Function Interface contains:
469 - Core NVIC Functions
470 - Core SysTick Functions
471 - Core Register Access Functions
472 ******************************************************************************/
473 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
474 */
475
476
477
478 /* ########################## NVIC functions #################################### */
479 /** \ingroup CMSIS_Core_FunctionInterface
480 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
481 \brief Functions that manage interrupts and exceptions via the NVIC.
482 @{
483 */
484
485 /* Interrupt Priorities are WORD accessible only under ARMv6M */
486 /* The following MACROS handle generation of the register offset and byte masks */
487 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
488 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
489 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
490
491
492 /** \brief Enable External Interrupt
493
494 The function enables a device-specific interrupt in the NVIC interrupt controller.
495
496 \param [in] IRQn External interrupt number. Value cannot be negative.
497 */
NVIC_EnableIRQ(IRQn_Type IRQn)498 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
499 {
500 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
501 }
502
503
504 /** \brief Disable External Interrupt
505
506 The function disables a device-specific interrupt in the NVIC interrupt controller.
507
508 \param [in] IRQn External interrupt number. Value cannot be negative.
509 */
NVIC_DisableIRQ(IRQn_Type IRQn)510 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
511 {
512 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
513 }
514
515
516 /** \brief Get Pending Interrupt
517
518 The function reads the pending register in the NVIC and returns the pending bit
519 for the specified interrupt.
520
521 \param [in] IRQn Interrupt number.
522
523 \return 0 Interrupt status is not pending.
524 \return 1 Interrupt status is pending.
525 */
NVIC_GetPendingIRQ(IRQn_Type IRQn)526 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
527 {
528 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
529 }
530
531
532 /** \brief Set Pending Interrupt
533
534 The function sets the pending bit of an external interrupt.
535
536 \param [in] IRQn Interrupt number. Value cannot be negative.
537 */
NVIC_SetPendingIRQ(IRQn_Type IRQn)538 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
539 {
540 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
541 }
542
543
544 /** \brief Clear Pending Interrupt
545
546 The function clears the pending bit of an external interrupt.
547
548 \param [in] IRQn External interrupt number. Value cannot be negative.
549 */
NVIC_ClearPendingIRQ(IRQn_Type IRQn)550 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
551 {
552 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
553 }
554
555
556 /** \brief Set Interrupt Priority
557
558 The function sets the priority of an interrupt.
559
560 \note The priority cannot be set for every core interrupt.
561
562 \param [in] IRQn Interrupt number.
563 \param [in] priority Priority to set.
564 */
NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)565 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
566 {
567 if(IRQn < 0) {
568 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
569 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
570 else {
571 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
572 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
573 }
574
575
576 /** \brief Get Interrupt Priority
577
578 The function reads the priority of an interrupt. The interrupt
579 number can be positive to specify an external (device specific)
580 interrupt, or negative to specify an internal (core) interrupt.
581
582
583 \param [in] IRQn Interrupt number.
584 \return Interrupt Priority. Value is aligned automatically to the implemented
585 priority bits of the microcontroller.
586 */
NVIC_GetPriority(IRQn_Type IRQn)587 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
588 {
589
590 if(IRQn < 0) {
591 return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
592 else {
593 return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
594 }
595
596
597 /** \brief System Reset
598
599 The function initiates a system reset request to reset the MCU.
600 */
NVIC_SystemReset(void)601 __STATIC_INLINE void NVIC_SystemReset(void)
602 {
603 __DSB(); /* Ensure all outstanding memory accesses included
604 buffered write are completed before reset */
605 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
606 SCB_AIRCR_SYSRESETREQ_Msk);
607 __DSB(); /* Ensure completion of memory access */
608 while(1); /* wait until reset */
609 }
610
611 /*@} end of CMSIS_Core_NVICFunctions */
612
613
614
615 /* ################################## SysTick function ############################################ */
616 /** \ingroup CMSIS_Core_FunctionInterface
617 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
618 \brief Functions that configure the System.
619 @{
620 */
621
622 #if (__Vendor_SysTickConfig == 0)
623
624 /** \brief System Tick Configuration
625
626 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
627 Counter is in free running mode to generate periodic interrupts.
628
629 \param [in] ticks Number of ticks between two interrupts.
630
631 \return 0 Function succeeded.
632 \return 1 Function failed.
633
634 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
635 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
636 must contain a vendor-specific implementation of this function.
637
638 */
SysTick_Config(uint32_t ticks)639 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
640 {
641 if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
642
643 SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
644 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
645 SysTick->VAL = 0; /* Load the SysTick Counter Value */
646 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
647 SysTick_CTRL_TICKINT_Msk |
648 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
649 return (0); /* Function successful */
650 }
651
652 #endif
653
654 /*@} end of CMSIS_Core_SysTickFunctions */
655
656
657
658
659 #endif /* __CORE_CM0_H_DEPENDANT */
660
661 #endif /* __CMSIS_GENERIC */
662
663 #ifdef __cplusplus
664 }
665 #endif
666