1 /**************************************************************************//**
2 * @file core_sc300.h
3 * @brief CMSIS SC300 Core Peripheral Access Layer Header File
4 * @version V3.00
5 * @date 03. February 2012
6 *
7 * @note
8 * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
9 *
10 * @par
11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
12 * processor based microcontrollers. This file can be freely distributed
13 * within development tools that are supporting such ARM based processors.
14 *
15 * @par
16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
21 *
22 ******************************************************************************/
23 #if defined ( __ICCARM__ )
24 #pragma system_include /* treat file as system include file for MISRA check */
25 #endif
26
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30
31 #ifndef __CORE_SC300_H_GENERIC
32 #define __CORE_SC300_H_GENERIC
33
34 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
35 CMSIS violates the following MISRA-C:2004 rules:
36
37 \li Required Rule 8.5, object/function definition in header file.<br>
38 Function definitions in header files are used to allow 'inlining'.
39
40 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
41 Unions are used for effective representation of core registers.
42
43 \li Advisory Rule 19.7, Function-like macro defined.<br>
44 Function-like macros are used to allow more efficient code.
45 */
46
47
48 /*******************************************************************************
49 * CMSIS definitions
50 ******************************************************************************/
51 /** \ingroup SC3000
52 @{
53 */
54
55 /* CMSIS SC300 definitions */
56 #define __SC300_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
57 #define __SC300_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
58 #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \
59 __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
60
61 #define __CORTEX_SC (300) /*!< Cortex secure core */
62
63
64 #if defined ( __CC_ARM )
65 #define __ASM __asm /*!< asm keyword for ARM Compiler */
66 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
67 #define __STATIC_INLINE static __inline
68
69 #elif defined ( __ICCARM__ )
70 #define __ASM __asm /*!< asm keyword for IAR Compiler */
71 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
72 #define __STATIC_INLINE static inline
73
74 #elif defined ( __GNUC__ )
75 #define __ASM __asm /*!< asm keyword for GNU Compiler */
76 #define __INLINE inline /*!< inline keyword for GNU Compiler */
77 #define __STATIC_INLINE static inline
78
79 #elif defined ( __TASKING__ )
80 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
81 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
82 #define __STATIC_INLINE static inline
83
84 #endif
85
86 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
87 */
88 #define __FPU_USED 0
89
90 #if defined ( __CC_ARM )
91 #if defined __TARGET_FPU_VFP
92 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
93 #endif
94
95 #elif defined ( __ICCARM__ )
96 #if defined __ARMVFP__
97 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
98 #endif
99
100 #elif defined ( __GNUC__ )
101 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
102 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
103 #endif
104
105 #elif defined ( __TASKING__ )
106 /* add preprocessor checks */
107 #endif
108
109 #include <stdint.h> /* standard types definitions */
110 #include <core_cmInstr.h> /* Core Instruction Access */
111 #include <core_cmFunc.h> /* Core Function Access */
112
113 #endif /* __CORE_SC300_H_GENERIC */
114
115 #ifndef __CMSIS_GENERIC
116
117 #ifndef __CORE_SC300_H_DEPENDANT
118 #define __CORE_SC300_H_DEPENDANT
119
120 /* check device defines and use defaults */
121 #if defined __CHECK_DEVICE_DEFINES
122 #ifndef __SC300_REV
123 #define __SC300_REV 0x0000
124 #warning "__SC300_REV not defined in device header file; using default!"
125 #endif
126
127 #ifndef __MPU_PRESENT
128 #define __MPU_PRESENT 0
129 #warning "__MPU_PRESENT not defined in device header file; using default!"
130 #endif
131
132 #ifndef __NVIC_PRIO_BITS
133 #define __NVIC_PRIO_BITS 4
134 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
135 #endif
136
137 #ifndef __Vendor_SysTickConfig
138 #define __Vendor_SysTickConfig 0
139 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
140 #endif
141 #endif
142
143 /* IO definitions (access restrictions to peripheral registers) */
144 /**
145 \defgroup CMSIS_glob_defs CMSIS Global Defines
146
147 <strong>IO Type Qualifiers</strong> are used
148 \li to specify the access to peripheral variables.
149 \li for automatic generation of peripheral register debug information.
150 */
151 #ifdef __cplusplus
152 #define __I volatile /*!< Defines 'read only' permissions */
153 #else
154 #define __I volatile const /*!< Defines 'read only' permissions */
155 #endif
156 #define __O volatile /*!< Defines 'write only' permissions */
157 #define __IO volatile /*!< Defines 'read / write' permissions */
158
159 /*@} end of group SC300 */
160
161
162
163 /*******************************************************************************
164 * Register Abstraction
165 Core Register contain:
166 - Core Register
167 - Core NVIC Register
168 - Core SCB Register
169 - Core SysTick Register
170 - Core Debug Register
171 - Core MPU Register
172 ******************************************************************************/
173 /** \defgroup CMSIS_core_register Defines and Type Definitions
174 \brief Type definitions and defines for Cortex-M processor based devices.
175 */
176
177 /** \ingroup CMSIS_core_register
178 \defgroup CMSIS_CORE Status and Control Registers
179 \brief Core Register type definitions.
180 @{
181 */
182
183 /** \brief Union type to access the Application Program Status Register (APSR).
184 */
185 typedef union
186 {
187 struct
188 {
189 #if (__CORTEX_M != 0x04)
190 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
191 #else
192 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
193 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
194 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
195 #endif
196 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
197 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
198 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
199 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
200 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
201 } b; /*!< Structure used for bit access */
202 uint32_t w; /*!< Type used for word access */
203 } APSR_Type;
204
205
206 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
207 */
208 typedef union
209 {
210 struct
211 {
212 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
213 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
214 } b; /*!< Structure used for bit access */
215 uint32_t w; /*!< Type used for word access */
216 } IPSR_Type;
217
218
219 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
220 */
221 typedef union
222 {
223 struct
224 {
225 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
226 #if (__CORTEX_M != 0x04)
227 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
228 #else
229 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
230 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
231 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
232 #endif
233 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
234 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
235 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
236 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
237 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
238 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
239 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
240 } b; /*!< Structure used for bit access */
241 uint32_t w; /*!< Type used for word access */
242 } xPSR_Type;
243
244
245 /** \brief Union type to access the Control Registers (CONTROL).
246 */
247 typedef union
248 {
249 struct
250 {
251 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
252 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
253 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
254 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
255 } b; /*!< Structure used for bit access */
256 uint32_t w; /*!< Type used for word access */
257 } CONTROL_Type;
258
259 /*@} end of group CMSIS_CORE */
260
261
262 /** \ingroup CMSIS_core_register
263 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
264 \brief Type definitions for the NVIC Registers
265 @{
266 */
267
268 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
269 */
270 typedef struct
271 {
272 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
273 uint32_t RESERVED0[24];
274 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
275 uint32_t RSERVED1[24];
276 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
277 uint32_t RESERVED2[24];
278 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
279 uint32_t RESERVED3[24];
280 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
281 uint32_t RESERVED4[56];
282 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
283 uint32_t RESERVED5[644];
284 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
285 } NVIC_Type;
286
287 /* Software Triggered Interrupt Register Definitions */
288 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
289 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
290
291 /*@} end of group CMSIS_NVIC */
292
293
294 /** \ingroup CMSIS_core_register
295 \defgroup CMSIS_SCB System Control Block (SCB)
296 \brief Type definitions for the System Control Block Registers
297 @{
298 */
299
300 /** \brief Structure type to access the System Control Block (SCB).
301 */
302 typedef struct
303 {
304 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
305 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
306 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
307 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
308 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
309 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
310 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
311 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
312 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
313 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
314 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
315 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
316 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
317 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
318 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
319 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
320 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
321 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
322 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
323 uint32_t RESERVED0[5];
324 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
325 } SCB_Type;
326
327 /* SCB CPUID Register Definitions */
328 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
329 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
330
331 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
332 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
333
334 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
335 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
336
337 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
338 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
339
340 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
341 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
342
343 /* SCB Interrupt Control State Register Definitions */
344 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
345 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
346
347 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
348 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
349
350 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
351 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
352
353 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
354 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
355
356 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
357 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
358
359 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
360 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
361
362 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
363 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
364
365 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
366 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
367
368 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
369 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
370
371 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
372 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
373
374 /* SCB Vector Table Offset Register Definitions */
375 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
376 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
377
378 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
379 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
380
381 /* SCB Application Interrupt and Reset Control Register Definitions */
382 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
383 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
384
385 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
386 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
387
388 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
389 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
390
391 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
392 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
393
394 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
395 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
396
397 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
398 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
399
400 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
401 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
402
403 /* SCB System Control Register Definitions */
404 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
405 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
406
407 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
408 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
409
410 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
411 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
412
413 /* SCB Configuration Control Register Definitions */
414 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
415 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
416
417 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
418 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
419
420 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
421 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
422
423 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
424 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
425
426 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
427 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
428
429 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
430 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
431
432 /* SCB System Handler Control and State Register Definitions */
433 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
434 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
435
436 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
437 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
438
439 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
440 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
441
442 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
443 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
444
445 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
446 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
447
448 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
449 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
450
451 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
452 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
453
454 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
455 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
456
457 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
458 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
459
460 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
461 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
462
463 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
464 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
465
466 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
467 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
468
469 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
470 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
471
472 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
473 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
474
475 /* SCB Configurable Fault Status Registers Definitions */
476 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
477 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
478
479 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
480 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
481
482 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
483 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
484
485 /* SCB Hard Fault Status Registers Definitions */
486 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
487 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
488
489 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
490 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
491
492 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
493 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
494
495 /* SCB Debug Fault Status Register Definitions */
496 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
497 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
498
499 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
500 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
501
502 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
503 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
504
505 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
506 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
507
508 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
509 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
510
511 /*@} end of group CMSIS_SCB */
512
513
514 /** \ingroup CMSIS_core_register
515 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
516 \brief Type definitions for the System Control and ID Register not in the SCB
517 @{
518 */
519
520 /** \brief Structure type to access the System Control and ID Register not in the SCB.
521 */
522 typedef struct
523 {
524 uint32_t RESERVED0[1];
525 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
526 uint32_t RESERVED1[1];
527 } SCnSCB_Type;
528
529 /* Interrupt Controller Type Register Definitions */
530 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
531 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
532
533 /*@} end of group CMSIS_SCnotSCB */
534
535
536 /** \ingroup CMSIS_core_register
537 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
538 \brief Type definitions for the System Timer Registers.
539 @{
540 */
541
542 /** \brief Structure type to access the System Timer (SysTick).
543 */
544 typedef struct
545 {
546 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
547 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
548 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
549 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
550 } SysTick_Type;
551
552 /* SysTick Control / Status Register Definitions */
553 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
554 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
555
556 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
557 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
558
559 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
560 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
561
562 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
563 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
564
565 /* SysTick Reload Register Definitions */
566 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
567 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
568
569 /* SysTick Current Register Definitions */
570 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
571 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
572
573 /* SysTick Calibration Register Definitions */
574 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
575 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
576
577 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
578 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
579
580 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
581 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
582
583 /*@} end of group CMSIS_SysTick */
584
585
586 /** \ingroup CMSIS_core_register
587 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
588 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
589 @{
590 */
591
592 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
593 */
594 typedef struct
595 {
596 __O union
597 {
598 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
599 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
600 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
601 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
602 uint32_t RESERVED0[864];
603 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
604 uint32_t RESERVED1[15];
605 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
606 uint32_t RESERVED2[15];
607 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
608 } ITM_Type;
609
610 /* ITM Trace Privilege Register Definitions */
611 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
612 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
613
614 /* ITM Trace Control Register Definitions */
615 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
616 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
617
618 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
619 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
620
621 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
622 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
623
624 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
625 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
626
627 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
628 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
629
630 #define ITM_TCR_TXENA_Pos 3 /*!< ITM TCR: TXENA Position */
631 #define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) /*!< ITM TCR: TXENA Mask */
632
633 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
634 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
635
636 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
637 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
638
639 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
640 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
641
642 /*@}*/ /* end of group CMSIS_ITM */
643
644
645 /** \ingroup CMSIS_core_register
646 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
647 \brief Type definitions for the Data Watchpoint and Trace (DWT)
648 @{
649 */
650
651 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
652 */
653 typedef struct
654 {
655 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
656 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
657 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
658 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
659 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
660 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
661 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
662 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
663 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
664 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
665 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
666 uint32_t RESERVED0[1];
667 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
668 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
669 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
670 uint32_t RESERVED1[1];
671 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
672 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
673 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
674 uint32_t RESERVED2[1];
675 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
676 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
677 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
678 } DWT_Type;
679
680 /* DWT Control Register Definitions */
681 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
682 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
683
684 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
685 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
686
687 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
688 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
689
690 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
691 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
692
693 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
694 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
695
696 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
697 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
698
699 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
700 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
701
702 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
703 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
704
705 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
706 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
707
708 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
709 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
710
711 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
712 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
713
714 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
715 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
716
717 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
718 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
719
720 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
721 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
722
723 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
724 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
725
726 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
727 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
728
729 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
730 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
731
732 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
733 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
734
735 /* DWT CPI Count Register Definitions */
736 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
737 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
738
739 /* DWT Exception Overhead Count Register Definitions */
740 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
741 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
742
743 /* DWT Sleep Count Register Definitions */
744 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
745 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
746
747 /* DWT LSU Count Register Definitions */
748 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
749 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
750
751 /* DWT Folded-instruction Count Register Definitions */
752 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
753 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
754
755 /* DWT Comparator Mask Register Definitions */
756 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
757 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
758
759 /* DWT Comparator Function Register Definitions */
760 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
761 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
762
763 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
764 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
765
766 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
767 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
768
769 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
770 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
771
772 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
773 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
774
775 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
776 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
777
778 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
779 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
780
781 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
782 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
783
784 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
785 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
786
787 /*@}*/ /* end of group CMSIS_DWT */
788
789
790 /** \ingroup CMSIS_core_register
791 \defgroup CMSIS_TPI Trace Port Interface (TPI)
792 \brief Type definitions for the Trace Port Interface (TPI)
793 @{
794 */
795
796 /** \brief Structure type to access the Trace Port Interface Register (TPI).
797 */
798 typedef struct
799 {
800 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
801 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
802 uint32_t RESERVED0[2];
803 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
804 uint32_t RESERVED1[55];
805 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
806 uint32_t RESERVED2[131];
807 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
808 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
809 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
810 uint32_t RESERVED3[759];
811 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
812 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
813 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
814 uint32_t RESERVED4[1];
815 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
816 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
817 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
818 uint32_t RESERVED5[39];
819 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
820 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
821 uint32_t RESERVED7[8];
822 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
823 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
824 } TPI_Type;
825
826 /* TPI Asynchronous Clock Prescaler Register Definitions */
827 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
828 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
829
830 /* TPI Selected Pin Protocol Register Definitions */
831 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
832 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
833
834 /* TPI Formatter and Flush Status Register Definitions */
835 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
836 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
837
838 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
839 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
840
841 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
842 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
843
844 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
845 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
846
847 /* TPI Formatter and Flush Control Register Definitions */
848 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
849 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
850
851 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
852 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
853
854 /* TPI TRIGGER Register Definitions */
855 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
856 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
857
858 /* TPI Integration ETM Data Register Definitions (FIFO0) */
859 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
860 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
861
862 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
863 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
864
865 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
866 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
867
868 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
869 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
870
871 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
872 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
873
874 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
875 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
876
877 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
878 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
879
880 /* TPI ITATBCTR2 Register Definitions */
881 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
882 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
883
884 /* TPI Integration ITM Data Register Definitions (FIFO1) */
885 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
886 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
887
888 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
889 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
890
891 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
892 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
893
894 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
895 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
896
897 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
898 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
899
900 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
901 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
902
903 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
904 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
905
906 /* TPI ITATBCTR0 Register Definitions */
907 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
908 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
909
910 /* TPI Integration Mode Control Register Definitions */
911 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
912 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
913
914 /* TPI DEVID Register Definitions */
915 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
916 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
917
918 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
919 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
920
921 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
922 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
923
924 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
925 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
926
927 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
928 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
929
930 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
931 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
932
933 /* TPI DEVTYPE Register Definitions */
934 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
935 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
936
937 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
938 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
939
940 /*@}*/ /* end of group CMSIS_TPI */
941
942
943 #if (__MPU_PRESENT == 1)
944 /** \ingroup CMSIS_core_register
945 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
946 \brief Type definitions for the Memory Protection Unit (MPU)
947 @{
948 */
949
950 /** \brief Structure type to access the Memory Protection Unit (MPU).
951 */
952 typedef struct
953 {
954 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
955 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
956 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
957 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
958 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
959 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
960 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
961 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
962 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
963 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
964 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
965 } MPU_Type;
966
967 /* MPU Type Register */
968 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
969 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
970
971 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
972 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
973
974 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
975 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
976
977 /* MPU Control Register */
978 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
979 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
980
981 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
982 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
983
984 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
985 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
986
987 /* MPU Region Number Register */
988 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
989 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
990
991 /* MPU Region Base Address Register */
992 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
993 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
994
995 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
996 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
997
998 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
999 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
1000
1001 /* MPU Region Attribute and Size Register */
1002 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
1003 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1004
1005 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
1006 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1007
1008 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
1009 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1010
1011 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
1012 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
1013
1014 /*@} end of group CMSIS_MPU */
1015 #endif
1016
1017
1018 /** \ingroup CMSIS_core_register
1019 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1020 \brief Type definitions for the Core Debug Registers
1021 @{
1022 */
1023
1024 /** \brief Structure type to access the Core Debug Register (CoreDebug).
1025 */
1026 typedef struct
1027 {
1028 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1029 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1030 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1031 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1032 } CoreDebug_Type;
1033
1034 /* Debug Halting Control and Status Register */
1035 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
1036 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1037
1038 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
1039 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1040
1041 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1042 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1043
1044 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
1045 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1046
1047 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
1048 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1049
1050 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
1051 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1052
1053 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
1054 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1055
1056 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1057 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1058
1059 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
1060 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1061
1062 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
1063 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1064
1065 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
1066 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1067
1068 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1069 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1070
1071 /* Debug Core Register Selector Register */
1072 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
1073 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1074
1075 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
1076 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
1077
1078 /* Debug Exception and Monitor Control Register */
1079 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
1080 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1081
1082 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
1083 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1084
1085 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
1086 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1087
1088 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
1089 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1090
1091 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
1092 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1093
1094 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
1095 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1096
1097 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
1098 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1099
1100 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
1101 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1102
1103 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
1104 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1105
1106 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
1107 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1108
1109 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1110 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1111
1112 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
1113 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1114
1115 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
1116 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1117
1118 /*@} end of group CMSIS_CoreDebug */
1119
1120
1121 /** \ingroup CMSIS_core_register
1122 \defgroup CMSIS_core_base Core Definitions
1123 \brief Definitions for base addresses, unions, and structures.
1124 @{
1125 */
1126
1127 /* Memory mapping of Cortex-M3 Hardware */
1128 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1129 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1130 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1131 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1132 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1133 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1134 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1135 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1136
1137 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1138 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1139 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1140 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1141 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1142 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1143 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1144 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
1145
1146 #if (__MPU_PRESENT == 1)
1147 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1148 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1149 #endif
1150
1151 /*@} */
1152
1153
1154
1155 /*******************************************************************************
1156 * Hardware Abstraction Layer
1157 Core Function Interface contains:
1158 - Core NVIC Functions
1159 - Core SysTick Functions
1160 - Core Debug Functions
1161 - Core Register Access Functions
1162 ******************************************************************************/
1163 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1164 */
1165
1166
1167
1168 /* ########################## NVIC functions #################################### */
1169 /** \ingroup CMSIS_Core_FunctionInterface
1170 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1171 \brief Functions that manage interrupts and exceptions via the NVIC.
1172 @{
1173 */
1174
1175 /** \brief Set Priority Grouping
1176
1177 The function sets the priority grouping field using the required unlock sequence.
1178 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1179 Only values from 0..7 are used.
1180 In case of a conflict between priority grouping and available
1181 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1182
1183 \param [in] PriorityGroup Priority grouping field.
1184 */
NVIC_SetPriorityGrouping(uint32_t PriorityGroup)1185 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1186 {
1187 uint32_t reg_value;
1188 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
1189
1190 reg_value = SCB->AIRCR; /* read old register configuration */
1191 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
1192 reg_value = (reg_value |
1193 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1194 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
1195 SCB->AIRCR = reg_value;
1196 }
1197
1198
1199 /** \brief Get Priority Grouping
1200
1201 The function reads the priority grouping field from the NVIC Interrupt Controller.
1202
1203 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1204 */
NVIC_GetPriorityGrouping(void)1205 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1206 {
1207 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
1208 }
1209
1210
1211 /** \brief Enable External Interrupt
1212
1213 The function enables a device-specific interrupt in the NVIC interrupt controller.
1214
1215 \param [in] IRQn External interrupt number. Value cannot be negative.
1216 */
NVIC_EnableIRQ(IRQn_Type IRQn)1217 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1218 {
1219 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
1220 }
1221
1222
1223 /** \brief Disable External Interrupt
1224
1225 The function disables a device-specific interrupt in the NVIC interrupt controller.
1226
1227 \param [in] IRQn External interrupt number. Value cannot be negative.
1228 */
NVIC_DisableIRQ(IRQn_Type IRQn)1229 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1230 {
1231 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
1232 }
1233
1234
1235 /** \brief Get Pending Interrupt
1236
1237 The function reads the pending register in the NVIC and returns the pending bit
1238 for the specified interrupt.
1239
1240 \param [in] IRQn Interrupt number.
1241
1242 \return 0 Interrupt status is not pending.
1243 \return 1 Interrupt status is pending.
1244 */
NVIC_GetPendingIRQ(IRQn_Type IRQn)1245 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1246 {
1247 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
1248 }
1249
1250
1251 /** \brief Set Pending Interrupt
1252
1253 The function sets the pending bit of an external interrupt.
1254
1255 \param [in] IRQn Interrupt number. Value cannot be negative.
1256 */
NVIC_SetPendingIRQ(IRQn_Type IRQn)1257 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1258 {
1259 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
1260 }
1261
1262
1263 /** \brief Clear Pending Interrupt
1264
1265 The function clears the pending bit of an external interrupt.
1266
1267 \param [in] IRQn External interrupt number. Value cannot be negative.
1268 */
NVIC_ClearPendingIRQ(IRQn_Type IRQn)1269 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1270 {
1271 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
1272 }
1273
1274
1275 /** \brief Get Active Interrupt
1276
1277 The function reads the active register in NVIC and returns the active bit.
1278
1279 \param [in] IRQn Interrupt number.
1280
1281 \return 0 Interrupt status is not active.
1282 \return 1 Interrupt status is active.
1283 */
NVIC_GetActive(IRQn_Type IRQn)1284 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1285 {
1286 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
1287 }
1288
1289
1290 /** \brief Set Interrupt Priority
1291
1292 The function sets the priority of an interrupt.
1293
1294 \note The priority cannot be set for every core interrupt.
1295
1296 \param [in] IRQn Interrupt number.
1297 \param [in] priority Priority to set.
1298 */
NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)1299 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1300 {
1301 if(IRQn < 0) {
1302 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
1303 else {
1304 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
1305 }
1306
1307
1308 /** \brief Get Interrupt Priority
1309
1310 The function reads the priority of an interrupt. The interrupt
1311 number can be positive to specify an external (device specific)
1312 interrupt, or negative to specify an internal (core) interrupt.
1313
1314
1315 \param [in] IRQn Interrupt number.
1316 \return Interrupt Priority. Value is aligned automatically to the implemented
1317 priority bits of the microcontroller.
1318 */
NVIC_GetPriority(IRQn_Type IRQn)1319 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1320 {
1321
1322 if(IRQn < 0) {
1323 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
1324 else {
1325 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
1326 }
1327
1328
1329 /** \brief Encode Priority
1330
1331 The function encodes the priority for an interrupt with the given priority group,
1332 preemptive priority value, and subpriority value.
1333 In case of a conflict between priority grouping and available
1334 priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
1335
1336 \param [in] PriorityGroup Used priority group.
1337 \param [in] PreemptPriority Preemptive priority value (starting from 0).
1338 \param [in] SubPriority Subpriority value (starting from 0).
1339 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1340 */
NVIC_EncodePriority(uint32_t PriorityGroup,uint32_t PreemptPriority,uint32_t SubPriority)1341 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1342 {
1343 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1344 uint32_t PreemptPriorityBits;
1345 uint32_t SubPriorityBits;
1346
1347 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1348 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1349
1350 return (
1351 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
1352 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
1353 );
1354 }
1355
1356
1357 /** \brief Decode Priority
1358
1359 The function decodes an interrupt priority value with a given priority group to
1360 preemptive priority value and subpriority value.
1361 In case of a conflict between priority grouping and available
1362 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
1363
1364 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1365 \param [in] PriorityGroup Used priority group.
1366 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1367 \param [out] pSubPriority Subpriority value (starting from 0).
1368 */
NVIC_DecodePriority(uint32_t Priority,uint32_t PriorityGroup,uint32_t * pPreemptPriority,uint32_t * pSubPriority)1369 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
1370 {
1371 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1372 uint32_t PreemptPriorityBits;
1373 uint32_t SubPriorityBits;
1374
1375 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1376 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1377
1378 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
1379 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
1380 }
1381
1382
1383 /** \brief System Reset
1384
1385 The function initiates a system reset request to reset the MCU.
1386 */
NVIC_SystemReset(void)1387 __STATIC_INLINE void NVIC_SystemReset(void)
1388 {
1389 __DSB(); /* Ensure all outstanding memory accesses included
1390 buffered write are completed before reset */
1391 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1392 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1393 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
1394 __DSB(); /* Ensure completion of memory access */
1395 while(1); /* wait until reset */
1396 }
1397
1398 /*@} end of CMSIS_Core_NVICFunctions */
1399
1400
1401
1402 /* ################################## SysTick function ############################################ */
1403 /** \ingroup CMSIS_Core_FunctionInterface
1404 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1405 \brief Functions that configure the System.
1406 @{
1407 */
1408
1409 #if (__Vendor_SysTickConfig == 0)
1410
1411 /** \brief System Tick Configuration
1412
1413 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
1414 Counter is in free running mode to generate periodic interrupts.
1415
1416 \param [in] ticks Number of ticks between two interrupts.
1417
1418 \return 0 Function succeeded.
1419 \return 1 Function failed.
1420
1421 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1422 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
1423 must contain a vendor-specific implementation of this function.
1424
1425 */
SysTick_Config(uint32_t ticks)1426 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1427 {
1428 if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
1429
1430 SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
1431 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
1432 SysTick->VAL = 0; /* Load the SysTick Counter Value */
1433 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1434 SysTick_CTRL_TICKINT_Msk |
1435 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1436 return (0); /* Function successful */
1437 }
1438
1439 #endif
1440
1441 /*@} end of CMSIS_Core_SysTickFunctions */
1442
1443
1444
1445 /* ##################################### Debug In/Output function ########################################### */
1446 /** \ingroup CMSIS_Core_FunctionInterface
1447 \defgroup CMSIS_core_DebugFunctions ITM Functions
1448 \brief Functions that access the ITM debug interface.
1449 @{
1450 */
1451
1452 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
1453 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
1454
1455
1456 /** \brief ITM Send Character
1457
1458 The function transmits a character via the ITM channel 0, and
1459 \li Just returns when no debugger is connected that has booked the output.
1460 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
1461
1462 \param [in] ch Character to transmit.
1463
1464 \returns Character to transmit.
1465 */
ITM_SendChar(uint32_t ch)1466 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
1467 {
1468 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
1469 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
1470 {
1471 while (ITM->PORT[0].u32 == 0);
1472 ITM->PORT[0].u8 = (uint8_t) ch;
1473 }
1474 return (ch);
1475 }
1476
1477
1478 /** \brief ITM Receive Character
1479
1480 The function inputs a character via the external variable \ref ITM_RxBuffer.
1481
1482 \return Received character.
1483 \return -1 No character pending.
1484 */
ITM_ReceiveChar(void)1485 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
1486 int32_t ch = -1; /* no character available */
1487
1488 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
1489 ch = ITM_RxBuffer;
1490 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1491 }
1492
1493 return (ch);
1494 }
1495
1496
1497 /** \brief ITM Check Character
1498
1499 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
1500
1501 \return 0 No character available.
1502 \return 1 Character available.
1503 */
ITM_CheckChar(void)1504 __STATIC_INLINE int32_t ITM_CheckChar (void) {
1505
1506 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
1507 return (0); /* no character available */
1508 } else {
1509 return (1); /* character available */
1510 }
1511 }
1512
1513 /*@} end of CMSIS_core_DebugFunctions */
1514
1515 #endif /* __CORE_SC300_H_DEPENDANT */
1516
1517 #endif /* __CMSIS_GENERIC */
1518
1519 #ifdef __cplusplus
1520 }
1521 #endif
1522