1 /*
2 * This file is part of libsidplayfp, a SID player engine.
3 *
4 * Copyright 2011-2016 Leandro Nini <drfiemost@users.sourceforge.net>
5 * Copyright 2007-2010 Antti Lankila
6 * Copyright 2004,2010 Dag Lem <resid@nimrod.no>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
21 */
22
23 #ifndef WAVEFORMGENERATOR_H
24 #define WAVEFORMGENERATOR_H
25
26 #include "siddefs-fp.h"
27 #include "array.h"
28
29 #include "sidcxx11.h"
30
31 namespace reSIDfp
32 {
33
34 /**
35 * A 24 bit accumulator is the basis for waveform generation.
36 * FREQ is added to the lower 16 bits of the accumulator each cycle.
37 * The accumulator is set to zero when TEST is set, and starts counting
38 * when TEST is cleared.
39 *
40 * Waveforms are generated as follows:
41 *
42 * - No waveform:
43 * When no waveform is selected, the DAC input is floating.
44 *
45 *
46 * - Triangle:
47 * The upper 12 bits of the accumulator are used.
48 * The MSB is used to create the falling edge of the triangle by inverting
49 * the lower 11 bits. The MSB is thrown away and the lower 11 bits are
50 * left-shifted (half the resolution, full amplitude).
51 * Ring modulation substitutes the MSB with MSB EOR NOT sync_source MSB.
52 *
53 *
54 * - Sawtooth:
55 * The output is identical to the upper 12 bits of the accumulator.
56 *
57 *
58 * - Pulse:
59 * The upper 12 bits of the accumulator are used.
60 * These bits are compared to the pulse width register by a 12 bit digital
61 * comparator; output is either all one or all zero bits.
62 * The pulse setting is delayed one cycle after the compare.
63 * The test bit, when set to one, holds the pulse waveform output at 0xfff
64 * regardless of the pulse width setting.
65 *
66 *
67 * - Noise:
68 * The noise output is taken from intermediate bits of a 23-bit shift register
69 * which is clocked by bit 19 of the accumulator.
70 * The shift is delayed 2 cycles after bit 19 is set high.
71 *
72 * Operation: Calculate EOR result, shift register, set bit 0 = result.
73 *
74 * reset +--------------------------------------------+
75 * | | |
76 * test--OR-->EOR<--+ |
77 * | | |
78 * 2 2 2 1 1 1 1 1 1 1 1 1 1 |
79 * Register bits: 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 <---+
80 * | | | | | | | |
81 * Waveform bits: 1 1 9 8 7 6 5 4
82 * 1 0
83 *
84 * The low 4 waveform bits are zero (grounded).
85 */
86 class WaveformGenerator
87 {
88 private:
89 matrix_t* model_wave;
90
91 short* wave;
92
93 // PWout = (PWn/40.95)%
94 unsigned int pw;
95
96 unsigned int shift_register;
97
98 /// Emulation of pipeline causing bit 19 to clock the shift register.
99 int shift_pipeline;
100
101 unsigned int ring_msb_mask;
102 unsigned int no_noise;
103 unsigned int noise_output;
104 unsigned int no_noise_or_noise_output;
105 unsigned int no_pulse;
106 unsigned int pulse_output;
107
108 /// The control register right-shifted 4 bits; used for output function table lookup.
109 unsigned int waveform;
110
111 unsigned int waveform_output;
112
113 /// Current accumulator value.
114 unsigned int accumulator;
115
116 // Fout = (Fn*Fclk/16777216)Hz
117 unsigned int freq;
118
119 /// 8580 tri/saw pipeline
120 unsigned int tri_saw_pipeline;
121
122 /// The OSC3 value
123 unsigned int osc3;
124
125 /// Remaining time to fully reset shift register.
126 unsigned int shift_register_reset;
127
128 // The wave signal TTL when no waveform is selected
129 unsigned int floating_output_ttl;
130
131 /// The control register bits. Gate is handled by EnvelopeGenerator.
132 //@{
133 bool test;
134 bool sync;
135 //@}
136
137 /// Tell whether the accumulator MSB was set high on this cycle.
138 bool msb_rising;
139
140 bool is6581; //-V730_NOINIT this is initialized in the SID constructor
141
142 /// The DAC LUT for analog output
143 float* dac; //-V730_NOINIT this is initialized in the SID constructor
144
145 private:
146 void clock_shift_register(unsigned int bit0);
147
148 unsigned int get_noise_writeback();
149
150 void write_shift_register();
151
152 void set_noise_output();
153
154 void set_no_noise_or_noise_output();
155
156 void waveBitfade();
157
158 void shiftregBitfade();
159
160 public:
161 void setWaveformModels(matrix_t* models);
162
163 /**
164 * Set the analog DAC emulation:
165 * 8580 is perfectly linear while 6581 is nonlinear.
166 * Must be called before any operation.
167 *
168 * @param dac
169 */
setDAC(float * dac)170 void setDAC(float* dac) { this->dac = dac; }
171
172 /**
173 * Set the chip model.
174 * Must be called before any operation.
175 *
176 * @param is6581 true if MOS6581, false if CSG8580
177 */
setModel(bool is6581)178 void setModel(bool is6581) { this->is6581 = is6581; }
179
180 /**
181 * SID clocking.
182 */
183 void clock();
184
185 /**
186 * Synchronize oscillators.
187 * This must be done after all the oscillators have been clock()'ed,
188 * so that they are in the same state.
189 *
190 * @param syncDest The oscillator that will be synced
191 * @param syncSource The sync source oscillator
192 */
193 void synchronize(WaveformGenerator* syncDest, const WaveformGenerator* syncSource) const;
194
195 /**
196 * Constructor.
197 */
WaveformGenerator()198 WaveformGenerator() :
199 model_wave(nullptr),
200 wave(nullptr),
201 pw(0),
202 shift_register(0),
203 shift_pipeline(0),
204 ring_msb_mask(0),
205 no_noise(0),
206 noise_output(0),
207 no_noise_or_noise_output(0),
208 no_pulse(0),
209 pulse_output(0),
210 waveform(0),
211 waveform_output(0),
212 accumulator(0x555555), // Accumulator's even bits are high on powerup
213 freq(0),
214 tri_saw_pipeline(0x555),
215 osc3(0),
216 shift_register_reset(0),
217 floating_output_ttl(0),
218 test(false),
219 sync(false),
220 msb_rising(false) {}
221
222 /**
223 * Write FREQ LO register.
224 *
225 * @param freq_lo low 8 bits of frequency
226 */
writeFREQ_LO(unsigned char freq_lo)227 void writeFREQ_LO(unsigned char freq_lo) { freq = (freq & 0xff00) | (freq_lo & 0xff); }
228
229 /**
230 * Write FREQ HI register.
231 *
232 * @param freq_hi high 8 bits of frequency
233 */
writeFREQ_HI(unsigned char freq_hi)234 void writeFREQ_HI(unsigned char freq_hi) { freq = (freq_hi << 8 & 0xff00) | (freq & 0xff); }
235
236 /**
237 * Write PW LO register.
238 *
239 * @param pw_lo low 8 bits of pulse width
240 */
writePW_LO(unsigned char pw_lo)241 void writePW_LO(unsigned char pw_lo) { pw = (pw & 0xf00) | (pw_lo & 0x0ff); }
242
243 /**
244 * Write PW HI register.
245 *
246 * @param pw_hi high 8 bits of pulse width
247 */
writePW_HI(unsigned char pw_hi)248 void writePW_HI(unsigned char pw_hi) { pw = (pw_hi << 8 & 0xf00) | (pw & 0x0ff); }
249
250 /**
251 * Write CONTROL REGISTER register.
252 *
253 * @param control control register value
254 */
255 void writeCONTROL_REG(unsigned char control);
256
257 /**
258 * SID reset.
259 */
260 void reset();
261
262 /**
263 * 12-bit waveform output as an analogue float value.
264 *
265 * @param ringModulator The oscillator ring-modulating current one.
266 * @return output the waveform generator output
267 */
268 float output(const WaveformGenerator* ringModulator);
269
270 /**
271 * Read OSC3 value.
272 */
readOSC()273 unsigned char readOSC() const { return static_cast<unsigned char>(osc3 >> 4); }
274
275 /**
276 * Read accumulator value.
277 */
readAccumulator()278 unsigned int readAccumulator() const { return accumulator; }
279
280 /**
281 * Read freq value.
282 */
readFreq()283 unsigned int readFreq() const { return freq; }
284
285 /**
286 * Read test value.
287 */
readTest()288 bool readTest() const { return test; }
289
290 /**
291 * Read sync value.
292 */
readSync()293 bool readSync() const { return sync; }
294 };
295
296 } // namespace reSIDfp
297
298 #if RESID_INLINING || defined(WAVEFORMGENERATOR_CPP)
299
300 namespace reSIDfp
301 {
302
303 RESID_INLINE
clock()304 void WaveformGenerator::clock()
305 {
306 if (unlikely(test))
307 {
308 if (unlikely(shift_register_reset != 0) && unlikely(--shift_register_reset == 0))
309 {
310 shiftregBitfade();
311
312 // New noise waveform output.
313 set_noise_output();
314 }
315
316 // The test bit sets pulse high.
317 pulse_output = 0xfff;
318 }
319 else
320 {
321 // Calculate new accumulator value;
322 const unsigned int accumulator_old = accumulator;
323 accumulator = (accumulator + freq) & 0xffffff;
324
325 // Check which bit have changed
326 const unsigned int accumulator_bits_set = ~accumulator_old & accumulator;
327
328 // Check whether the MSB is set high. This is used for synchronization.
329 msb_rising = (accumulator_bits_set & 0x800000) != 0;
330
331 // Shift noise register once for each time accumulator bit 19 is set high.
332 // The shift is delayed 2 cycles.
333 if (unlikely((accumulator_bits_set & 0x080000) != 0))
334 {
335 // Pipeline: Detect rising bit, shift phase 1, shift phase 2.
336 shift_pipeline = 2;
337 }
338 else if (unlikely(shift_pipeline != 0) && --shift_pipeline == 0)
339 {
340 // bit0 = (bit22 | test) ^ bit17
341 clock_shift_register(((shift_register << 22) ^ (shift_register << 17)) & (1 << 22));
342 }
343 }
344 }
345
346 RESID_INLINE
output(const WaveformGenerator * ringModulator)347 float WaveformGenerator::output(const WaveformGenerator* ringModulator)
348 {
349 // Set output value.
350 if (likely(waveform != 0))
351 {
352 const unsigned int ix = (accumulator ^ (~ringModulator->accumulator & ring_msb_mask)) >> 12;
353
354 // The bit masks no_pulse and no_noise are used to achieve branch-free
355 // calculation of the output value.
356 waveform_output = wave[ix] & (no_pulse | pulse_output) & no_noise_or_noise_output;
357
358 // Triangle/Sawtooth output is delayed half cycle on 8580.
359 // This will appear as a one cycle delay on OSC3 as it is latched first phase of the clock.
360 if ((waveform & 3) && !is6581)
361 {
362 osc3 = tri_saw_pipeline & (no_pulse | pulse_output) & no_noise_or_noise_output;
363 tri_saw_pipeline = wave[ix];
364 }
365 else
366 {
367 osc3 = waveform_output;
368 }
369
370 // In the 6581 the top bit of the accumulator may be driven low by combined waveforms
371 // when the sawtooth is selected
372 // FIXME doesn't seem to always happen
373 if ((waveform & 2) && unlikely(waveform & 0xd) && is6581)
374 accumulator &= (waveform_output << 12) | 0x7fffff;
375
376 write_shift_register();
377 }
378 else
379 {
380 // Age floating DAC input.
381 if (likely(floating_output_ttl != 0) && unlikely(--floating_output_ttl == 0))
382 {
383 waveBitfade();
384 }
385 }
386
387 // The pulse level is defined as (accumulator >> 12) >= pw ? 0xfff : 0x000.
388 // The expression -((accumulator >> 12) >= pw) & 0xfff yields the same
389 // results without any branching (and thus without any pipeline stalls).
390 // NB! This expression relies on that the result of a boolean expression
391 // is either 0 or 1, and furthermore requires two's complement integer.
392 // A few more cycles may be saved by storing the pulse width left shifted
393 // 12 bits, and dropping the and with 0xfff (this is valid since pulse is
394 // used as a bit mask on 12 bit values), yielding the expression
395 // -(accumulator >= pw24). However this only results in negligible savings.
396
397 // The result of the pulse width compare is delayed one cycle.
398 // Push next pulse level into pulse level pipeline.
399 pulse_output = ((accumulator >> 12) >= pw) ? 0xfff : 0x000;
400
401 // DAC imperfections are emulated by using waveform_output as an index
402 // into a DAC lookup table. readOSC() uses waveform_output directly.
403 return dac[waveform_output];
404 }
405
406 } // namespace reSIDfp
407
408 #endif
409
410 #endif
411