1 /*
2 **
3 ** File: fmopl.c - software implementation of FM sound generator
4 ** types OPL and OPL2
5 **
6 ** Copyright Jarek Burczynski (bujar at mame dot net)
7 ** Copyright Tatsuyuki Satoh , MultiArcadeMachineEmulator development
8 **
9 ** Version 0.72
10 **
11
12 Revision History:
13
14 04-08-2003 Jarek Burczynski:
15 - removed BFRDY hack. BFRDY is busy flag, and it should be 0 only when the chip
16 handles memory read/write or during the adpcm synthesis when the chip
17 requests another byte of ADPCM data.
18
19 24-07-2003 Jarek Burczynski:
20 - added a small hack for Y8950 status BFRDY flag (bit 3 should be set after
21 some (unknown) delay). Right now it's always set.
22
23 14-06-2003 Jarek Burczynski:
24 - implemented all of the status register flags in Y8950 emulation
25 - renamed y8950_set_delta_t_memory() parameters from _rom_ to _mem_ since
26 they can be either RAM or ROM
27
28 08-10-2002 Jarek Burczynski (thanks to Dox for the YM3526 chip)
29 - corrected ym3526_read() to always set bit 2 and bit 1
30 to HIGH state - identical to ym3812_read (verified on real YM3526)
31
32 04-28-2002 Jarek Burczynski:
33 - binary exact Envelope Generator (verified on real YM3812);
34 compared to YM2151: the EG clock is equal to internal_clock,
35 rates are 2 times slower and volume resolution is one bit less
36 - modified interface functions (they no longer return pointer -
37 that's internal to the emulator now):
38 - new wrapper functions for OPLCreate: ym3526_init(), ym3812_init() and y8950_init()
39 - corrected 'off by one' error in feedback calculations (when feedback is off)
40 - enabled waveform usage (credit goes to Vlad Romascanu and zazzal22)
41 - speeded up noise generator calculations (Nicola Salmoria)
42
43 03-24-2002 Jarek Burczynski (thanks to Dox for the YM3812 chip)
44 Complete rewrite (all verified on real YM3812):
45 - corrected sin_tab and tl_tab data
46 - corrected operator output calculations
47 - corrected waveform_select_enable register;
48 simply: ignore all writes to waveform_select register when
49 waveform_select_enable == 0 and do not change the waveform previously selected.
50 - corrected KSR handling
51 - corrected Envelope Generator: attack shape, Sustain mode and
52 Percussive/Non-percussive modes handling
53 - Envelope Generator rates are two times slower now
54 - LFO amplitude (tremolo) and phase modulation (vibrato)
55 - rhythm sounds phase generation
56 - white noise generator (big thanks to Olivier Galibert for mentioning Berlekamp-Massey algorithm)
57 - corrected key on/off handling (the 'key' signal is ORed from three sources: FM, rhythm and CSM)
58 - funky details (like ignoring output of operator 1 in BD rhythm sound when connect == 1)
59
60 12-28-2001 Acho A. Tang
61 - reflected Delta-T EOS status on Y8950 status port.
62 - fixed subscription range of attack/decay tables
63
64
65 To do:
66 add delay before key off in CSM mode (see CSMKeyControll)
67 verify volume of the FM part on the Y8950
68 */
69
70 #include <math.h>
71 #include "mamedef.h"
72 #ifdef _DEBUG
73 #include <stdio.h>
74 #endif
75 #include <stdlib.h>
76 #include <string.h> // for memset
77 #include <stddef.h> // for NULL
78 //#include "sndintrf.h"
79 #include "fmopl.h"
80 #if BUILD_Y8950
81 #include "ymdeltat.h"
82 #endif
83
84
85 /* output final shift */
86 #if (OPL_SAMPLE_BITS==16)
87 #define FINAL_SH (0)
88 #define MAXOUT (+32767)
89 #define MINOUT (-32768)
90 #else
91 #define FINAL_SH (8)
92 #define MAXOUT (+127)
93 #define MINOUT (-128)
94 #endif
95
96
97 #define FREQ_SH 16 /* 16.16 fixed point (frequency calculations) */
98 #define EG_SH 16 /* 16.16 fixed point (EG timing) */
99 #define LFO_SH 24 /* 8.24 fixed point (LFO calculations) */
100 #define TIMER_SH 16 /* 16.16 fixed point (timers calculations) */
101
102 #define FREQ_MASK ((1<<FREQ_SH)-1)
103
104 /* envelope output entries */
105 #define ENV_BITS 10
106 #define ENV_LEN (1<<ENV_BITS)
107 #define ENV_STEP (128.0/ENV_LEN)
108
109 #define MAX_ATT_INDEX ((1<<(ENV_BITS-1))-1) /*511*/
110 #define MIN_ATT_INDEX (0)
111
112 /* sinwave entries */
113 #define SIN_BITS 10
114 #define SIN_LEN (1<<SIN_BITS)
115 #define SIN_MASK (SIN_LEN-1)
116
117 #define TL_RES_LEN (256) /* 8 bits addressing (real chip) */
118
119
120
121 /* register number to channel number , slot offset */
122 #define SLOT1 0
123 #define SLOT2 1
124
125 /* Envelope Generator phases */
126
127 #define EG_ATT 4
128 #define EG_DEC 3
129 #define EG_SUS 2
130 #define EG_REL 1
131 #define EG_OFF 0
132
133
134 /* save output as raw 16-bit sample */
135
136 /*#define SAVE_SAMPLE*/
137
138 #ifdef SAVE_SAMPLE
acc_calc(signed int value)139 INLINE signed int acc_calc(signed int value)
140 {
141 if (value>=0)
142 {
143 if (value < 0x0200)
144 return (value & ~0);
145 if (value < 0x0400)
146 return (value & ~1);
147 if (value < 0x0800)
148 return (value & ~3);
149 if (value < 0x1000)
150 return (value & ~7);
151 if (value < 0x2000)
152 return (value & ~15);
153 if (value < 0x4000)
154 return (value & ~31);
155 return (value & ~63);
156 }
157 /*else value < 0*/
158 if (value > -0x0200)
159 return (~abs(value) & ~0);
160 if (value > -0x0400)
161 return (~abs(value) & ~1);
162 if (value > -0x0800)
163 return (~abs(value) & ~3);
164 if (value > -0x1000)
165 return (~abs(value) & ~7);
166 if (value > -0x2000)
167 return (~abs(value) & ~15);
168 if (value > -0x4000)
169 return (~abs(value) & ~31);
170 return (~abs(value) & ~63);
171 }
172
173
174 static FILE *sample[1];
175 #if 1 /*save to MONO file */
176 #define SAVE_ALL_CHANNELS \
177 { signed int pom = acc_calc(lt); \
178 fputc((unsigned short)pom&0xff,sample[0]); \
179 fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
180 }
181 #else /*save to STEREO file */
182 #define SAVE_ALL_CHANNELS \
183 { signed int pom = lt; \
184 fputc((unsigned short)pom&0xff,sample[0]); \
185 fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
186 pom = rt; \
187 fputc((unsigned short)pom&0xff,sample[0]); \
188 fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
189 }
190 #endif
191 #endif
192
193 //#define LOG_CYM_FILE 0
194 //static FILE * cymfile = NULL;
195
196
197
198 #define OPL_TYPE_WAVESEL 0x01 /* waveform select */
199 #define OPL_TYPE_ADPCM 0x02 /* DELTA-T ADPCM unit */
200 #define OPL_TYPE_KEYBOARD 0x04 /* keyboard interface */
201 #define OPL_TYPE_IO 0x08 /* I/O port */
202
203 /* ---------- Generic interface section ---------- */
204 #define OPL_TYPE_YM3526 (0)
205 #define OPL_TYPE_YM3812 (OPL_TYPE_WAVESEL)
206 #define OPL_TYPE_Y8950 (OPL_TYPE_ADPCM|OPL_TYPE_KEYBOARD|OPL_TYPE_IO)
207
208
209
210 typedef struct
211 {
212 UINT32 ar; /* attack rate: AR<<2 */
213 UINT32 dr; /* decay rate: DR<<2 */
214 UINT32 rr; /* release rate:RR<<2 */
215 UINT8 KSR; /* key scale rate */
216 UINT8 ksl; /* keyscale level */
217 UINT8 ksr; /* key scale rate: kcode>>KSR */
218 UINT8 mul; /* multiple: mul_tab[ML] */
219
220 /* Phase Generator */
221 UINT32 Cnt; /* frequency counter */
222 UINT32 Incr; /* frequency counter step */
223 UINT8 FB; /* feedback shift value */
224 INT32 *connect1; /* slot1 output pointer */
225 INT32 op1_out[2]; /* slot1 output for feedback */
226 UINT8 CON; /* connection (algorithm) type */
227
228 /* Envelope Generator */
229 UINT8 eg_type; /* percussive/non-percussive mode */
230 UINT8 state; /* phase type */
231 UINT32 TL; /* total level: TL << 2 */
232 INT32 TLL; /* adjusted now TL */
233 INT32 volume; /* envelope counter */
234 UINT32 sl; /* sustain level: sl_tab[SL] */
235 UINT8 eg_sh_ar; /* (attack state) */
236 UINT8 eg_sel_ar; /* (attack state) */
237 UINT8 eg_sh_dr; /* (decay state) */
238 UINT8 eg_sel_dr; /* (decay state) */
239 UINT8 eg_sh_rr; /* (release state) */
240 UINT8 eg_sel_rr; /* (release state) */
241 UINT32 key; /* 0 = KEY OFF, >0 = KEY ON */
242
243 /* LFO */
244 UINT32 AMmask; /* LFO Amplitude Modulation enable mask */
245 UINT8 vib; /* LFO Phase Modulation enable flag (active high)*/
246
247 /* waveform select */
248 UINT16 wavetable;
249 } OPL_SLOT;
250
251 typedef struct
252 {
253 OPL_SLOT SLOT[2];
254 /* phase generator state */
255 UINT32 block_fnum; /* block+fnum */
256 UINT32 fc; /* Freq. Increment base */
257 UINT32 ksl_base; /* KeyScaleLevel Base step */
258 UINT8 kcode; /* key code (for key scaling) */
259 UINT8 Muted;
260 } OPL_CH;
261
262 /* OPL state */
263 typedef struct fm_opl_f
264 {
265 /* FM channel slots */
266 OPL_CH P_CH[9]; /* OPL/OPL2 chips have 9 channels*/
267 UINT8 MuteSpc[6]; /* Mute Special: 5 Rhythm + 1 DELTA-T Channel */
268
269 UINT32 eg_cnt; /* global envelope generator counter */
270 UINT32 eg_timer; /* global envelope generator counter works at frequency = chipclock/72 */
271 UINT32 eg_timer_add; /* step of eg_timer */
272 UINT32 eg_timer_overflow; /* envelope generator timer overlfows every 1 sample (on real chip) */
273
274 UINT8 rhythm; /* Rhythm mode */
275
276 UINT32 fn_tab[1024]; /* fnumber->increment counter */
277
278 /* LFO */
279 UINT32 LFO_AM;
280 INT32 LFO_PM;
281
282 UINT8 lfo_am_depth;
283 UINT8 lfo_pm_depth_range;
284 UINT32 lfo_am_cnt;
285 UINT32 lfo_am_inc;
286 UINT32 lfo_pm_cnt;
287 UINT32 lfo_pm_inc;
288
289 UINT32 noise_rng; /* 23 bit noise shift register */
290 UINT32 noise_p; /* current noise 'phase' */
291 UINT32 noise_f; /* current noise period */
292
293 UINT8 wavesel; /* waveform select enable flag */
294
295 UINT32 T[2]; /* timer counters */
296 UINT8 st[2]; /* timer enable */
297
298 #if BUILD_Y8950
299 /* Delta-T ADPCM unit (Y8950) */
300
301 YM_DELTAT *deltat;
302
303 /* Keyboard and I/O ports interface */
304 UINT8 portDirection;
305 UINT8 portLatch;
306 OPL_PORTHANDLER_R porthandler_r;
307 OPL_PORTHANDLER_W porthandler_w;
308 void * port_param;
309 OPL_PORTHANDLER_R keyboardhandler_r;
310 OPL_PORTHANDLER_W keyboardhandler_w;
311 void * keyboard_param;
312 #endif
313
314 /* external event callback handlers */
315 OPL_TIMERHANDLER timer_handler; /* TIMER handler */
316 void *TimerParam; /* TIMER parameter */
317 OPL_IRQHANDLER IRQHandler; /* IRQ handler */
318 void *IRQParam; /* IRQ parameter */
319 OPL_UPDATEHANDLER UpdateHandler;/* stream update handler */
320 void *UpdateParam; /* stream update parameter */
321
322 UINT8 type; /* chip type */
323 UINT8 address; /* address register */
324 UINT8 status; /* status flag */
325 UINT8 statusmask; /* status mask */
326 UINT8 mode; /* Reg.08 : CSM,notesel,etc. */
327
328 UINT32 clock; /* master clock (Hz) */
329 UINT32 rate; /* sampling rate (Hz) */
330 double freqbase; /* frequency base */
331 //attotime TimerBase; /* Timer base time (==sampling time)*/
332
333 signed int phase_modulation; /* phase modulation input (SLOT 2) */
334 signed int output[1];
335 #if BUILD_Y8950
336 INT32 output_deltat[4]; /* for Y8950 DELTA-T, chip is mono, that 4 here is just for safety */
337 #endif
338 } FM_OPL;
339
340
341
342 /* mapping of register number (offset) to slot number used by the emulator */
343 static const int slot_array[32]=
344 {
345 0, 2, 4, 1, 3, 5,-1,-1,
346 6, 8,10, 7, 9,11,-1,-1,
347 12,14,16,13,15,17,-1,-1,
348 -1,-1,-1,-1,-1,-1,-1,-1
349 };
350
351 /* key scale level */
352 /* table is 3dB/octave , DV converts this into 6dB/octave */
353 /* 0.1875 is bit 0 weight of the envelope counter (volume) expressed in the 'decibel' scale */
354 #define DV (0.1875/2.0)
355 static const UINT32 ksl_tab[8*16]=
356 {
357 /* OCT 0 */
358 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
359 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
360 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
361 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
362 /* OCT 1 */
363 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
364 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
365 0.000/DV, 0.750/DV, 1.125/DV, 1.500/DV,
366 1.875/DV, 2.250/DV, 2.625/DV, 3.000/DV,
367 /* OCT 2 */
368 0.000/DV, 0.000/DV, 0.000/DV, 0.000/DV,
369 0.000/DV, 1.125/DV, 1.875/DV, 2.625/DV,
370 3.000/DV, 3.750/DV, 4.125/DV, 4.500/DV,
371 4.875/DV, 5.250/DV, 5.625/DV, 6.000/DV,
372 /* OCT 3 */
373 0.000/DV, 0.000/DV, 0.000/DV, 1.875/DV,
374 3.000/DV, 4.125/DV, 4.875/DV, 5.625/DV,
375 6.000/DV, 6.750/DV, 7.125/DV, 7.500/DV,
376 7.875/DV, 8.250/DV, 8.625/DV, 9.000/DV,
377 /* OCT 4 */
378 0.000/DV, 0.000/DV, 3.000/DV, 4.875/DV,
379 6.000/DV, 7.125/DV, 7.875/DV, 8.625/DV,
380 9.000/DV, 9.750/DV,10.125/DV,10.500/DV,
381 10.875/DV,11.250/DV,11.625/DV,12.000/DV,
382 /* OCT 5 */
383 0.000/DV, 3.000/DV, 6.000/DV, 7.875/DV,
384 9.000/DV,10.125/DV,10.875/DV,11.625/DV,
385 12.000/DV,12.750/DV,13.125/DV,13.500/DV,
386 13.875/DV,14.250/DV,14.625/DV,15.000/DV,
387 /* OCT 6 */
388 0.000/DV, 6.000/DV, 9.000/DV,10.875/DV,
389 12.000/DV,13.125/DV,13.875/DV,14.625/DV,
390 15.000/DV,15.750/DV,16.125/DV,16.500/DV,
391 16.875/DV,17.250/DV,17.625/DV,18.000/DV,
392 /* OCT 7 */
393 0.000/DV, 9.000/DV,12.000/DV,13.875/DV,
394 15.000/DV,16.125/DV,16.875/DV,17.625/DV,
395 18.000/DV,18.750/DV,19.125/DV,19.500/DV,
396 19.875/DV,20.250/DV,20.625/DV,21.000/DV
397 };
398 #undef DV
399
400 /* 0 / 3.0 / 1.5 / 6.0 dB/OCT */
401 static const UINT32 ksl_shift[4] = { 31, 1, 2, 0 };
402
403
404 /* sustain level table (3dB per step) */
405 /* 0 - 15: 0, 3, 6, 9,12,15,18,21,24,27,30,33,36,39,42,93 (dB)*/
406 #define SC(db) (UINT32) ( db * (2.0/ENV_STEP) )
407 static const UINT32 sl_tab[16]={
408 SC( 0),SC( 1),SC( 2),SC(3 ),SC(4 ),SC(5 ),SC(6 ),SC( 7),
409 SC( 8),SC( 9),SC(10),SC(11),SC(12),SC(13),SC(14),SC(31)
410 };
411 #undef SC
412
413
414 #define RATE_STEPS (8)
415 static const unsigned char eg_inc[15*RATE_STEPS]={
416
417 /*cycle:0 1 2 3 4 5 6 7*/
418
419 /* 0 */ 0,1, 0,1, 0,1, 0,1, /* rates 00..12 0 (increment by 0 or 1) */
420 /* 1 */ 0,1, 0,1, 1,1, 0,1, /* rates 00..12 1 */
421 /* 2 */ 0,1, 1,1, 0,1, 1,1, /* rates 00..12 2 */
422 /* 3 */ 0,1, 1,1, 1,1, 1,1, /* rates 00..12 3 */
423
424 /* 4 */ 1,1, 1,1, 1,1, 1,1, /* rate 13 0 (increment by 1) */
425 /* 5 */ 1,1, 1,2, 1,1, 1,2, /* rate 13 1 */
426 /* 6 */ 1,2, 1,2, 1,2, 1,2, /* rate 13 2 */
427 /* 7 */ 1,2, 2,2, 1,2, 2,2, /* rate 13 3 */
428
429 /* 8 */ 2,2, 2,2, 2,2, 2,2, /* rate 14 0 (increment by 2) */
430 /* 9 */ 2,2, 2,4, 2,2, 2,4, /* rate 14 1 */
431 /*10 */ 2,4, 2,4, 2,4, 2,4, /* rate 14 2 */
432 /*11 */ 2,4, 4,4, 2,4, 4,4, /* rate 14 3 */
433
434 /*12 */ 4,4, 4,4, 4,4, 4,4, /* rates 15 0, 15 1, 15 2, 15 3 (increment by 4) */
435 /*13 */ 8,8, 8,8, 8,8, 8,8, /* rates 15 2, 15 3 for attack */
436 /*14 */ 0,0, 0,0, 0,0, 0,0, /* infinity rates for attack and decay(s) */
437 };
438
439
440 #define O(a) (a*RATE_STEPS)
441
442 /*note that there is no O(13) in this table - it's directly in the code */
443 static const unsigned char eg_rate_select[16+64+16]={ /* Envelope Generator rates (16 + 64 rates + 16 RKS) */
444 /* 16 infinite time rates */
445 O(14),O(14),O(14),O(14),O(14),O(14),O(14),O(14),
446 O(14),O(14),O(14),O(14),O(14),O(14),O(14),O(14),
447
448 /* rates 00-12 */
449 O( 0),O( 1),O( 2),O( 3),
450 O( 0),O( 1),O( 2),O( 3),
451 O( 0),O( 1),O( 2),O( 3),
452 O( 0),O( 1),O( 2),O( 3),
453 O( 0),O( 1),O( 2),O( 3),
454 O( 0),O( 1),O( 2),O( 3),
455 O( 0),O( 1),O( 2),O( 3),
456 O( 0),O( 1),O( 2),O( 3),
457 O( 0),O( 1),O( 2),O( 3),
458 O( 0),O( 1),O( 2),O( 3),
459 O( 0),O( 1),O( 2),O( 3),
460 O( 0),O( 1),O( 2),O( 3),
461 O( 0),O( 1),O( 2),O( 3),
462
463 /* rate 13 */
464 O( 4),O( 5),O( 6),O( 7),
465
466 /* rate 14 */
467 O( 8),O( 9),O(10),O(11),
468
469 /* rate 15 */
470 O(12),O(12),O(12),O(12),
471
472 /* 16 dummy rates (same as 15 3) */
473 O(12),O(12),O(12),O(12),O(12),O(12),O(12),O(12),
474 O(12),O(12),O(12),O(12),O(12),O(12),O(12),O(12),
475
476 };
477 #undef O
478
479 /*rate 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 */
480 /*shift 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 0, 0, 0 */
481 /*mask 4095, 2047, 1023, 511, 255, 127, 63, 31, 15, 7, 3, 1, 0, 0, 0, 0 */
482
483 #define O(a) (a*1)
484 static const unsigned char eg_rate_shift[16+64+16]={ /* Envelope Generator counter shifts (16 + 64 rates + 16 RKS) */
485 /* 16 infinite time rates */
486 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
487 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
488
489 /* rates 00-12 */
490 O(12),O(12),O(12),O(12),
491 O(11),O(11),O(11),O(11),
492 O(10),O(10),O(10),O(10),
493 O( 9),O( 9),O( 9),O( 9),
494 O( 8),O( 8),O( 8),O( 8),
495 O( 7),O( 7),O( 7),O( 7),
496 O( 6),O( 6),O( 6),O( 6),
497 O( 5),O( 5),O( 5),O( 5),
498 O( 4),O( 4),O( 4),O( 4),
499 O( 3),O( 3),O( 3),O( 3),
500 O( 2),O( 2),O( 2),O( 2),
501 O( 1),O( 1),O( 1),O( 1),
502 O( 0),O( 0),O( 0),O( 0),
503
504 /* rate 13 */
505 O( 0),O( 0),O( 0),O( 0),
506
507 /* rate 14 */
508 O( 0),O( 0),O( 0),O( 0),
509
510 /* rate 15 */
511 O( 0),O( 0),O( 0),O( 0),
512
513 /* 16 dummy rates (same as 15 3) */
514 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
515 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
516
517 };
518 #undef O
519
520
521 /* multiple table */
522 #define ML 2
523 static const UINT8 mul_tab[16]= {
524 /* 1/2, 1, 2, 3, 4, 5, 6, 7, 8, 9,10,10,12,12,15,15 */
525 0.50*ML, 1.00*ML, 2.00*ML, 3.00*ML, 4.00*ML, 5.00*ML, 6.00*ML, 7.00*ML,
526 8.00*ML, 9.00*ML,10.00*ML,10.00*ML,12.00*ML,12.00*ML,15.00*ML,15.00*ML
527 };
528 #undef ML
529
530 /* TL_TAB_LEN is calculated as:
531 * 12 - sinus amplitude bits (Y axis)
532 * 2 - sinus sign bit (Y axis)
533 * TL_RES_LEN - sinus resolution (X axis)
534 */
535 #define TL_TAB_LEN (12*2*TL_RES_LEN)
536 static signed int tl_tab[TL_TAB_LEN];
537
538 #define ENV_QUIET (TL_TAB_LEN>>4)
539
540 /* sin waveform table in 'decibel' scale */
541 /* four waveforms on OPL2 type chips */
542 static unsigned int sin_tab[SIN_LEN * 4];
543
544
545 /* LFO Amplitude Modulation table (verified on real YM3812)
546 27 output levels (triangle waveform); 1 level takes one of: 192, 256 or 448 samples
547
548 Length: 210 elements.
549
550 Each of the elements has to be repeated
551 exactly 64 times (on 64 consecutive samples).
552 The whole table takes: 64 * 210 = 13440 samples.
553
554 When AM = 1 data is used directly
555 When AM = 0 data is divided by 4 before being used (losing precision is important)
556 */
557
558 #define LFO_AM_TAB_ELEMENTS 210
559
560 static const UINT8 lfo_am_table[LFO_AM_TAB_ELEMENTS] = {
561 0,0,0,0,0,0,0,
562 1,1,1,1,
563 2,2,2,2,
564 3,3,3,3,
565 4,4,4,4,
566 5,5,5,5,
567 6,6,6,6,
568 7,7,7,7,
569 8,8,8,8,
570 9,9,9,9,
571 10,10,10,10,
572 11,11,11,11,
573 12,12,12,12,
574 13,13,13,13,
575 14,14,14,14,
576 15,15,15,15,
577 16,16,16,16,
578 17,17,17,17,
579 18,18,18,18,
580 19,19,19,19,
581 20,20,20,20,
582 21,21,21,21,
583 22,22,22,22,
584 23,23,23,23,
585 24,24,24,24,
586 25,25,25,25,
587 26,26,26,
588 25,25,25,25,
589 24,24,24,24,
590 23,23,23,23,
591 22,22,22,22,
592 21,21,21,21,
593 20,20,20,20,
594 19,19,19,19,
595 18,18,18,18,
596 17,17,17,17,
597 16,16,16,16,
598 15,15,15,15,
599 14,14,14,14,
600 13,13,13,13,
601 12,12,12,12,
602 11,11,11,11,
603 10,10,10,10,
604 9,9,9,9,
605 8,8,8,8,
606 7,7,7,7,
607 6,6,6,6,
608 5,5,5,5,
609 4,4,4,4,
610 3,3,3,3,
611 2,2,2,2,
612 1,1,1,1
613 };
614
615 /* LFO Phase Modulation table (verified on real YM3812) */
616 static const INT8 lfo_pm_table[8*8*2] = {
617
618 /* FNUM2/FNUM = 00 0xxxxxxx (0x0000) */
619 0, 0, 0, 0, 0, 0, 0, 0, /*LFO PM depth = 0*/
620 0, 0, 0, 0, 0, 0, 0, 0, /*LFO PM depth = 1*/
621
622 /* FNUM2/FNUM = 00 1xxxxxxx (0x0080) */
623 0, 0, 0, 0, 0, 0, 0, 0, /*LFO PM depth = 0*/
624 1, 0, 0, 0,-1, 0, 0, 0, /*LFO PM depth = 1*/
625
626 /* FNUM2/FNUM = 01 0xxxxxxx (0x0100) */
627 1, 0, 0, 0,-1, 0, 0, 0, /*LFO PM depth = 0*/
628 2, 1, 0,-1,-2,-1, 0, 1, /*LFO PM depth = 1*/
629
630 /* FNUM2/FNUM = 01 1xxxxxxx (0x0180) */
631 1, 0, 0, 0,-1, 0, 0, 0, /*LFO PM depth = 0*/
632 3, 1, 0,-1,-3,-1, 0, 1, /*LFO PM depth = 1*/
633
634 /* FNUM2/FNUM = 10 0xxxxxxx (0x0200) */
635 2, 1, 0,-1,-2,-1, 0, 1, /*LFO PM depth = 0*/
636 4, 2, 0,-2,-4,-2, 0, 2, /*LFO PM depth = 1*/
637
638 /* FNUM2/FNUM = 10 1xxxxxxx (0x0280) */
639 2, 1, 0,-1,-2,-1, 0, 1, /*LFO PM depth = 0*/
640 5, 2, 0,-2,-5,-2, 0, 2, /*LFO PM depth = 1*/
641
642 /* FNUM2/FNUM = 11 0xxxxxxx (0x0300) */
643 3, 1, 0,-1,-3,-1, 0, 1, /*LFO PM depth = 0*/
644 6, 3, 0,-3,-6,-3, 0, 3, /*LFO PM depth = 1*/
645
646 /* FNUM2/FNUM = 11 1xxxxxxx (0x0380) */
647 3, 1, 0,-1,-3,-1, 0, 1, /*LFO PM depth = 0*/
648 7, 3, 0,-3,-7,-3, 0, 3 /*LFO PM depth = 1*/
649 };
650
651
652 /* lock level of common table */
653 static int num_lock = 0;
654
655
656 #define SLOT7_1 (&OPL->P_CH[7].SLOT[SLOT1])
657 #define SLOT7_2 (&OPL->P_CH[7].SLOT[SLOT2])
658 #define SLOT8_1 (&OPL->P_CH[8].SLOT[SLOT1])
659 #define SLOT8_2 (&OPL->P_CH[8].SLOT[SLOT2])
660
661
662
663
664 /*INLINE int limit( int val, int max, int min ) {
665 if ( val > max )
666 val = max;
667 else if ( val < min )
668 val = min;
669
670 return val;
671 }*/
672
673
674 /* status set and IRQ handling */
OPL_STATUS_SET(FM_OPL * OPL,int flag)675 INLINE void OPL_STATUS_SET(FM_OPL *OPL,int flag)
676 {
677 /* set status flag */
678 OPL->status |= flag;
679 if(!(OPL->status & 0x80))
680 {
681 if(OPL->status & OPL->statusmask)
682 { /* IRQ on */
683 OPL->status |= 0x80;
684 /* callback user interrupt handler (IRQ is OFF to ON) */
685 if(OPL->IRQHandler) (OPL->IRQHandler)(OPL->IRQParam,1);
686 }
687 }
688 }
689
690 /* status reset and IRQ handling */
OPL_STATUS_RESET(FM_OPL * OPL,int flag)691 INLINE void OPL_STATUS_RESET(FM_OPL *OPL,int flag)
692 {
693 /* reset status flag */
694 OPL->status &=~flag;
695 if((OPL->status & 0x80))
696 {
697 if (!(OPL->status & OPL->statusmask) )
698 {
699 OPL->status &= 0x7f;
700 /* callback user interrupt handler (IRQ is ON to OFF) */
701 if(OPL->IRQHandler) (OPL->IRQHandler)(OPL->IRQParam,0);
702 }
703 }
704 }
705
706 /* IRQ mask set */
OPL_STATUSMASK_SET(FM_OPL * OPL,int flag)707 INLINE void OPL_STATUSMASK_SET(FM_OPL *OPL,int flag)
708 {
709 OPL->statusmask = flag;
710 /* IRQ handling check */
711 OPL_STATUS_SET(OPL,0);
712 OPL_STATUS_RESET(OPL,0);
713 }
714
715
716 /* advance LFO to next sample */
advance_lfo(FM_OPL * OPL)717 INLINE void advance_lfo(FM_OPL *OPL)
718 {
719 UINT8 tmp;
720
721 /* LFO */
722 OPL->lfo_am_cnt += OPL->lfo_am_inc;
723 if (OPL->lfo_am_cnt >= ((UINT32)LFO_AM_TAB_ELEMENTS<<LFO_SH) ) /* lfo_am_table is 210 elements long */
724 OPL->lfo_am_cnt -= ((UINT32)LFO_AM_TAB_ELEMENTS<<LFO_SH);
725
726 tmp = lfo_am_table[ OPL->lfo_am_cnt >> LFO_SH ];
727
728 if (OPL->lfo_am_depth)
729 OPL->LFO_AM = tmp;
730 else
731 OPL->LFO_AM = tmp>>2;
732
733 OPL->lfo_pm_cnt += OPL->lfo_pm_inc;
734 OPL->LFO_PM = ((OPL->lfo_pm_cnt>>LFO_SH) & 7) | OPL->lfo_pm_depth_range;
735 }
736
refresh_eg(FM_OPL * OPL)737 INLINE void refresh_eg(FM_OPL* OPL)
738 {
739 OPL_CH *CH;
740 OPL_SLOT *op;
741 int i;
742 int new_vol;
743
744 for (i=0; i<9*2; i++)
745 {
746 CH = &OPL->P_CH[i/2];
747 op = &CH->SLOT[i&1];
748
749 // Envelope Generator
750 switch(op->state)
751 {
752 case EG_ATT: // attack phase
753 if ( !(OPL->eg_cnt & ((1<<op->eg_sh_ar)-1) ) )
754 {
755 new_vol = op->volume + ((~op->volume *
756 (eg_inc[op->eg_sel_ar + ((OPL->eg_cnt>>op->eg_sh_ar)&7)])
757 ) >> 3);
758 if (new_vol <= MIN_ATT_INDEX)
759 {
760 op->volume = MIN_ATT_INDEX;
761 op->state = EG_DEC;
762 }
763 }
764 break;
765 /*case EG_DEC: // decay phase
766 if ( !(OPL->eg_cnt & ((1<<op->eg_sh_dr)-1) ) )
767 {
768 new_vol = op->volume + eg_inc[op->eg_sel_dr + ((OPL->eg_cnt>>op->eg_sh_dr)&7)];
769
770 if ( new_vol >= op->sl )
771 op->state = EG_SUS;
772 }
773 break;
774 case EG_SUS: // sustain phase
775 if ( !op->eg_type) percussive mode
776 {
777 new_vol = op->volume + eg_inc[op->eg_sel_rr + ((OPL->eg_cnt>>op->eg_sh_rr)&7)];
778
779 if ( !(OPL->eg_cnt & ((1<<op->eg_sh_rr)-1) ) )
780 {
781 if ( new_vol >= MAX_ATT_INDEX )
782 op->volume = MAX_ATT_INDEX;
783 }
784 }
785 break;
786 case EG_REL: // release phase
787 if ( !(OPL->eg_cnt & ((1<<op->eg_sh_rr)-1) ) )
788 {
789 new_vol = op->volume + eg_inc[op->eg_sel_rr + ((OPL->eg_cnt>>op->eg_sh_rr)&7)];
790 if ( new_vol >= MAX_ATT_INDEX )
791 {
792 op->volume = MAX_ATT_INDEX;
793 op->state = EG_OFF;
794 }
795
796 }
797 break;
798 default:
799 break;*/
800 }
801 }
802
803 return;
804 }
805
806 /* advance to next sample */
advance(FM_OPL * OPL)807 INLINE void advance(FM_OPL *OPL)
808 {
809 OPL_CH *CH;
810 OPL_SLOT *op;
811 int i;
812
813 OPL->eg_timer += OPL->eg_timer_add;
814
815 while (OPL->eg_timer >= OPL->eg_timer_overflow)
816 {
817 OPL->eg_timer -= OPL->eg_timer_overflow;
818
819 OPL->eg_cnt++;
820
821 for (i=0; i<9*2; i++)
822 {
823 CH = &OPL->P_CH[i/2];
824 op = &CH->SLOT[i&1];
825
826 /* Envelope Generator */
827 switch(op->state)
828 {
829 case EG_ATT: /* attack phase */
830 if ( !(OPL->eg_cnt & ((1<<op->eg_sh_ar)-1) ) )
831 {
832 op->volume += (~op->volume *
833 (eg_inc[op->eg_sel_ar + ((OPL->eg_cnt>>op->eg_sh_ar)&7)])
834 ) >>3;
835
836 if (op->volume <= MIN_ATT_INDEX)
837 {
838 op->volume = MIN_ATT_INDEX;
839 op->state = EG_DEC;
840 }
841
842 }
843 break;
844
845 case EG_DEC: /* decay phase */
846 if ( !(OPL->eg_cnt & ((1<<op->eg_sh_dr)-1) ) )
847 {
848 op->volume += eg_inc[op->eg_sel_dr + ((OPL->eg_cnt>>op->eg_sh_dr)&7)];
849
850 if ( op->volume >= op->sl )
851 op->state = EG_SUS;
852
853 }
854 break;
855
856 case EG_SUS: /* sustain phase */
857
858 /* this is important behaviour:
859 one can change percusive/non-percussive modes on the fly and
860 the chip will remain in sustain phase - verified on real YM3812 */
861
862 if(op->eg_type) /* non-percussive mode */
863 {
864 /* do nothing */
865 }
866 else /* percussive mode */
867 {
868 /* during sustain phase chip adds Release Rate (in percussive mode) */
869 if ( !(OPL->eg_cnt & ((1<<op->eg_sh_rr)-1) ) )
870 {
871 op->volume += eg_inc[op->eg_sel_rr + ((OPL->eg_cnt>>op->eg_sh_rr)&7)];
872
873 if ( op->volume >= MAX_ATT_INDEX )
874 op->volume = MAX_ATT_INDEX;
875 }
876 /* else do nothing in sustain phase */
877 }
878 break;
879
880 case EG_REL: /* release phase */
881 if ( !(OPL->eg_cnt & ((1<<op->eg_sh_rr)-1) ) )
882 {
883 op->volume += eg_inc[op->eg_sel_rr + ((OPL->eg_cnt>>op->eg_sh_rr)&7)];
884
885 if ( op->volume >= MAX_ATT_INDEX )
886 {
887 op->volume = MAX_ATT_INDEX;
888 op->state = EG_OFF;
889 }
890
891 }
892 break;
893
894 default:
895 break;
896 }
897 }
898 }
899
900 for (i=0; i<9*2; i++)
901 {
902 CH = &OPL->P_CH[i/2];
903 op = &CH->SLOT[i&1];
904
905 /* Phase Generator */
906 if(op->vib)
907 {
908 UINT8 block;
909 unsigned int block_fnum = CH->block_fnum;
910
911 unsigned int fnum_lfo = (block_fnum&0x0380) >> 7;
912
913 signed int lfo_fn_table_index_offset = lfo_pm_table[OPL->LFO_PM + 16*fnum_lfo ];
914
915 if (lfo_fn_table_index_offset) /* LFO phase modulation active */
916 {
917 block_fnum += lfo_fn_table_index_offset;
918 block = (block_fnum&0x1c00) >> 10;
919 op->Cnt += (OPL->fn_tab[block_fnum&0x03ff] >> (7-block)) * op->mul;
920 }
921 else /* LFO phase modulation = zero */
922 {
923 op->Cnt += op->Incr;
924 }
925 }
926 else /* LFO phase modulation disabled for this operator */
927 {
928 op->Cnt += op->Incr;
929 }
930 }
931
932 /* The Noise Generator of the YM3812 is 23-bit shift register.
933 * Period is equal to 2^23-2 samples.
934 * Register works at sampling frequency of the chip, so output
935 * can change on every sample.
936 *
937 * Output of the register and input to the bit 22 is:
938 * bit0 XOR bit14 XOR bit15 XOR bit22
939 *
940 * Simply use bit 22 as the noise output.
941 */
942
943 OPL->noise_p += OPL->noise_f;
944 i = OPL->noise_p >> FREQ_SH; /* number of events (shifts of the shift register) */
945 OPL->noise_p &= FREQ_MASK;
946 while (i)
947 {
948 /*
949 UINT32 j;
950 j = ( (OPL->noise_rng) ^ (OPL->noise_rng>>14) ^ (OPL->noise_rng>>15) ^ (OPL->noise_rng>>22) ) & 1;
951 OPL->noise_rng = (j<<22) | (OPL->noise_rng>>1);
952 */
953
954 /*
955 Instead of doing all the logic operations above, we
956 use a trick here (and use bit 0 as the noise output).
957 The difference is only that the noise bit changes one
958 step ahead. This doesn't matter since we don't know
959 what is real state of the noise_rng after the reset.
960 */
961
962 if (OPL->noise_rng & 1) OPL->noise_rng ^= 0x800302;
963 OPL->noise_rng >>= 1;
964
965 i--;
966 }
967 }
968
969
op_calc(UINT32 phase,unsigned int env,signed int pm,unsigned int wave_tab)970 INLINE signed int op_calc(UINT32 phase, unsigned int env, signed int pm, unsigned int wave_tab)
971 {
972 UINT32 p;
973
974 p = (env<<4) + sin_tab[wave_tab + ((((signed int)((phase & ~FREQ_MASK) + (pm<<16))) >> FREQ_SH ) & SIN_MASK) ];
975
976 if (p >= TL_TAB_LEN)
977 return 0;
978 return tl_tab[p];
979 }
980
op_calc1(UINT32 phase,unsigned int env,signed int pm,unsigned int wave_tab)981 INLINE signed int op_calc1(UINT32 phase, unsigned int env, signed int pm, unsigned int wave_tab)
982 {
983 UINT32 p;
984
985 p = (env<<4) + sin_tab[wave_tab + ((((signed int)((phase & ~FREQ_MASK) + pm )) >> FREQ_SH ) & SIN_MASK) ];
986
987 if (p >= TL_TAB_LEN)
988 return 0;
989 return tl_tab[p];
990 }
991
992
993 #define volume_calc(OP) ((OP)->TLL + ((UINT32)(OP)->volume) + (OPL->LFO_AM & (OP)->AMmask))
994
995 /* calculate output */
OPL_CALC_CH(FM_OPL * OPL,OPL_CH * CH)996 INLINE void OPL_CALC_CH( FM_OPL *OPL, OPL_CH *CH )
997 {
998 OPL_SLOT *SLOT;
999 unsigned int env;
1000 signed int out;
1001
1002 if (CH->Muted)
1003 return;
1004
1005 OPL->phase_modulation = 0;
1006
1007 /* SLOT 1 */
1008 SLOT = &CH->SLOT[SLOT1];
1009 env = volume_calc(SLOT);
1010 out = SLOT->op1_out[0] + SLOT->op1_out[1];
1011 SLOT->op1_out[0] = SLOT->op1_out[1];
1012 *SLOT->connect1 += SLOT->op1_out[0];
1013 SLOT->op1_out[1] = 0;
1014 if( env < ENV_QUIET )
1015 {
1016 if (!SLOT->FB)
1017 out = 0;
1018 SLOT->op1_out[1] = op_calc1(SLOT->Cnt, env, (out<<SLOT->FB), SLOT->wavetable );
1019 }
1020
1021 /* SLOT 2 */
1022 SLOT++;
1023 env = volume_calc(SLOT);
1024 if( env < ENV_QUIET )
1025 OPL->output[0] += op_calc(SLOT->Cnt, env, OPL->phase_modulation, SLOT->wavetable);
1026 }
1027
1028 /*
1029 operators used in the rhythm sounds generation process:
1030
1031 Envelope Generator:
1032
1033 channel operator register number Bass High Snare Tom Top
1034 / slot number TL ARDR SLRR Wave Drum Hat Drum Tom Cymbal
1035 6 / 0 12 50 70 90 f0 +
1036 6 / 1 15 53 73 93 f3 +
1037 7 / 0 13 51 71 91 f1 +
1038 7 / 1 16 54 74 94 f4 +
1039 8 / 0 14 52 72 92 f2 +
1040 8 / 1 17 55 75 95 f5 +
1041
1042 Phase Generator:
1043
1044 channel operator register number Bass High Snare Tom Top
1045 / slot number MULTIPLE Drum Hat Drum Tom Cymbal
1046 6 / 0 12 30 +
1047 6 / 1 15 33 +
1048 7 / 0 13 31 + + +
1049 7 / 1 16 34 ----- n o t u s e d -----
1050 8 / 0 14 32 +
1051 8 / 1 17 35 + +
1052
1053 channel operator register number Bass High Snare Tom Top
1054 number number BLK/FNUM2 FNUM Drum Hat Drum Tom Cymbal
1055 6 12,15 B6 A6 +
1056
1057 7 13,16 B7 A7 + + +
1058
1059 8 14,17 B8 A8 + + +
1060
1061 */
1062
1063 /* calculate rhythm */
1064
OPL_CALC_RH(FM_OPL * OPL,OPL_CH * CH,unsigned int noise)1065 INLINE void OPL_CALC_RH( FM_OPL *OPL, OPL_CH *CH, unsigned int noise )
1066 {
1067 OPL_SLOT *SLOT;
1068 signed int out;
1069 unsigned int env;
1070
1071
1072 /* Bass Drum (verified on real YM3812):
1073 - depends on the channel 6 'connect' register:
1074 when connect = 0 it works the same as in normal (non-rhythm) mode (op1->op2->out)
1075 when connect = 1 _only_ operator 2 is present on output (op2->out), operator 1 is ignored
1076 - output sample always is multiplied by 2
1077 */
1078
1079 OPL->phase_modulation = 0;
1080 /* SLOT 1 */
1081 SLOT = &CH[6].SLOT[SLOT1];
1082 env = volume_calc(SLOT);
1083
1084 out = SLOT->op1_out[0] + SLOT->op1_out[1];
1085 SLOT->op1_out[0] = SLOT->op1_out[1];
1086
1087 if (!SLOT->CON)
1088 OPL->phase_modulation = SLOT->op1_out[0];
1089 /* else ignore output of operator 1 */
1090
1091 SLOT->op1_out[1] = 0;
1092 if( env < ENV_QUIET )
1093 {
1094 if (!SLOT->FB)
1095 out = 0;
1096 SLOT->op1_out[1] = op_calc1(SLOT->Cnt, env, (out<<SLOT->FB), SLOT->wavetable );
1097 }
1098
1099 /* SLOT 2 */
1100 SLOT++;
1101 env = volume_calc(SLOT);
1102 if( env < ENV_QUIET && ! OPL->MuteSpc[0] )
1103 OPL->output[0] += op_calc(SLOT->Cnt, env, OPL->phase_modulation, SLOT->wavetable) * 2;
1104
1105
1106 /* Phase generation is based on: */
1107 /* HH (13) channel 7->slot 1 combined with channel 8->slot 2 (same combination as TOP CYMBAL but different output phases) */
1108 /* SD (16) channel 7->slot 1 */
1109 /* TOM (14) channel 8->slot 1 */
1110 /* TOP (17) channel 7->slot 1 combined with channel 8->slot 2 (same combination as HIGH HAT but different output phases) */
1111
1112 /* Envelope generation based on: */
1113 /* HH channel 7->slot1 */
1114 /* SD channel 7->slot2 */
1115 /* TOM channel 8->slot1 */
1116 /* TOP channel 8->slot2 */
1117
1118
1119 /* The following formulas can be well optimized.
1120 I leave them in direct form for now (in case I've missed something).
1121 */
1122
1123 /* High Hat (verified on real YM3812) */
1124 env = volume_calc(SLOT7_1);
1125 if( env < ENV_QUIET && ! OPL->MuteSpc[4] )
1126 {
1127
1128 /* high hat phase generation:
1129 phase = d0 or 234 (based on frequency only)
1130 phase = 34 or 2d0 (based on noise)
1131 */
1132
1133 /* base frequency derived from operator 1 in channel 7 */
1134 unsigned char bit7 = ((SLOT7_1->Cnt>>FREQ_SH)>>7)&1;
1135 unsigned char bit3 = ((SLOT7_1->Cnt>>FREQ_SH)>>3)&1;
1136 unsigned char bit2 = ((SLOT7_1->Cnt>>FREQ_SH)>>2)&1;
1137
1138 unsigned char res1 = (bit2 ^ bit7) | bit3;
1139
1140 /* when res1 = 0 phase = 0x000 | 0xd0; */
1141 /* when res1 = 1 phase = 0x200 | (0xd0>>2); */
1142 UINT32 phase = res1 ? (0x200|(0xd0>>2)) : 0xd0;
1143
1144 /* enable gate based on frequency of operator 2 in channel 8 */
1145 unsigned char bit5e= ((SLOT8_2->Cnt>>FREQ_SH)>>5)&1;
1146 unsigned char bit3e= ((SLOT8_2->Cnt>>FREQ_SH)>>3)&1;
1147
1148 unsigned char res2 = (bit3e ^ bit5e);
1149
1150 /* when res2 = 0 pass the phase from calculation above (res1); */
1151 /* when res2 = 1 phase = 0x200 | (0xd0>>2); */
1152 if (res2)
1153 phase = (0x200|(0xd0>>2));
1154
1155
1156 /* when phase & 0x200 is set and noise=1 then phase = 0x200|0xd0 */
1157 /* when phase & 0x200 is set and noise=0 then phase = 0x200|(0xd0>>2), ie no change */
1158 if (phase&0x200)
1159 {
1160 if (noise)
1161 phase = 0x200|0xd0;
1162 }
1163 else
1164 /* when phase & 0x200 is clear and noise=1 then phase = 0xd0>>2 */
1165 /* when phase & 0x200 is clear and noise=0 then phase = 0xd0, ie no change */
1166 {
1167 if (noise)
1168 phase = 0xd0>>2;
1169 }
1170
1171 OPL->output[0] += op_calc(phase<<FREQ_SH, env, 0, SLOT7_1->wavetable) * 2;
1172 }
1173
1174 /* Snare Drum (verified on real YM3812) */
1175 env = volume_calc(SLOT7_2);
1176 if( env < ENV_QUIET && ! OPL->MuteSpc[1] )
1177 {
1178 /* base frequency derived from operator 1 in channel 7 */
1179 unsigned char bit8 = ((SLOT7_1->Cnt>>FREQ_SH)>>8)&1;
1180
1181 /* when bit8 = 0 phase = 0x100; */
1182 /* when bit8 = 1 phase = 0x200; */
1183 UINT32 phase = bit8 ? 0x200 : 0x100;
1184
1185 /* Noise bit XOR'es phase by 0x100 */
1186 /* when noisebit = 0 pass the phase from calculation above */
1187 /* when noisebit = 1 phase ^= 0x100; */
1188 /* in other words: phase ^= (noisebit<<8); */
1189 if (noise)
1190 phase ^= 0x100;
1191
1192 OPL->output[0] += op_calc(phase<<FREQ_SH, env, 0, SLOT7_2->wavetable) * 2;
1193 }
1194
1195 /* Tom Tom (verified on real YM3812) */
1196 env = volume_calc(SLOT8_1);
1197 if( env < ENV_QUIET && ! OPL->MuteSpc[2] )
1198 OPL->output[0] += op_calc(SLOT8_1->Cnt, env, 0, SLOT8_1->wavetable) * 2;
1199
1200 /* Top Cymbal (verified on real YM3812) */
1201 env = volume_calc(SLOT8_2);
1202 if( env < ENV_QUIET && ! OPL->MuteSpc[3] )
1203 {
1204 /* base frequency derived from operator 1 in channel 7 */
1205 unsigned char bit7 = ((SLOT7_1->Cnt>>FREQ_SH)>>7)&1;
1206 unsigned char bit3 = ((SLOT7_1->Cnt>>FREQ_SH)>>3)&1;
1207 unsigned char bit2 = ((SLOT7_1->Cnt>>FREQ_SH)>>2)&1;
1208
1209 unsigned char res1 = (bit2 ^ bit7) | bit3;
1210
1211 /* when res1 = 0 phase = 0x000 | 0x100; */
1212 /* when res1 = 1 phase = 0x200 | 0x100; */
1213 UINT32 phase = res1 ? 0x300 : 0x100;
1214
1215 /* enable gate based on frequency of operator 2 in channel 8 */
1216 unsigned char bit5e= ((SLOT8_2->Cnt>>FREQ_SH)>>5)&1;
1217 unsigned char bit3e= ((SLOT8_2->Cnt>>FREQ_SH)>>3)&1;
1218
1219 unsigned char res2 = (bit3e ^ bit5e);
1220 /* when res2 = 0 pass the phase from calculation above (res1); */
1221 /* when res2 = 1 phase = 0x200 | 0x100; */
1222 if (res2)
1223 phase = 0x300;
1224
1225 OPL->output[0] += op_calc(phase<<FREQ_SH, env, 0, SLOT8_2->wavetable) * 2;
1226 }
1227 }
1228
1229
1230 /* generic table initialize */
init_tables(void)1231 static int init_tables(void)
1232 {
1233 signed int i,x;
1234 signed int n;
1235 double o,m;
1236
1237
1238 for (x=0; x<TL_RES_LEN; x++)
1239 {
1240 m = (1<<16) / pow(2, (x+1) * (ENV_STEP/4.0) / 8.0);
1241 m = floor(m);
1242
1243 /* we never reach (1<<16) here due to the (x+1) */
1244 /* result fits within 16 bits at maximum */
1245
1246 n = (int)m; /* 16 bits here */
1247 n >>= 4; /* 12 bits here */
1248 if (n&1) /* round to nearest */
1249 n = (n>>1)+1;
1250 else
1251 n = n>>1;
1252 /* 11 bits here (rounded) */
1253 n <<= 1; /* 12 bits here (as in real chip) */
1254 tl_tab[ x*2 + 0 ] = n;
1255 tl_tab[ x*2 + 1 ] = -tl_tab[ x*2 + 0 ];
1256
1257 for (i=1; i<12; i++)
1258 {
1259 tl_tab[ x*2+0 + i*2*TL_RES_LEN ] = tl_tab[ x*2+0 ]>>i;
1260 tl_tab[ x*2+1 + i*2*TL_RES_LEN ] = -tl_tab[ x*2+0 + i*2*TL_RES_LEN ];
1261 }
1262 #if 0
1263 logerror("tl %04i", x*2);
1264 for (i=0; i<12; i++)
1265 logerror(", [%02i] %5i", i*2, tl_tab[ x*2 /*+1*/ + i*2*TL_RES_LEN ] );
1266 logerror("\n");
1267 #endif
1268 }
1269 /*logerror("FMOPL.C: TL_TAB_LEN = %i elements (%i bytes)\n",TL_TAB_LEN, (int)sizeof(tl_tab));*/
1270
1271
1272 for (i=0; i<SIN_LEN; i++)
1273 {
1274 /* non-standard sinus */
1275 m = sin( ((i*2)+1) * M_PI / SIN_LEN ); /* checked against the real chip */
1276
1277 /* we never reach zero here due to ((i*2)+1) */
1278
1279 if (m>0.0)
1280 o = 8*log(1.0/m)/log(2.0); /* convert to 'decibels' */
1281 else
1282 o = 8*log(-1.0/m)/log(2.0); /* convert to 'decibels' */
1283
1284 o = o / (ENV_STEP/4);
1285
1286 n = (int)(2.0*o);
1287 if (n&1) /* round to nearest */
1288 n = (n>>1)+1;
1289 else
1290 n = n>>1;
1291
1292 sin_tab[ i ] = n*2 + (m>=0.0? 0: 1 );
1293
1294 /*logerror("FMOPL.C: sin [%4i (hex=%03x)]= %4i (tl_tab value=%5i)\n", i, i, sin_tab[i], tl_tab[sin_tab[i]] );*/
1295 }
1296
1297 for (i=0; i<SIN_LEN; i++)
1298 {
1299 /* waveform 1: __ __ */
1300 /* / \____/ \____*/
1301 /* output only first half of the sinus waveform (positive one) */
1302
1303 if (i & (1<<(SIN_BITS-1)) )
1304 sin_tab[1*SIN_LEN+i] = TL_TAB_LEN;
1305 else
1306 sin_tab[1*SIN_LEN+i] = sin_tab[i];
1307
1308 /* waveform 2: __ __ __ __ */
1309 /* / \/ \/ \/ \*/
1310 /* abs(sin) */
1311
1312 sin_tab[2*SIN_LEN+i] = sin_tab[i & (SIN_MASK>>1) ];
1313
1314 /* waveform 3: _ _ _ _ */
1315 /* / |_/ |_/ |_/ |_*/
1316 /* abs(output only first quarter of the sinus waveform) */
1317
1318 if (i & (1<<(SIN_BITS-2)) )
1319 sin_tab[3*SIN_LEN+i] = TL_TAB_LEN;
1320 else
1321 sin_tab[3*SIN_LEN+i] = sin_tab[i & (SIN_MASK>>2)];
1322
1323 /*logerror("FMOPL.C: sin1[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[1*SIN_LEN+i], tl_tab[sin_tab[1*SIN_LEN+i]] );
1324 logerror("FMOPL.C: sin2[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[2*SIN_LEN+i], tl_tab[sin_tab[2*SIN_LEN+i]] );
1325 logerror("FMOPL.C: sin3[%4i]= %4i (tl_tab value=%5i)\n", i, sin_tab[3*SIN_LEN+i], tl_tab[sin_tab[3*SIN_LEN+i]] );*/
1326 }
1327 /*logerror("FMOPL.C: ENV_QUIET= %08x (dec*8=%i)\n", ENV_QUIET, ENV_QUIET*8 );*/
1328
1329
1330 #ifdef SAVE_SAMPLE
1331 sample[0]=fopen("sampsum.pcm","wb");
1332 #endif
1333
1334 return 1;
1335 }
1336
OPLCloseTable(void)1337 static void OPLCloseTable( void )
1338 {
1339 #ifdef SAVE_SAMPLE
1340 fclose(sample[0]);
1341 #endif
1342 }
1343
1344
1345
OPL_initalize(FM_OPL * OPL)1346 static void OPL_initalize(FM_OPL *OPL)
1347 {
1348 int i;
1349
1350 /* frequency base */
1351 OPL->freqbase = (OPL->rate) ? ((double)OPL->clock / 72.0) / OPL->rate : 0;
1352 #if 0
1353 OPL->rate = (double)OPL->clock / 72.0;
1354 OPL->freqbase = 1.0;
1355 #endif
1356
1357 /*logerror("freqbase=%f\n", OPL->freqbase);*/
1358
1359 /* Timer base time */
1360 //OPL->TimerBase = attotime_mul(ATTOTIME_IN_HZ(OPL->clock), 72);
1361
1362 /* make fnumber -> increment counter table */
1363 for( i=0 ; i < 1024 ; i++ )
1364 {
1365 /* opn phase increment counter = 20bit */
1366 OPL->fn_tab[i] = (UINT32)( (double)i * 64 * OPL->freqbase * (1<<(FREQ_SH-10)) ); /* -10 because chip works with 10.10 fixed point, while we use 16.16 */
1367 #if 0
1368 logerror("FMOPL.C: fn_tab[%4i] = %08x (dec=%8i)\n",
1369 i, OPL->fn_tab[i]>>6, OPL->fn_tab[i]>>6 );
1370 #endif
1371 }
1372
1373 #if 0
1374 for( i=0 ; i < 16 ; i++ )
1375 {
1376 logerror("FMOPL.C: sl_tab[%i] = %08x\n",
1377 i, sl_tab[i] );
1378 }
1379 for( i=0 ; i < 8 ; i++ )
1380 {
1381 int j;
1382 logerror("FMOPL.C: ksl_tab[oct=%2i] =",i);
1383 for (j=0; j<16; j++)
1384 {
1385 logerror("%08x ", ksl_tab[i*16+j] );
1386 }
1387 logerror("\n");
1388 }
1389 #endif
1390
1391 for(i = 0; i < 9; i ++)
1392 OPL->P_CH[i].Muted = 0x00;
1393 for(i = 0; i < 6; i ++)
1394 OPL->MuteSpc[i] = 0x00;
1395
1396
1397 /* Amplitude modulation: 27 output levels (triangle waveform); 1 level takes one of: 192, 256 or 448 samples */
1398 /* One entry from LFO_AM_TABLE lasts for 64 samples */
1399 OPL->lfo_am_inc = (1.0 / 64.0 ) * (1<<LFO_SH) * OPL->freqbase;
1400
1401 /* Vibrato: 8 output levels (triangle waveform); 1 level takes 1024 samples */
1402 OPL->lfo_pm_inc = (1.0 / 1024.0) * (1<<LFO_SH) * OPL->freqbase;
1403
1404 /*logerror ("OPL->lfo_am_inc = %8x ; OPL->lfo_pm_inc = %8x\n", OPL->lfo_am_inc, OPL->lfo_pm_inc);*/
1405
1406 /* Noise generator: a step takes 1 sample */
1407 OPL->noise_f = (1.0 / 1.0) * (1<<FREQ_SH) * OPL->freqbase;
1408
1409 OPL->eg_timer_add = (1<<EG_SH) * OPL->freqbase;
1410 OPL->eg_timer_overflow = ( 1 ) * (1<<EG_SH);
1411 /*logerror("OPLinit eg_timer_add=%8x eg_timer_overflow=%8x\n", OPL->eg_timer_add, OPL->eg_timer_overflow);*/
1412
1413 }
1414
FM_KEYON(OPL_SLOT * SLOT,UINT32 key_set)1415 INLINE void FM_KEYON(OPL_SLOT *SLOT, UINT32 key_set)
1416 {
1417 if( !SLOT->key )
1418 {
1419 /* restart Phase Generator */
1420 SLOT->Cnt = 0;
1421 /* phase -> Attack */
1422 SLOT->state = EG_ATT;
1423 }
1424 SLOT->key |= key_set;
1425 }
1426
FM_KEYOFF(OPL_SLOT * SLOT,UINT32 key_clr)1427 INLINE void FM_KEYOFF(OPL_SLOT *SLOT, UINT32 key_clr)
1428 {
1429 if( SLOT->key )
1430 {
1431 SLOT->key &= key_clr;
1432
1433 if( !SLOT->key )
1434 {
1435 /* phase -> Release */
1436 if (SLOT->state>EG_REL)
1437 SLOT->state = EG_REL;
1438 }
1439 }
1440 }
1441
1442 /* update phase increment counter of operator (also update the EG rates if necessary) */
CALC_FCSLOT(OPL_CH * CH,OPL_SLOT * SLOT)1443 INLINE void CALC_FCSLOT(OPL_CH *CH,OPL_SLOT *SLOT)
1444 {
1445 int ksr;
1446
1447 /* (frequency) phase increment counter */
1448 SLOT->Incr = CH->fc * SLOT->mul;
1449 ksr = CH->kcode >> SLOT->KSR;
1450
1451 if( SLOT->ksr != ksr )
1452 {
1453 SLOT->ksr = ksr;
1454
1455 /* calculate envelope generator rates */
1456 if ((SLOT->ar + SLOT->ksr) < 16+62)
1457 {
1458 SLOT->eg_sh_ar = eg_rate_shift [SLOT->ar + SLOT->ksr ];
1459 SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr ];
1460 }
1461 else
1462 {
1463 SLOT->eg_sh_ar = 0;
1464 SLOT->eg_sel_ar = 13*RATE_STEPS;
1465 }
1466 SLOT->eg_sh_dr = eg_rate_shift [SLOT->dr + SLOT->ksr ];
1467 SLOT->eg_sel_dr = eg_rate_select[SLOT->dr + SLOT->ksr ];
1468 SLOT->eg_sh_rr = eg_rate_shift [SLOT->rr + SLOT->ksr ];
1469 SLOT->eg_sel_rr = eg_rate_select[SLOT->rr + SLOT->ksr ];
1470 }
1471 }
1472
1473 /* set multi,am,vib,EG-TYP,KSR,mul */
set_mul(FM_OPL * OPL,int slot,int v)1474 INLINE void set_mul(FM_OPL *OPL,int slot,int v)
1475 {
1476 OPL_CH *CH = &OPL->P_CH[slot/2];
1477 OPL_SLOT *SLOT = &CH->SLOT[slot&1];
1478
1479 SLOT->mul = mul_tab[v&0x0f];
1480 SLOT->KSR = (v&0x10) ? 0 : 2;
1481 SLOT->eg_type = (v&0x20);
1482 SLOT->vib = (v&0x40);
1483 SLOT->AMmask = (v&0x80) ? ~0 : 0;
1484 CALC_FCSLOT(CH,SLOT);
1485 }
1486
1487 /* set ksl & tl */
set_ksl_tl(FM_OPL * OPL,int slot,int v)1488 INLINE void set_ksl_tl(FM_OPL *OPL,int slot,int v)
1489 {
1490 OPL_CH *CH = &OPL->P_CH[slot/2];
1491 OPL_SLOT *SLOT = &CH->SLOT[slot&1];
1492
1493 SLOT->ksl = ksl_shift[v >> 6];
1494 SLOT->TL = (v&0x3f)<<(ENV_BITS-1-7); /* 7 bits TL (bit 6 = always 0) */
1495
1496 SLOT->TLL = SLOT->TL + (CH->ksl_base>>SLOT->ksl);
1497 }
1498
1499 /* set attack rate & decay rate */
set_ar_dr(FM_OPL * OPL,int slot,int v)1500 INLINE void set_ar_dr(FM_OPL *OPL,int slot,int v)
1501 {
1502 OPL_CH *CH = &OPL->P_CH[slot/2];
1503 OPL_SLOT *SLOT = &CH->SLOT[slot&1];
1504
1505 SLOT->ar = (v>>4) ? 16 + ((v>>4) <<2) : 0;
1506
1507 if ((SLOT->ar + SLOT->ksr) < 16+62)
1508 {
1509 SLOT->eg_sh_ar = eg_rate_shift [SLOT->ar + SLOT->ksr ];
1510 SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr ];
1511 }
1512 else
1513 {
1514 SLOT->eg_sh_ar = 0;
1515 SLOT->eg_sel_ar = 13*RATE_STEPS;
1516 }
1517
1518 SLOT->dr = (v&0x0f)? 16 + ((v&0x0f)<<2) : 0;
1519 SLOT->eg_sh_dr = eg_rate_shift [SLOT->dr + SLOT->ksr ];
1520 SLOT->eg_sel_dr = eg_rate_select[SLOT->dr + SLOT->ksr ];
1521 }
1522
1523 /* set sustain level & release rate */
set_sl_rr(FM_OPL * OPL,int slot,int v)1524 INLINE void set_sl_rr(FM_OPL *OPL,int slot,int v)
1525 {
1526 OPL_CH *CH = &OPL->P_CH[slot/2];
1527 OPL_SLOT *SLOT = &CH->SLOT[slot&1];
1528
1529 SLOT->sl = sl_tab[ v>>4 ];
1530
1531 SLOT->rr = (v&0x0f)? 16 + ((v&0x0f)<<2) : 0;
1532 SLOT->eg_sh_rr = eg_rate_shift [SLOT->rr + SLOT->ksr ];
1533 SLOT->eg_sel_rr = eg_rate_select[SLOT->rr + SLOT->ksr ];
1534 }
1535
1536
1537 /* write a value v to register r on OPL chip */
OPLWriteReg(FM_OPL * OPL,int r,int v)1538 static void OPLWriteReg(FM_OPL *OPL, int r, int v)
1539 {
1540 OPL_CH *CH;
1541 int slot;
1542 int block_fnum;
1543
1544
1545 /* adjust bus to 8 bits */
1546 r &= 0xff;
1547 v &= 0xff;
1548
1549 /*if (LOG_CYM_FILE && (cymfile) && (r!=0) )
1550 {
1551 fputc( (unsigned char)r, cymfile );
1552 fputc( (unsigned char)v, cymfile );
1553 }*/
1554
1555
1556 switch(r&0xe0)
1557 {
1558 case 0x00: /* 00-1f:control */
1559 switch(r&0x1f)
1560 {
1561 case 0x01: /* waveform select enable */
1562 if(OPL->type&OPL_TYPE_WAVESEL)
1563 {
1564 OPL->wavesel = v&0x20;
1565 /* do not change the waveform previously selected */
1566 }
1567 break;
1568 case 0x02: /* Timer 1 */
1569 OPL->T[0] = (256-v)*4;
1570 break;
1571 case 0x03: /* Timer 2 */
1572 OPL->T[1] = (256-v)*16;
1573 break;
1574 case 0x04: /* IRQ clear / mask and Timer enable */
1575 if(v&0x80)
1576 { /* IRQ flag clear */
1577 OPL_STATUS_RESET(OPL,0x7f-0x08); /* don't reset BFRDY flag or we will have to call deltat module to set the flag */
1578 }
1579 else
1580 { /* set IRQ mask ,timer enable*/
1581 UINT8 st1 = v&1;
1582 UINT8 st2 = (v>>1)&1;
1583
1584 /* IRQRST,T1MSK,t2MSK,EOSMSK,BRMSK,x,ST2,ST1 */
1585 OPL_STATUS_RESET(OPL, v & (0x78-0x08) );
1586 OPL_STATUSMASK_SET(OPL, (~v) & 0x78 );
1587
1588 /* timer 2 */
1589 if(OPL->st[1] != st2)
1590 {
1591 //attotime period = st2 ? attotime_mul(OPL->TimerBase, OPL->T[1]) : attotime_zero;
1592 OPL->st[1] = st2;
1593 //if (OPL->timer_handler) (OPL->timer_handler)(OPL->TimerParam,1,period);
1594 }
1595 /* timer 1 */
1596 if(OPL->st[0] != st1)
1597 {
1598 //attotime period = st1 ? attotime_mul(OPL->TimerBase, OPL->T[0]) : attotime_zero;
1599 OPL->st[0] = st1;
1600 //if (OPL->timer_handler) (OPL->timer_handler)(OPL->TimerParam,0,period);
1601 }
1602 }
1603 break;
1604 #if BUILD_Y8950
1605 case 0x06: /* Key Board OUT */
1606 if(OPL->type&OPL_TYPE_KEYBOARD)
1607 {
1608 if(OPL->keyboardhandler_w)
1609 OPL->keyboardhandler_w(OPL->keyboard_param,v);
1610 #ifdef _DEBUG
1611 else
1612 logerror("Y8950: write unmapped KEYBOARD port\n");
1613 #endif
1614 }
1615 break;
1616 case 0x07: /* DELTA-T control 1 : START,REC,MEMDATA,REPT,SPOFF,x,x,RST */
1617 if(OPL->type&OPL_TYPE_ADPCM)
1618 YM_DELTAT_ADPCM_Write(OPL->deltat,r-0x07,v);
1619 break;
1620 #endif
1621 case 0x08: /* MODE,DELTA-T control 2 : CSM,NOTESEL,x,x,smpl,da/ad,64k,rom */
1622 OPL->mode = v;
1623 #if BUILD_Y8950
1624 if(OPL->type&OPL_TYPE_ADPCM)
1625 YM_DELTAT_ADPCM_Write(OPL->deltat,r-0x07,v&0x0f); /* mask 4 LSBs in register 08 for DELTA-T unit */
1626 #endif
1627 break;
1628
1629 #if BUILD_Y8950
1630 case 0x09: /* START ADD */
1631 case 0x0a:
1632 case 0x0b: /* STOP ADD */
1633 case 0x0c:
1634 case 0x0d: /* PRESCALE */
1635 case 0x0e:
1636 case 0x0f: /* ADPCM data write */
1637 case 0x10: /* DELTA-N */
1638 case 0x11: /* DELTA-N */
1639 case 0x12: /* ADPCM volume */
1640 if(OPL->type&OPL_TYPE_ADPCM)
1641 YM_DELTAT_ADPCM_Write(OPL->deltat,r-0x07,v);
1642 break;
1643
1644 case 0x15: /* DAC data high 8 bits (F7,F6...F2) */
1645 case 0x16: /* DAC data low 2 bits (F1, F0 in bits 7,6) */
1646 case 0x17: /* DAC data shift (S2,S1,S0 in bits 2,1,0) */
1647 #ifdef _DEBUG
1648 logerror("FMOPL.C: DAC data register written, but not implemented reg=%02x val=%02x\n",r,v);
1649 #endif
1650 break;
1651
1652 case 0x18: /* I/O CTRL (Direction) */
1653 if(OPL->type&OPL_TYPE_IO)
1654 OPL->portDirection = v&0x0f;
1655 break;
1656 case 0x19: /* I/O DATA */
1657 if(OPL->type&OPL_TYPE_IO)
1658 {
1659 OPL->portLatch = v;
1660 if(OPL->porthandler_w)
1661 OPL->porthandler_w(OPL->port_param,v&OPL->portDirection);
1662 }
1663 break;
1664 #endif
1665 default:
1666 #ifdef _DEBUG
1667 logerror("FMOPL.C: write to unknown register: %02x\n",r);
1668 #endif
1669 break;
1670 }
1671 break;
1672 case 0x20: /* am ON, vib ON, ksr, eg_type, mul */
1673 slot = slot_array[r&0x1f];
1674 if(slot < 0) return;
1675 set_mul(OPL,slot,v);
1676 break;
1677 case 0x40:
1678 slot = slot_array[r&0x1f];
1679 if(slot < 0) return;
1680 set_ksl_tl(OPL,slot,v);
1681 break;
1682 case 0x60:
1683 slot = slot_array[r&0x1f];
1684 if(slot < 0) return;
1685 set_ar_dr(OPL,slot,v);
1686 break;
1687 case 0x80:
1688 slot = slot_array[r&0x1f];
1689 if(slot < 0) return;
1690 set_sl_rr(OPL,slot,v);
1691 break;
1692 case 0xa0:
1693 if (r == 0xbd) /* am depth, vibrato depth, r,bd,sd,tom,tc,hh */
1694 {
1695 OPL->lfo_am_depth = v & 0x80;
1696 OPL->lfo_pm_depth_range = (v&0x40) ? 8 : 0;
1697
1698 OPL->rhythm = v&0x3f;
1699
1700 if(OPL->rhythm&0x20)
1701 {
1702 /* BD key on/off */
1703 if(v&0x10)
1704 {
1705 FM_KEYON (&OPL->P_CH[6].SLOT[SLOT1], 2);
1706 FM_KEYON (&OPL->P_CH[6].SLOT[SLOT2], 2);
1707 }
1708 else
1709 {
1710 FM_KEYOFF(&OPL->P_CH[6].SLOT[SLOT1],~2);
1711 FM_KEYOFF(&OPL->P_CH[6].SLOT[SLOT2],~2);
1712 }
1713 /* HH key on/off */
1714 if(v&0x01) FM_KEYON (&OPL->P_CH[7].SLOT[SLOT1], 2);
1715 else FM_KEYOFF(&OPL->P_CH[7].SLOT[SLOT1],~2);
1716 /* SD key on/off */
1717 if(v&0x08) FM_KEYON (&OPL->P_CH[7].SLOT[SLOT2], 2);
1718 else FM_KEYOFF(&OPL->P_CH[7].SLOT[SLOT2],~2);
1719 /* TOM key on/off */
1720 if(v&0x04) FM_KEYON (&OPL->P_CH[8].SLOT[SLOT1], 2);
1721 else FM_KEYOFF(&OPL->P_CH[8].SLOT[SLOT1],~2);
1722 /* TOP-CY key on/off */
1723 if(v&0x02) FM_KEYON (&OPL->P_CH[8].SLOT[SLOT2], 2);
1724 else FM_KEYOFF(&OPL->P_CH[8].SLOT[SLOT2],~2);
1725 }
1726 else
1727 {
1728 /* BD key off */
1729 FM_KEYOFF(&OPL->P_CH[6].SLOT[SLOT1],~2);
1730 FM_KEYOFF(&OPL->P_CH[6].SLOT[SLOT2],~2);
1731 /* HH key off */
1732 FM_KEYOFF(&OPL->P_CH[7].SLOT[SLOT1],~2);
1733 /* SD key off */
1734 FM_KEYOFF(&OPL->P_CH[7].SLOT[SLOT2],~2);
1735 /* TOM key off */
1736 FM_KEYOFF(&OPL->P_CH[8].SLOT[SLOT1],~2);
1737 /* TOP-CY off */
1738 FM_KEYOFF(&OPL->P_CH[8].SLOT[SLOT2],~2);
1739 }
1740 return;
1741 }
1742 /* keyon,block,fnum */
1743 if( (r&0x0f) > 8) return;
1744 CH = &OPL->P_CH[r&0x0f];
1745 if(!(r&0x10))
1746 { /* a0-a8 */
1747 block_fnum = (CH->block_fnum&0x1f00) | v;
1748 }
1749 else
1750 { /* b0-b8 */
1751 block_fnum = ((v&0x1f)<<8) | (CH->block_fnum&0xff);
1752
1753 if(v&0x20)
1754 {
1755 FM_KEYON (&CH->SLOT[SLOT1], 1);
1756 FM_KEYON (&CH->SLOT[SLOT2], 1);
1757 }
1758 else
1759 {
1760 FM_KEYOFF(&CH->SLOT[SLOT1],~1);
1761 FM_KEYOFF(&CH->SLOT[SLOT2],~1);
1762 }
1763 }
1764 /* update */
1765 if(CH->block_fnum != block_fnum)
1766 {
1767 UINT8 block = block_fnum >> 10;
1768
1769 CH->block_fnum = block_fnum;
1770
1771 CH->ksl_base = ksl_tab[block_fnum>>6];
1772 CH->fc = OPL->fn_tab[block_fnum&0x03ff] >> (7-block);
1773
1774 /* BLK 2,1,0 bits -> bits 3,2,1 of kcode */
1775 CH->kcode = (CH->block_fnum&0x1c00)>>9;
1776
1777 /* the info below is actually opposite to what is stated in the Manuals (verifed on real YM3812) */
1778 /* if notesel == 0 -> lsb of kcode is bit 10 (MSB) of fnum */
1779 /* if notesel == 1 -> lsb of kcode is bit 9 (MSB-1) of fnum */
1780 if (OPL->mode&0x40)
1781 CH->kcode |= (CH->block_fnum&0x100)>>8; /* notesel == 1 */
1782 else
1783 CH->kcode |= (CH->block_fnum&0x200)>>9; /* notesel == 0 */
1784
1785 /* refresh Total Level in both SLOTs of this channel */
1786 CH->SLOT[SLOT1].TLL = CH->SLOT[SLOT1].TL + (CH->ksl_base>>CH->SLOT[SLOT1].ksl);
1787 CH->SLOT[SLOT2].TLL = CH->SLOT[SLOT2].TL + (CH->ksl_base>>CH->SLOT[SLOT2].ksl);
1788
1789 /* refresh frequency counter in both SLOTs of this channel */
1790 CALC_FCSLOT(CH,&CH->SLOT[SLOT1]);
1791 CALC_FCSLOT(CH,&CH->SLOT[SLOT2]);
1792 }
1793 break;
1794 case 0xc0:
1795 /* FB,C */
1796 if( (r&0x0f) > 8) return;
1797 CH = &OPL->P_CH[r&0x0f];
1798 CH->SLOT[SLOT1].FB = (v>>1)&7 ? ((v>>1)&7) + 7 : 0;
1799 CH->SLOT[SLOT1].CON = v&1;
1800 CH->SLOT[SLOT1].connect1 = CH->SLOT[SLOT1].CON ? &OPL->output[0] : &OPL->phase_modulation;
1801 break;
1802 case 0xe0: /* waveform select */
1803 /* simply ignore write to the waveform select register if selecting not enabled in test register */
1804 if(OPL->wavesel)
1805 {
1806 slot = slot_array[r&0x1f];
1807 if(slot < 0) return;
1808 CH = &OPL->P_CH[slot/2];
1809
1810 CH->SLOT[slot&1].wavetable = (v&0x03)*SIN_LEN;
1811 }
1812 break;
1813 }
1814 }
1815
1816 /*static TIMER_CALLBACK( cymfile_callback )
1817 {
1818 if (cymfile)
1819 {
1820 fputc( (unsigned char)0, cymfile );
1821 }
1822 }*/
1823
1824 /* lock/unlock for common table */
OPL_LockTable(void)1825 static int OPL_LockTable(void)
1826 {
1827 num_lock++;
1828 if(num_lock>1) return 0;
1829
1830 /* first time */
1831
1832 /* allocate total level table (128kb space) */
1833 if( !init_tables() )
1834 {
1835 num_lock--;
1836 return -1;
1837 }
1838
1839 /*if (LOG_CYM_FILE)
1840 {
1841 cymfile = fopen("3812_.cym","wb");
1842 if (cymfile)
1843 timer_pulse ( device->machine, ATTOTIME_IN_HZ(110), NULL, 0, cymfile_callback); //110 Hz pulse timer
1844 else
1845 logerror("Could not create file 3812_.cym\n");
1846 }*/
1847
1848 return 0;
1849 }
1850
OPL_UnLockTable(void)1851 static void OPL_UnLockTable(void)
1852 {
1853 if(num_lock) num_lock--;
1854 if(num_lock) return;
1855
1856 /* last time */
1857
1858 OPLCloseTable();
1859
1860 /*if (cymfile)
1861 fclose (cymfile);
1862 cymfile = NULL;*/
1863 }
1864
OPLResetChip(FM_OPL * OPL)1865 static void OPLResetChip(FM_OPL *OPL)
1866 {
1867 int c,s;
1868 int i;
1869
1870 OPL->eg_timer = 0;
1871 OPL->eg_cnt = 0;
1872
1873 OPL->noise_rng = 1; /* noise shift register */
1874 OPL->mode = 0; /* normal mode */
1875 OPL_STATUS_RESET(OPL,0x7f);
1876
1877 /* reset with register write */
1878 OPLWriteReg(OPL,0x01,0); /* wavesel disable */
1879 OPLWriteReg(OPL,0x02,0); /* Timer1 */
1880 OPLWriteReg(OPL,0x03,0); /* Timer2 */
1881 OPLWriteReg(OPL,0x04,0); /* IRQ mask clear */
1882 for(i = 0xff ; i >= 0x20 ; i-- ) OPLWriteReg(OPL,i,0);
1883
1884 /* reset operator parameters */
1885 for( c = 0 ; c < 9 ; c++ )
1886 {
1887 OPL_CH *CH = &OPL->P_CH[c];
1888 for(s = 0 ; s < 2 ; s++ )
1889 {
1890 /* wave table */
1891 CH->SLOT[s].wavetable = 0;
1892 CH->SLOT[s].state = EG_OFF;
1893 CH->SLOT[s].volume = MAX_ATT_INDEX;
1894 }
1895 }
1896 #if BUILD_Y8950
1897 if(OPL->type&OPL_TYPE_ADPCM)
1898 {
1899 YM_DELTAT *DELTAT = OPL->deltat;
1900
1901 DELTAT->freqbase = OPL->freqbase;
1902 DELTAT->output_pointer = &OPL->output_deltat[0];
1903 DELTAT->portshift = 5;
1904 DELTAT->output_range = 1<<23;
1905 YM_DELTAT_ADPCM_Reset(DELTAT,0,YM_DELTAT_EMULATION_MODE_NORMAL);
1906 }
1907 #endif
1908 }
1909
1910
1911 #if 0
1912 //static STATE_POSTLOAD( OPL_postload )
1913 static void OPL_postload(void* param)
1914 {
1915 FM_OPL *OPL = (FM_OPL *)param;
1916 int slot, ch;
1917
1918 for( ch=0 ; ch < 9 ; ch++ )
1919 {
1920 OPL_CH *CH = &OPL->P_CH[ch];
1921
1922 /* Look up key scale level */
1923 UINT32 block_fnum = CH->block_fnum;
1924 CH->ksl_base = ksl_tab[block_fnum >> 6];
1925 CH->fc = OPL->fn_tab[block_fnum & 0x03ff] >> (7 - (block_fnum >> 10));
1926
1927 for( slot=0 ; slot < 2 ; slot++ )
1928 {
1929 OPL_SLOT *SLOT = &CH->SLOT[slot];
1930
1931 /* Calculate key scale rate */
1932 SLOT->ksr = CH->kcode >> SLOT->KSR;
1933
1934 /* Calculate attack, decay and release rates */
1935 if ((SLOT->ar + SLOT->ksr) < 16+62)
1936 {
1937 SLOT->eg_sh_ar = eg_rate_shift [SLOT->ar + SLOT->ksr ];
1938 SLOT->eg_sel_ar = eg_rate_select[SLOT->ar + SLOT->ksr ];
1939 }
1940 else
1941 {
1942 SLOT->eg_sh_ar = 0;
1943 SLOT->eg_sel_ar = 13*RATE_STEPS;
1944 }
1945 SLOT->eg_sh_dr = eg_rate_shift [SLOT->dr + SLOT->ksr ];
1946 SLOT->eg_sel_dr = eg_rate_select[SLOT->dr + SLOT->ksr ];
1947 SLOT->eg_sh_rr = eg_rate_shift [SLOT->rr + SLOT->ksr ];
1948 SLOT->eg_sel_rr = eg_rate_select[SLOT->rr + SLOT->ksr ];
1949
1950 /* Calculate phase increment */
1951 SLOT->Incr = CH->fc * SLOT->mul;
1952
1953 /* Total level */
1954 SLOT->TLL = SLOT->TL + (CH->ksl_base >> SLOT->ksl);
1955
1956 /* Connect output */
1957 SLOT->connect1 = SLOT->CON ? &OPL->output[0] : &OPL->phase_modulation;
1958 }
1959 }
1960 #if BUILD_Y8950
1961 if ( (OPL->type & OPL_TYPE_ADPCM) && (OPL->deltat) )
1962 {
1963 // We really should call the postlod function for the YM_DELTAT, but it's hard without registers
1964 // (see the way the YM2610 does it)
1965 //YM_DELTAT_postload(OPL->deltat, REGS);
1966 }
1967 #endif
1968 }
1969
1970
1971 static void OPLsave_state_channel(OPL_CH *CH)
1972 {
1973 int slot, ch;
1974
1975 for( ch=0 ; ch < 9 ; ch++, CH++ )
1976 {
1977 // channel
1978 state_save_register_device_item(device, ch, CH->block_fnum);
1979 state_save_register_device_item(device, ch, CH->kcode);
1980 // slots
1981 for( slot=0 ; slot < 2 ; slot++ )
1982 {
1983 OPL_SLOT *SLOT = &CH->SLOT[slot];
1984
1985 state_save_register_device_item(device, ch * 2 + slot, SLOT->ar);
1986 state_save_register_device_item(device, ch * 2 + slot, SLOT->dr);
1987 state_save_register_device_item(device, ch * 2 + slot, SLOT->rr);
1988 state_save_register_device_item(device, ch * 2 + slot, SLOT->KSR);
1989 state_save_register_device_item(device, ch * 2 + slot, SLOT->ksl);
1990 state_save_register_device_item(device, ch * 2 + slot, SLOT->mul);
1991
1992 state_save_register_device_item(device, ch * 2 + slot, SLOT->Cnt);
1993 state_save_register_device_item(device, ch * 2 + slot, SLOT->FB);
1994 state_save_register_device_item_array(device, ch * 2 + slot, SLOT->op1_out);
1995 state_save_register_device_item(device, ch * 2 + slot, SLOT->CON);
1996
1997 state_save_register_device_item(device, ch * 2 + slot, SLOT->eg_type);
1998 state_save_register_device_item(device, ch * 2 + slot, SLOT->state);
1999 state_save_register_device_item(device, ch * 2 + slot, SLOT->TL);
2000 state_save_register_device_item(device, ch * 2 + slot, SLOT->volume);
2001 state_save_register_device_item(device, ch * 2 + slot, SLOT->sl);
2002 state_save_register_device_item(device, ch * 2 + slot, SLOT->key);
2003
2004 state_save_register_device_item(device, ch * 2 + slot, SLOT->AMmask);
2005 state_save_register_device_item(device, ch * 2 + slot, SLOT->vib);
2006
2007 state_save_register_device_item(device, ch * 2 + slot, SLOT->wavetable);
2008 }
2009 }
2010 }
2011 #endif
2012
2013
2014 /* Register savestate for a virtual YM3812/YM3526/Y8950 */
2015
2016 /*static void OPL_save_state(FM_OPL *OPL)
2017 {
2018 OPLsave_state_channel(device, OPL->P_CH);
2019
2020 state_save_register_device_item(device, 0, OPL->eg_cnt);
2021 state_save_register_device_item(device, 0, OPL->eg_timer);
2022
2023 state_save_register_device_item(device, 0, OPL->rhythm);
2024
2025 state_save_register_device_item(device, 0, OPL->lfo_am_depth);
2026 state_save_register_device_item(device, 0, OPL->lfo_pm_depth_range);
2027 state_save_register_device_item(device, 0, OPL->lfo_am_cnt);
2028 state_save_register_device_item(device, 0, OPL->lfo_pm_cnt);
2029
2030 state_save_register_device_item(device, 0, OPL->noise_rng);
2031 state_save_register_device_item(device, 0, OPL->noise_p);
2032
2033 if( OPL->type & OPL_TYPE_WAVESEL )
2034 {
2035 state_save_register_device_item(device, 0, OPL->wavesel);
2036 }
2037
2038 state_save_register_device_item_array(device, 0, OPL->T);
2039 state_save_register_device_item_array(device, 0, OPL->st);
2040
2041 #if BUILD_Y8950
2042 if ( (OPL->type & OPL_TYPE_ADPCM) && (OPL->deltat) )
2043 {
2044 YM_DELTAT_savestate(device, OPL->deltat);
2045 }
2046
2047 if ( OPL->type & OPL_TYPE_IO )
2048 {
2049 state_save_register_device_item(device, 0, OPL->portDirection);
2050 state_save_register_device_item(device, 0, OPL->portLatch);
2051 }
2052 #endif
2053
2054 state_save_register_device_item(device, 0, OPL->address);
2055 state_save_register_device_item(device, 0, OPL->status);
2056 state_save_register_device_item(device, 0, OPL->statusmask);
2057 state_save_register_device_item(device, 0, OPL->mode);
2058
2059 state_save_register_postload(device->machine, OPL_postload, OPL);
2060 }*/
2061
2062
2063 /* Create one of virtual YM3812/YM3526/Y8950 */
2064 /* 'clock' is chip clock in Hz */
2065 /* 'rate' is sampling rate */
OPLCreate(UINT32 clock,UINT32 rate,int type)2066 static FM_OPL *OPLCreate(UINT32 clock, UINT32 rate, int type)
2067 {
2068 char *ptr;
2069 FM_OPL *OPL;
2070 int state_size;
2071
2072 if (OPL_LockTable() == -1) return NULL;
2073
2074 /* calculate OPL state size */
2075 state_size = sizeof(FM_OPL);
2076
2077 #if BUILD_Y8950
2078 if (type&OPL_TYPE_ADPCM) state_size+= sizeof(YM_DELTAT);
2079 #endif
2080
2081 /* allocate memory block */
2082 ptr = (char *)malloc(state_size);
2083
2084 if (ptr==NULL)
2085 return NULL;
2086
2087 /* clear */
2088 memset(ptr,0,state_size);
2089
2090 OPL = (FM_OPL *)ptr;
2091
2092 ptr += sizeof(FM_OPL);
2093
2094 #if BUILD_Y8950
2095 if (type&OPL_TYPE_ADPCM)
2096 {
2097 OPL->deltat = (YM_DELTAT *)ptr;
2098 }
2099 ptr += sizeof(YM_DELTAT);
2100 #endif
2101
2102 OPL->type = type;
2103 OPL->clock = clock;
2104 OPL->rate = rate;
2105
2106 /* init global tables */
2107 OPL_initalize(OPL);
2108
2109 return OPL;
2110 }
2111
2112 /* Destroy one of virtual YM3812 */
OPLDestroy(FM_OPL * OPL)2113 static void OPLDestroy(FM_OPL *OPL)
2114 {
2115 OPL_UnLockTable();
2116 free(OPL);
2117 }
2118
2119 /* Optional handlers */
2120
OPLSetTimerHandler(FM_OPL * OPL,OPL_TIMERHANDLER timer_handler,void * param)2121 static void OPLSetTimerHandler(FM_OPL *OPL,OPL_TIMERHANDLER timer_handler,void *param)
2122 {
2123 OPL->timer_handler = timer_handler;
2124 OPL->TimerParam = param;
2125 }
OPLSetIRQHandler(FM_OPL * OPL,OPL_IRQHANDLER IRQHandler,void * param)2126 static void OPLSetIRQHandler(FM_OPL *OPL,OPL_IRQHANDLER IRQHandler,void *param)
2127 {
2128 OPL->IRQHandler = IRQHandler;
2129 OPL->IRQParam = param;
2130 }
OPLSetUpdateHandler(FM_OPL * OPL,OPL_UPDATEHANDLER UpdateHandler,void * param)2131 static void OPLSetUpdateHandler(FM_OPL *OPL,OPL_UPDATEHANDLER UpdateHandler,void *param)
2132 {
2133 OPL->UpdateHandler = UpdateHandler;
2134 OPL->UpdateParam = param;
2135 }
2136
OPLWrite(FM_OPL * OPL,int a,int v)2137 static int OPLWrite(FM_OPL *OPL,int a,int v)
2138 {
2139 if( !(a&1) )
2140 { /* address port */
2141 OPL->address = v & 0xff;
2142 }
2143 else
2144 { /* data port */
2145 if(OPL->UpdateHandler) OPL->UpdateHandler(OPL->UpdateParam/*,0*/);
2146 OPLWriteReg(OPL,OPL->address,v);
2147 }
2148 return OPL->status>>7;
2149 }
2150
OPLRead(FM_OPL * OPL,int a)2151 static unsigned char OPLRead(FM_OPL *OPL,int a)
2152 {
2153 if( !(a&1) )
2154 {
2155 /* status port */
2156
2157 #if BUILD_Y8950
2158
2159 if(OPL->type&OPL_TYPE_ADPCM) /* Y8950 */
2160 {
2161 return (OPL->status & (OPL->statusmask|0x80)) | (OPL->deltat->PCM_BSY&1);
2162 }
2163
2164 #endif
2165
2166 /* OPL and OPL2 */
2167 return OPL->status & (OPL->statusmask|0x80);
2168 }
2169
2170 #if BUILD_Y8950
2171 /* data port */
2172 switch(OPL->address)
2173 {
2174 case 0x05: /* KeyBoard IN */
2175 if(OPL->type&OPL_TYPE_KEYBOARD)
2176 {
2177 if(OPL->keyboardhandler_r)
2178 return OPL->keyboardhandler_r(OPL->keyboard_param);
2179 #ifdef _DEBUG
2180 else
2181 logerror("Y8950: read unmapped KEYBOARD port\n");
2182 #endif
2183 }
2184 return 0;
2185
2186 case 0x0f: /* ADPCM-DATA */
2187 if(OPL->type&OPL_TYPE_ADPCM)
2188 {
2189 UINT8 val;
2190
2191 val = YM_DELTAT_ADPCM_Read(OPL->deltat);
2192 /*logerror("Y8950: read ADPCM value read=%02x\n",val);*/
2193 return val;
2194 }
2195 return 0;
2196
2197 case 0x19: /* I/O DATA */
2198 if(OPL->type&OPL_TYPE_IO)
2199 {
2200 if(OPL->porthandler_r)
2201 return OPL->porthandler_r(OPL->port_param);
2202 #ifdef _DEBUG
2203 else
2204 logerror("Y8950:read unmapped I/O port\n");
2205 #endif
2206 }
2207 return 0;
2208 case 0x1a: /* PCM-DATA */
2209 if(OPL->type&OPL_TYPE_ADPCM)
2210 {
2211 #ifdef _DEBUG
2212 logerror("Y8950 A/D conversion is accessed but not implemented !\n");
2213 #endif
2214 return 0x80; /* 2's complement PCM data - result from A/D conversion */
2215 }
2216 return 0;
2217 }
2218 #endif
2219
2220 return 0xff;
2221 }
2222
2223 /* CSM Key Controll */
CSMKeyControll(OPL_CH * CH)2224 INLINE void CSMKeyControll(OPL_CH *CH)
2225 {
2226 FM_KEYON (&CH->SLOT[SLOT1], 4);
2227 FM_KEYON (&CH->SLOT[SLOT2], 4);
2228
2229 /* The key off should happen exactly one sample later - not implemented correctly yet */
2230
2231 FM_KEYOFF(&CH->SLOT[SLOT1], ~4);
2232 FM_KEYOFF(&CH->SLOT[SLOT2], ~4);
2233 }
2234
2235
OPLTimerOver(FM_OPL * OPL,int c)2236 static int OPLTimerOver(FM_OPL *OPL,int c)
2237 {
2238 if( c )
2239 { /* Timer B */
2240 OPL_STATUS_SET(OPL,0x20);
2241 }
2242 else
2243 { /* Timer A */
2244 OPL_STATUS_SET(OPL,0x40);
2245 /* CSM mode key,TL controll */
2246 if( OPL->mode & 0x80 )
2247 { /* CSM mode total level latch and auto key on */
2248 int ch;
2249 if(OPL->UpdateHandler) OPL->UpdateHandler(OPL->UpdateParam/*,0*/);
2250 for(ch=0; ch<9; ch++)
2251 CSMKeyControll( &OPL->P_CH[ch] );
2252 }
2253 }
2254 /* reload timer */
2255 //if (OPL->timer_handler) (OPL->timer_handler)(OPL->TimerParam,c,attotime_mul(OPL->TimerBase, OPL->T[c]));
2256 return OPL->status>>7;
2257 }
2258
2259
2260 #define MAX_OPL_CHIPS 2
2261
2262
2263 #if (BUILD_YM3812)
2264
ym3812_init(UINT32 clock,UINT32 rate)2265 void * ym3812_init(UINT32 clock, UINT32 rate)
2266 {
2267 /* emulator create */
2268 FM_OPL *YM3812 = OPLCreate(clock,rate,OPL_TYPE_YM3812);
2269 if (YM3812)
2270 {
2271 //OPL_save_state(YM3812);
2272 ym3812_reset_chip(YM3812);
2273 }
2274 return YM3812;
2275 }
2276
ym3812_shutdown(void * chip)2277 void ym3812_shutdown(void *chip)
2278 {
2279 FM_OPL *YM3812 = (FM_OPL *)chip;
2280 /* emulator shutdown */
2281 OPLDestroy(YM3812);
2282 }
ym3812_reset_chip(void * chip)2283 void ym3812_reset_chip(void *chip)
2284 {
2285 FM_OPL *YM3812 = (FM_OPL *)chip;
2286 OPLResetChip(YM3812);
2287 }
2288
ym3812_write(void * chip,int a,int v)2289 int ym3812_write(void *chip, int a, int v)
2290 {
2291 FM_OPL *YM3812 = (FM_OPL *)chip;
2292 return OPLWrite(YM3812, a, v);
2293 }
2294
ym3812_read(void * chip,int a)2295 unsigned char ym3812_read(void *chip, int a)
2296 {
2297 FM_OPL *YM3812 = (FM_OPL *)chip;
2298 /* YM3812 always returns bit2 and bit1 in HIGH state */
2299 return OPLRead(YM3812, a) | 0x06 ;
2300 }
ym3812_timer_over(void * chip,int c)2301 int ym3812_timer_over(void *chip, int c)
2302 {
2303 FM_OPL *YM3812 = (FM_OPL *)chip;
2304 return OPLTimerOver(YM3812, c);
2305 }
2306
ym3812_set_timer_handler(void * chip,OPL_TIMERHANDLER timer_handler,void * param)2307 void ym3812_set_timer_handler(void *chip, OPL_TIMERHANDLER timer_handler, void *param)
2308 {
2309 FM_OPL *YM3812 = (FM_OPL *)chip;
2310 OPLSetTimerHandler(YM3812, timer_handler, param);
2311 }
ym3812_set_irq_handler(void * chip,OPL_IRQHANDLER IRQHandler,void * param)2312 void ym3812_set_irq_handler(void *chip,OPL_IRQHANDLER IRQHandler,void *param)
2313 {
2314 FM_OPL *YM3812 = (FM_OPL *)chip;
2315 OPLSetIRQHandler(YM3812, IRQHandler, param);
2316 }
ym3812_set_update_handler(void * chip,OPL_UPDATEHANDLER UpdateHandler,void * param)2317 void ym3812_set_update_handler(void *chip,OPL_UPDATEHANDLER UpdateHandler,void *param)
2318 {
2319 FM_OPL *YM3812 = (FM_OPL *)chip;
2320 OPLSetUpdateHandler(YM3812, UpdateHandler, param);
2321 }
2322
2323
2324 /*
2325 ** Generate samples for one of the YM3812's
2326 **
2327 ** 'which' is the virtual YM3812 number
2328 ** '*buffer' is the output buffer pointer
2329 ** 'length' is the number of samples that should be generated
2330 */
ym3812_update_one(void * chip,OPLSAMPLE ** buffer,int length)2331 void ym3812_update_one(void *chip, OPLSAMPLE **buffer, int length)
2332 {
2333 FM_OPL *OPL = (FM_OPL *)chip;
2334 UINT8 rhythm = OPL->rhythm&0x20;
2335 OPLSAMPLE *bufL = buffer[0];
2336 OPLSAMPLE *bufR = buffer[1];
2337 int i;
2338
2339 if (! length)
2340 {
2341 refresh_eg(OPL);
2342 return;
2343 }
2344
2345 for( i=0; i < length ; i++ )
2346 {
2347 int lt;
2348
2349 OPL->output[0] = 0;
2350
2351 advance_lfo(OPL);
2352
2353 /* FM part */
2354 OPL_CALC_CH(OPL, &OPL->P_CH[0]);
2355 OPL_CALC_CH(OPL, &OPL->P_CH[1]);
2356 OPL_CALC_CH(OPL, &OPL->P_CH[2]);
2357 OPL_CALC_CH(OPL, &OPL->P_CH[3]);
2358 OPL_CALC_CH(OPL, &OPL->P_CH[4]);
2359 OPL_CALC_CH(OPL, &OPL->P_CH[5]);
2360
2361 if(!rhythm)
2362 {
2363 OPL_CALC_CH(OPL, &OPL->P_CH[6]);
2364 OPL_CALC_CH(OPL, &OPL->P_CH[7]);
2365 OPL_CALC_CH(OPL, &OPL->P_CH[8]);
2366 }
2367 else /* Rhythm part */
2368 {
2369 OPL_CALC_RH(OPL, &OPL->P_CH[0], (OPL->noise_rng>>0)&1 );
2370 }
2371
2372 lt = OPL->output[0];
2373
2374 lt >>= FINAL_SH;
2375
2376 /* limit check */
2377 //lt = limit( lt , MAXOUT, MINOUT );
2378
2379 #ifdef SAVE_SAMPLE
2380 if (which==0)
2381 {
2382 SAVE_ALL_CHANNELS
2383 }
2384 #endif
2385
2386 /* store to sound buffer */
2387 bufL[i] = lt;
2388 bufR[i] = lt;
2389
2390 advance(OPL);
2391 }
2392
2393 }
2394 #endif /* BUILD_YM3812 */
2395
2396
2397
2398 #if (BUILD_YM3526)
2399
ym3526_init(UINT32 clock,UINT32 rate)2400 void *ym3526_init(UINT32 clock, UINT32 rate)
2401 {
2402 /* emulator create */
2403 FM_OPL *YM3526 = OPLCreate(clock,rate,OPL_TYPE_YM3526);
2404 if (YM3526)
2405 {
2406 //OPL_save_state(YM3526);
2407 ym3526_reset_chip(YM3526);
2408 }
2409 return YM3526;
2410 }
2411
ym3526_shutdown(void * chip)2412 void ym3526_shutdown(void *chip)
2413 {
2414 FM_OPL *YM3526 = (FM_OPL *)chip;
2415 /* emulator shutdown */
2416 OPLDestroy(YM3526);
2417 }
ym3526_reset_chip(void * chip)2418 void ym3526_reset_chip(void *chip)
2419 {
2420 FM_OPL *YM3526 = (FM_OPL *)chip;
2421 OPLResetChip(YM3526);
2422 }
2423
ym3526_write(void * chip,int a,int v)2424 int ym3526_write(void *chip, int a, int v)
2425 {
2426 FM_OPL *YM3526 = (FM_OPL *)chip;
2427 return OPLWrite(YM3526, a, v);
2428 }
2429
ym3526_read(void * chip,int a)2430 unsigned char ym3526_read(void *chip, int a)
2431 {
2432 FM_OPL *YM3526 = (FM_OPL *)chip;
2433 /* YM3526 always returns bit2 and bit1 in HIGH state */
2434 return OPLRead(YM3526, a) | 0x06 ;
2435 }
ym3526_timer_over(void * chip,int c)2436 int ym3526_timer_over(void *chip, int c)
2437 {
2438 FM_OPL *YM3526 = (FM_OPL *)chip;
2439 return OPLTimerOver(YM3526, c);
2440 }
2441
ym3526_set_timer_handler(void * chip,OPL_TIMERHANDLER timer_handler,void * param)2442 void ym3526_set_timer_handler(void *chip, OPL_TIMERHANDLER timer_handler, void *param)
2443 {
2444 FM_OPL *YM3526 = (FM_OPL *)chip;
2445 OPLSetTimerHandler(YM3526, timer_handler, param);
2446 }
ym3526_set_irq_handler(void * chip,OPL_IRQHANDLER IRQHandler,void * param)2447 void ym3526_set_irq_handler(void *chip,OPL_IRQHANDLER IRQHandler,void *param)
2448 {
2449 FM_OPL *YM3526 = (FM_OPL *)chip;
2450 OPLSetIRQHandler(YM3526, IRQHandler, param);
2451 }
ym3526_set_update_handler(void * chip,OPL_UPDATEHANDLER UpdateHandler,void * param)2452 void ym3526_set_update_handler(void *chip,OPL_UPDATEHANDLER UpdateHandler,void *param)
2453 {
2454 FM_OPL *YM3526 = (FM_OPL *)chip;
2455 OPLSetUpdateHandler(YM3526, UpdateHandler, param);
2456 }
2457
2458
2459 /*
2460 ** Generate samples for one of the YM3526's
2461 **
2462 ** 'which' is the virtual YM3526 number
2463 ** '*buffer' is the output buffer pointer
2464 ** 'length' is the number of samples that should be generated
2465 */
ym3526_update_one(void * chip,OPLSAMPLE ** buffer,int length)2466 void ym3526_update_one(void *chip, OPLSAMPLE **buffer, int length)
2467 {
2468 FM_OPL *OPL = (FM_OPL *)chip;
2469 UINT8 rhythm = OPL->rhythm&0x20;
2470 OPLSAMPLE *bufL = buffer[0];
2471 OPLSAMPLE *bufR = buffer[1];
2472 int i;
2473
2474 for( i=0; i < length ; i++ )
2475 {
2476 int lt;
2477
2478 OPL->output[0] = 0;
2479
2480 advance_lfo(OPL);
2481
2482 /* FM part */
2483 OPL_CALC_CH(OPL, &OPL->P_CH[0]);
2484 OPL_CALC_CH(OPL, &OPL->P_CH[1]);
2485 OPL_CALC_CH(OPL, &OPL->P_CH[2]);
2486 OPL_CALC_CH(OPL, &OPL->P_CH[3]);
2487 OPL_CALC_CH(OPL, &OPL->P_CH[4]);
2488 OPL_CALC_CH(OPL, &OPL->P_CH[5]);
2489
2490 if(!rhythm)
2491 {
2492 OPL_CALC_CH(OPL, &OPL->P_CH[6]);
2493 OPL_CALC_CH(OPL, &OPL->P_CH[7]);
2494 OPL_CALC_CH(OPL, &OPL->P_CH[8]);
2495 }
2496 else /* Rhythm part */
2497 {
2498 OPL_CALC_RH(OPL, &OPL->P_CH[0], (OPL->noise_rng>>0)&1 );
2499 }
2500
2501 lt = OPL->output[0];
2502
2503 lt >>= FINAL_SH;
2504
2505 /* limit check */
2506 //lt = limit( lt , MAXOUT, MINOUT );
2507
2508 #ifdef SAVE_SAMPLE
2509 if (which==0)
2510 {
2511 SAVE_ALL_CHANNELS
2512 }
2513 #endif
2514
2515 /* store to sound buffer */
2516 bufL[i] = lt;
2517 bufR[i] = lt;
2518
2519 advance(OPL);
2520 }
2521
2522 }
2523 #endif /* BUILD_YM3526 */
2524
2525
2526
2527
2528 #if BUILD_Y8950
2529
Y8950_deltat_status_set(void * chip,UINT8 changebits)2530 static void Y8950_deltat_status_set(void *chip, UINT8 changebits)
2531 {
2532 FM_OPL *Y8950 = (FM_OPL *)chip;
2533 OPL_STATUS_SET(Y8950, changebits);
2534 }
Y8950_deltat_status_reset(void * chip,UINT8 changebits)2535 static void Y8950_deltat_status_reset(void *chip, UINT8 changebits)
2536 {
2537 FM_OPL *Y8950 = (FM_OPL *)chip;
2538 OPL_STATUS_RESET(Y8950, changebits);
2539 }
2540
y8950_init(UINT32 clock,UINT32 rate)2541 void *y8950_init(UINT32 clock, UINT32 rate)
2542 {
2543 /* emulator create */
2544 FM_OPL *Y8950 = OPLCreate(clock,rate,OPL_TYPE_Y8950);
2545 if (Y8950)
2546 {
2547 Y8950->deltat->memory = NULL;
2548 Y8950->deltat->memory_size = 0x00;
2549 Y8950->deltat->memory_mask = 0x00;
2550
2551 Y8950->deltat->status_set_handler = Y8950_deltat_status_set;
2552 Y8950->deltat->status_reset_handler = Y8950_deltat_status_reset;
2553 Y8950->deltat->status_change_which_chip = Y8950;
2554 Y8950->deltat->status_change_EOS_bit = 0x10; /* status flag: set bit4 on End Of Sample */
2555 Y8950->deltat->status_change_BRDY_bit = 0x08; /* status flag: set bit3 on BRDY (End Of: ADPCM analysis/synthesis, memory reading/writing) */
2556
2557 /*Y8950->deltat->write_time = 10.0 / clock;*/ /* a single byte write takes 10 cycles of main clock */
2558 /*Y8950->deltat->read_time = 8.0 / clock;*/ /* a single byte read takes 8 cycles of main clock */
2559 /* reset */
2560 //OPL_save_state(Y8950);
2561 y8950_reset_chip(Y8950);
2562 }
2563
2564 return Y8950;
2565 }
2566
y8950_shutdown(void * chip)2567 void y8950_shutdown(void *chip)
2568 {
2569 FM_OPL *Y8950 = (FM_OPL *)chip;
2570
2571 free(Y8950->deltat->memory); Y8950->deltat->memory = NULL;
2572
2573 /* emulator shutdown */
2574 OPLDestroy(Y8950);
2575 }
y8950_reset_chip(void * chip)2576 void y8950_reset_chip(void *chip)
2577 {
2578 FM_OPL *Y8950 = (FM_OPL *)chip;
2579 OPLResetChip(Y8950);
2580 }
2581
y8950_write(void * chip,int a,int v)2582 int y8950_write(void *chip, int a, int v)
2583 {
2584 FM_OPL *Y8950 = (FM_OPL *)chip;
2585 return OPLWrite(Y8950, a, v);
2586 }
2587
y8950_read(void * chip,int a)2588 unsigned char y8950_read(void *chip, int a)
2589 {
2590 FM_OPL *Y8950 = (FM_OPL *)chip;
2591 return OPLRead(Y8950, a);
2592 }
y8950_timer_over(void * chip,int c)2593 int y8950_timer_over(void *chip, int c)
2594 {
2595 FM_OPL *Y8950 = (FM_OPL *)chip;
2596 return OPLTimerOver(Y8950, c);
2597 }
2598
y8950_set_timer_handler(void * chip,OPL_TIMERHANDLER timer_handler,void * param)2599 void y8950_set_timer_handler(void *chip, OPL_TIMERHANDLER timer_handler, void *param)
2600 {
2601 FM_OPL *Y8950 = (FM_OPL *)chip;
2602 OPLSetTimerHandler(Y8950, timer_handler, param);
2603 }
y8950_set_irq_handler(void * chip,OPL_IRQHANDLER IRQHandler,void * param)2604 void y8950_set_irq_handler(void *chip,OPL_IRQHANDLER IRQHandler,void *param)
2605 {
2606 FM_OPL *Y8950 = (FM_OPL *)chip;
2607 OPLSetIRQHandler(Y8950, IRQHandler, param);
2608 }
y8950_set_update_handler(void * chip,OPL_UPDATEHANDLER UpdateHandler,void * param)2609 void y8950_set_update_handler(void *chip,OPL_UPDATEHANDLER UpdateHandler,void *param)
2610 {
2611 FM_OPL *Y8950 = (FM_OPL *)chip;
2612 OPLSetUpdateHandler(Y8950, UpdateHandler, param);
2613 }
2614
y8950_set_delta_t_memory(void * chip,void * deltat_mem_ptr,int deltat_mem_size)2615 void y8950_set_delta_t_memory(void *chip, void * deltat_mem_ptr, int deltat_mem_size )
2616 {
2617 FM_OPL *OPL = (FM_OPL *)chip;
2618 OPL->deltat->memory = (UINT8 *)(deltat_mem_ptr);
2619 OPL->deltat->memory_size = deltat_mem_size;
2620 }
2621
y8950_write_pcmrom(void * chip,offs_t ROMSize,offs_t DataStart,offs_t DataLength,const UINT8 * ROMData)2622 void y8950_write_pcmrom(void *chip, offs_t ROMSize, offs_t DataStart,
2623 offs_t DataLength, const UINT8* ROMData)
2624 {
2625 FM_OPL *Y8950 = (FM_OPL *)chip;
2626
2627 if (Y8950->deltat->memory_size != ROMSize)
2628 {
2629 Y8950->deltat->memory = (UINT8*)realloc(Y8950->deltat->memory, ROMSize);
2630 Y8950->deltat->memory_size = ROMSize;
2631 memset(Y8950->deltat->memory, 0xFF, ROMSize);
2632 YM_DELTAT_calc_mem_mask(Y8950->deltat);
2633 }
2634 if (DataStart > ROMSize)
2635 return;
2636 if (DataStart + DataLength > ROMSize)
2637 DataLength = ROMSize - DataStart;
2638
2639 memcpy(Y8950->deltat->memory + DataStart, ROMData, DataLength);
2640
2641 return;
2642 }
2643
2644 /*
2645 ** Generate samples for one of the Y8950's
2646 **
2647 ** 'which' is the virtual Y8950 number
2648 ** '*buffer' is the output buffer pointer
2649 ** 'length' is the number of samples that should be generated
2650 */
y8950_update_one(void * chip,OPLSAMPLE ** buffer,int length)2651 void y8950_update_one(void *chip, OPLSAMPLE **buffer, int length)
2652 {
2653 int i;
2654 FM_OPL *OPL = (FM_OPL *)chip;
2655 UINT8 rhythm = OPL->rhythm&0x20;
2656 YM_DELTAT *DELTAT = OPL->deltat;
2657 OPLSAMPLE *bufL = buffer[0];
2658 OPLSAMPLE *bufR = buffer[1];
2659
2660 for( i=0; i < length ; i++ )
2661 {
2662 int lt;
2663
2664 OPL->output[0] = 0;
2665 OPL->output_deltat[0] = 0;
2666
2667 advance_lfo(OPL);
2668
2669 /* deltaT ADPCM */
2670 if( DELTAT->portstate&0x80 && ! OPL->MuteSpc[5] )
2671 YM_DELTAT_ADPCM_CALC(DELTAT);
2672
2673 /* FM part */
2674 OPL_CALC_CH(OPL, &OPL->P_CH[0]);
2675 OPL_CALC_CH(OPL, &OPL->P_CH[1]);
2676 OPL_CALC_CH(OPL, &OPL->P_CH[2]);
2677 OPL_CALC_CH(OPL, &OPL->P_CH[3]);
2678 OPL_CALC_CH(OPL, &OPL->P_CH[4]);
2679 OPL_CALC_CH(OPL, &OPL->P_CH[5]);
2680
2681 if(!rhythm)
2682 {
2683 OPL_CALC_CH(OPL, &OPL->P_CH[6]);
2684 OPL_CALC_CH(OPL, &OPL->P_CH[7]);
2685 OPL_CALC_CH(OPL, &OPL->P_CH[8]);
2686 }
2687 else /* Rhythm part */
2688 {
2689 OPL_CALC_RH(OPL, &OPL->P_CH[0], (OPL->noise_rng>>0)&1 );
2690 }
2691
2692 lt = OPL->output[0] + (OPL->output_deltat[0]>>11);
2693
2694 lt >>= FINAL_SH;
2695
2696 /* limit check */
2697 //lt = limit( lt , MAXOUT, MINOUT );
2698
2699 #ifdef SAVE_SAMPLE
2700 if (which==0)
2701 {
2702 SAVE_ALL_CHANNELS
2703 }
2704 #endif
2705
2706 /* store to sound buffer */
2707 bufL[i] = lt;
2708 bufR[i] = lt;
2709
2710 advance(OPL);
2711 }
2712
2713 }
2714
y8950_set_port_handler(void * chip,OPL_PORTHANDLER_W PortHandler_w,OPL_PORTHANDLER_R PortHandler_r,void * param)2715 void y8950_set_port_handler(void *chip,OPL_PORTHANDLER_W PortHandler_w,OPL_PORTHANDLER_R PortHandler_r,void * param)
2716 {
2717 FM_OPL *OPL = (FM_OPL *)chip;
2718 OPL->porthandler_w = PortHandler_w;
2719 OPL->porthandler_r = PortHandler_r;
2720 OPL->port_param = param;
2721 }
2722
y8950_set_keyboard_handler(void * chip,OPL_PORTHANDLER_W KeyboardHandler_w,OPL_PORTHANDLER_R KeyboardHandler_r,void * param)2723 void y8950_set_keyboard_handler(void *chip,OPL_PORTHANDLER_W KeyboardHandler_w,OPL_PORTHANDLER_R KeyboardHandler_r,void * param)
2724 {
2725 FM_OPL *OPL = (FM_OPL *)chip;
2726 OPL->keyboardhandler_w = KeyboardHandler_w;
2727 OPL->keyboardhandler_r = KeyboardHandler_r;
2728 OPL->keyboard_param = param;
2729 }
2730
2731 #endif
2732
opl_set_mute_mask(void * chip,UINT32 MuteMask)2733 void opl_set_mute_mask(void *chip, UINT32 MuteMask)
2734 {
2735 FM_OPL *opl = (FM_OPL *)chip;
2736 UINT8 CurChn;
2737
2738 for (CurChn = 0; CurChn < 9; CurChn ++)
2739 opl->P_CH[CurChn].Muted = (MuteMask >> CurChn) & 0x01;
2740 for (CurChn = 0; CurChn < 6; CurChn ++)
2741 opl->MuteSpc[CurChn] = (MuteMask >> (9 + CurChn)) & 0x01;
2742
2743 return;
2744 }
2745