1 /*****************************************************************************
2 *
3 * Yamaha YM2151 driver (version 2.150 final beta)
4 *
5 ******************************************************************************/
6
7 #include <stdio.h>
8 #include <math.h>
9
10 #include "mamedef.h"
11 #include <stdlib.h>
12 #include <string.h> // for memset
13 #include <stddef.h> // for NULL
14 //#include "sndintrf.h"
15 //#include "streams.h"
16 #include "ym2151.h"
17
18
19 /* undef this to not use MAME timer system */
20 //#define USE_MAME_TIMERS
21
22 /*#define FM_EMU*/
23 #ifdef FM_EMU
24 #ifdef USE_MAME_TIMERS
25 #undef USE_MAME_TIMERS
26 #endif
27 #endif
28
29 //static char LOG_CYM_FILE = 0x00;
30 //static FILE * cymfile = NULL;
31
32
33 /* struct describing a single operator */
34 typedef struct{
35 UINT32 phase; /* accumulated operator phase */
36 UINT32 freq; /* operator frequency count */
37 INT32 dt1; /* current DT1 (detune 1 phase inc/decrement) value */
38 UINT32 mul; /* frequency count multiply */
39 UINT32 dt1_i; /* DT1 index * 32 */
40 UINT32 dt2; /* current DT2 (detune 2) value */
41
42 signed int *connect; /* operator output 'direction' */
43
44 /* only M1 (operator 0) is filled with this data: */
45 signed int *mem_connect; /* where to put the delayed sample (MEM) */
46 INT32 mem_value; /* delayed sample (MEM) value */
47
48 /* channel specific data; note: each operator number 0 contains channel specific data */
49 UINT32 fb_shift; /* feedback shift value for operators 0 in each channel */
50 INT32 fb_out_curr; /* operator feedback value (used only by operators 0) */
51 INT32 fb_out_prev; /* previous feedback value (used only by operators 0) */
52 UINT32 kc; /* channel KC (copied to all operators) */
53 UINT32 kc_i; /* just for speedup */
54 UINT32 pms; /* channel PMS */
55 UINT32 ams; /* channel AMS */
56 /* end of channel specific data */
57
58 UINT32 AMmask; /* LFO Amplitude Modulation enable mask */
59 UINT32 state; /* Envelope state: 4-attack(AR) 3-decay(D1R) 2-sustain(D2R) 1-release(RR) 0-off */
60 UINT8 eg_sh_ar; /* (attack state) */
61 UINT8 eg_sel_ar; /* (attack state) */
62 UINT32 tl; /* Total attenuation Level */
63 INT32 volume; /* current envelope attenuation level */
64 UINT8 eg_sh_d1r; /* (decay state) */
65 UINT8 eg_sel_d1r; /* (decay state) */
66 UINT32 d1l; /* envelope switches to sustain state after reaching this level */
67 UINT8 eg_sh_d2r; /* (sustain state) */
68 UINT8 eg_sel_d2r; /* (sustain state) */
69 UINT8 eg_sh_rr; /* (release state) */
70 UINT8 eg_sel_rr; /* (release state) */
71
72 UINT32 key; /* 0=last key was KEY OFF, 1=last key was KEY ON */
73
74 UINT32 ks; /* key scale */
75 UINT32 ar; /* attack rate */
76 UINT32 d1r; /* decay rate */
77 UINT32 d2r; /* sustain rate */
78 UINT32 rr; /* release rate */
79
80 UINT32 reserved0; /**/
81 UINT32 reserved1; /**/
82
83 } YM2151Operator;
84
85
86 typedef struct
87 {
88 YM2151Operator oper[32]; /* the 32 operators */
89
90 UINT32 pan[16]; /* channels output masks (0xffffffff = enable) */
91 UINT8 Muted[8]; /* used for muting */
92
93 UINT32 eg_cnt; /* global envelope generator counter */
94 UINT32 eg_timer; /* global envelope generator counter works at frequency = chipclock/64/3 */
95 UINT32 eg_timer_add; /* step of eg_timer */
96 UINT32 eg_timer_overflow; /* envelope generator timer overlfows every 3 samples (on real chip) */
97
98 UINT32 lfo_phase; /* accumulated LFO phase (0 to 255) */
99 UINT32 lfo_timer; /* LFO timer */
100 UINT32 lfo_timer_add; /* step of lfo_timer */
101 UINT32 lfo_overflow; /* LFO generates new output when lfo_timer reaches this value */
102 UINT32 lfo_counter; /* LFO phase increment counter */
103 UINT32 lfo_counter_add; /* step of lfo_counter */
104 UINT8 lfo_wsel; /* LFO waveform (0-saw, 1-square, 2-triangle, 3-random noise) */
105 UINT8 amd; /* LFO Amplitude Modulation Depth */
106 INT8 pmd; /* LFO Phase Modulation Depth */
107 UINT32 lfa; /* LFO current AM output */
108 INT32 lfp; /* LFO current PM output */
109
110 UINT8 test; /* TEST register */
111 UINT8 ct; /* output control pins (bit1-CT2, bit0-CT1) */
112
113 UINT32 noise; /* noise enable/period register (bit 7 - noise enable, bits 4-0 - noise period */
114 UINT32 noise_rng; /* 17 bit noise shift register */
115 UINT32 noise_p; /* current noise 'phase'*/
116 UINT32 noise_f; /* current noise period */
117
118 UINT32 csm_req; /* CSM KEY ON / KEY OFF sequence request */
119
120 UINT32 irq_enable; /* IRQ enable for timer B (bit 3) and timer A (bit 2); bit 7 - CSM mode (keyon to all slots, everytime timer A overflows) */
121 UINT32 status; /* chip status (BUSY, IRQ Flags) */
122 UINT8 connect[8]; /* channels connections */
123
124 #ifdef USE_MAME_TIMERS
125 /* ASG 980324 -- added for tracking timers */
126 emu_timer *timer_A;
127 emu_timer *timer_B;
128 attotime timer_A_time[1024]; /* timer A times for MAME */
129 attotime timer_B_time[256]; /* timer B times for MAME */
130 int irqlinestate;
131 #else
132 UINT8 tim_A; /* timer A enable (0-disabled) */
133 UINT8 tim_B; /* timer B enable (0-disabled) */
134 INT32 tim_A_val; /* current value of timer A */
135 INT32 tim_B_val; /* current value of timer B */
136 UINT32 tim_A_tab[1024]; /* timer A deltas */
137 UINT32 tim_B_tab[256]; /* timer B deltas */
138 #endif
139 UINT32 timer_A_index; /* timer A index */
140 UINT32 timer_B_index; /* timer B index */
141 UINT32 timer_A_index_old; /* timer A previous index */
142 UINT32 timer_B_index_old; /* timer B previous index */
143
144 /* Frequency-deltas to get the closest frequency possible.
145 * There are 11 octaves because of DT2 (max 950 cents over base frequency)
146 * and LFO phase modulation (max 800 cents below AND over base frequency)
147 * Summary: octave explanation
148 * 0 note code - LFO PM
149 * 1 note code
150 * 2 note code
151 * 3 note code
152 * 4 note code
153 * 5 note code
154 * 6 note code
155 * 7 note code
156 * 8 note code
157 * 9 note code + DT2 + LFO PM
158 * 10 note code + DT2 + LFO PM
159 */
160 UINT32 freq[11*768]; /* 11 octaves, 768 'cents' per octave */
161
162 /* Frequency deltas for DT1. These deltas alter operator frequency
163 * after it has been taken from frequency-deltas table.
164 */
165 INT32 dt1_freq[8*32]; /* 8 DT1 levels, 32 KC values */
166
167 UINT32 noise_tab[32]; /* 17bit Noise Generator periods */
168
169 //void (*irqhandler)(const device_config *device, int irq); /* IRQ function handler */
170 //write8_device_func porthandler; /* port write function handler */
171
172 //const device_config *device;
173 unsigned int clock; /* chip clock in Hz (passed from 2151intf.c) */
174 unsigned int sampfreq; /* sampling frequency in Hz (passed from 2151intf.c) */
175 } YM2151;
176
177
178 #define FREQ_SH 16 /* 16.16 fixed point (frequency calculations) */
179 #define EG_SH 16 /* 16.16 fixed point (envelope generator timing) */
180 #define LFO_SH 10 /* 22.10 fixed point (LFO calculations) */
181 #define TIMER_SH 16 /* 16.16 fixed point (timers calculations) */
182
183 #define FREQ_MASK ((1<<FREQ_SH)-1)
184
185 #define ENV_BITS 10
186 #define ENV_LEN (1<<ENV_BITS)
187 #define ENV_STEP (128.0/ENV_LEN)
188
189 #define MAX_ATT_INDEX (ENV_LEN-1) /* 1023 */
190 #define MIN_ATT_INDEX (0) /* 0 */
191
192 #define EG_ATT 4
193 #define EG_DEC 3
194 #define EG_SUS 2
195 #define EG_REL 1
196 #define EG_OFF 0
197
198 #define SIN_BITS 10
199 #define SIN_LEN (1<<SIN_BITS)
200 #define SIN_MASK (SIN_LEN-1)
201
202 #define TL_RES_LEN (256) /* 8 bits addressing (real chip) */
203
204
205 #if (SAMPLE_BITS==16)
206 #define FINAL_SH (0)
207 #define MAXOUT (+32767)
208 #define MINOUT (-32768)
209 #else
210 #define FINAL_SH (8)
211 #define MAXOUT (+127)
212 #define MINOUT (-128)
213 #endif
214
215
216 /* TL_TAB_LEN is calculated as:
217 * 13 - sinus amplitude bits (Y axis)
218 * 2 - sinus sign bit (Y axis)
219 * TL_RES_LEN - sinus resolution (X axis)
220 */
221 #define TL_TAB_LEN (13*2*TL_RES_LEN)
222 static signed int tl_tab[TL_TAB_LEN];
223
224 #define ENV_QUIET (TL_TAB_LEN>>3)
225
226 /* sin waveform table in 'decibel' scale */
227 static unsigned int sin_tab[SIN_LEN];
228
229
230 /* translate from D1L to volume index (16 D1L levels) */
231 static UINT32 d1l_tab[16];
232
233
234 #define RATE_STEPS (8)
235 static const UINT8 eg_inc[19*RATE_STEPS]={
236
237 /*cycle:0 1 2 3 4 5 6 7*/
238
239 /* 0 */ 0,1, 0,1, 0,1, 0,1, /* rates 00..11 0 (increment by 0 or 1) */
240 /* 1 */ 0,1, 0,1, 1,1, 0,1, /* rates 00..11 1 */
241 /* 2 */ 0,1, 1,1, 0,1, 1,1, /* rates 00..11 2 */
242 /* 3 */ 0,1, 1,1, 1,1, 1,1, /* rates 00..11 3 */
243
244 /* 4 */ 1,1, 1,1, 1,1, 1,1, /* rate 12 0 (increment by 1) */
245 /* 5 */ 1,1, 1,2, 1,1, 1,2, /* rate 12 1 */
246 /* 6 */ 1,2, 1,2, 1,2, 1,2, /* rate 12 2 */
247 /* 7 */ 1,2, 2,2, 1,2, 2,2, /* rate 12 3 */
248
249 /* 8 */ 2,2, 2,2, 2,2, 2,2, /* rate 13 0 (increment by 2) */
250 /* 9 */ 2,2, 2,4, 2,2, 2,4, /* rate 13 1 */
251 /*10 */ 2,4, 2,4, 2,4, 2,4, /* rate 13 2 */
252 /*11 */ 2,4, 4,4, 2,4, 4,4, /* rate 13 3 */
253
254 /*12 */ 4,4, 4,4, 4,4, 4,4, /* rate 14 0 (increment by 4) */
255 /*13 */ 4,4, 4,8, 4,4, 4,8, /* rate 14 1 */
256 /*14 */ 4,8, 4,8, 4,8, 4,8, /* rate 14 2 */
257 /*15 */ 4,8, 8,8, 4,8, 8,8, /* rate 14 3 */
258
259 /*16 */ 8,8, 8,8, 8,8, 8,8, /* rates 15 0, 15 1, 15 2, 15 3 (increment by 8) */
260 /*17 */ 16,16,16,16,16,16,16,16, /* rates 15 2, 15 3 for attack */
261 /*18 */ 0,0, 0,0, 0,0, 0,0, /* infinity rates for attack and decay(s) */
262 };
263
264
265 #define O(a) (a*RATE_STEPS)
266
267 /*note that there is no O(17) in this table - it's directly in the code */
268 static const UINT8 eg_rate_select[32+64+32]={ /* Envelope Generator rates (32 + 64 rates + 32 RKS) */
269 /* 32 dummy (infinite time) rates */
270 O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
271 O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
272 O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
273 O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
274
275 /* rates 00-11 */
276 O( 0),O( 1),O( 2),O( 3),
277 O( 0),O( 1),O( 2),O( 3),
278 O( 0),O( 1),O( 2),O( 3),
279 O( 0),O( 1),O( 2),O( 3),
280 O( 0),O( 1),O( 2),O( 3),
281 O( 0),O( 1),O( 2),O( 3),
282 O( 0),O( 1),O( 2),O( 3),
283 O( 0),O( 1),O( 2),O( 3),
284 O( 0),O( 1),O( 2),O( 3),
285 O( 0),O( 1),O( 2),O( 3),
286 O( 0),O( 1),O( 2),O( 3),
287 O( 0),O( 1),O( 2),O( 3),
288
289 /* rate 12 */
290 O( 4),O( 5),O( 6),O( 7),
291
292 /* rate 13 */
293 O( 8),O( 9),O(10),O(11),
294
295 /* rate 14 */
296 O(12),O(13),O(14),O(15),
297
298 /* rate 15 */
299 O(16),O(16),O(16),O(16),
300
301 /* 32 dummy rates (same as 15 3) */
302 O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16),
303 O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16),
304 O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16),
305 O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16)
306
307 };
308 #undef O
309
310 /*rate 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15*/
311 /*shift 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 0, 0, 0, 0 */
312 /*mask 2047, 1023, 511, 255, 127, 63, 31, 15, 7, 3, 1, 0, 0, 0, 0, 0 */
313
314 #define O(a) (a*1)
315 static const UINT8 eg_rate_shift[32+64+32]={ /* Envelope Generator counter shifts (32 + 64 rates + 32 RKS) */
316 /* 32 infinite time rates */
317 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
318 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
319 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
320 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
321
322
323 /* rates 00-11 */
324 O(11),O(11),O(11),O(11),
325 O(10),O(10),O(10),O(10),
326 O( 9),O( 9),O( 9),O( 9),
327 O( 8),O( 8),O( 8),O( 8),
328 O( 7),O( 7),O( 7),O( 7),
329 O( 6),O( 6),O( 6),O( 6),
330 O( 5),O( 5),O( 5),O( 5),
331 O( 4),O( 4),O( 4),O( 4),
332 O( 3),O( 3),O( 3),O( 3),
333 O( 2),O( 2),O( 2),O( 2),
334 O( 1),O( 1),O( 1),O( 1),
335 O( 0),O( 0),O( 0),O( 0),
336
337 /* rate 12 */
338 O( 0),O( 0),O( 0),O( 0),
339
340 /* rate 13 */
341 O( 0),O( 0),O( 0),O( 0),
342
343 /* rate 14 */
344 O( 0),O( 0),O( 0),O( 0),
345
346 /* rate 15 */
347 O( 0),O( 0),O( 0),O( 0),
348
349 /* 32 dummy rates (same as 15 3) */
350 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
351 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
352 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
353 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0)
354
355 };
356 #undef O
357
358 /* DT2 defines offset in cents from base note
359 *
360 * This table defines offset in frequency-deltas table.
361 * User's Manual page 22
362 *
363 * Values below were calculated using formula: value = orig.val / 1.5625
364 *
365 * DT2=0 DT2=1 DT2=2 DT2=3
366 * 0 600 781 950
367 */
368 static const UINT32 dt2_tab[4] = { 0, 384, 500, 608 };
369
370 /* DT1 defines offset in Hertz from base note
371 * This table is converted while initialization...
372 * Detune table shown in YM2151 User's Manual is wrong (verified on the real chip)
373 */
374
375 static const UINT8 dt1_tab[4*32] = { /* 4*32 DT1 values */
376 /* DT1=0 */
377 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
378 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
379
380 /* DT1=1 */
381 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,
382 2, 3, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 8, 8, 8, 8,
383
384 /* DT1=2 */
385 1, 1, 1, 1, 2, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5,
386 5, 6, 6, 7, 8, 8, 9,10,11,12,13,14,16,16,16,16,
387
388 /* DT1=3 */
389 2, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7,
390 8, 8, 9,10,11,12,13,14,16,17,19,20,22,22,22,22
391 };
392
393 static const UINT16 phaseinc_rom[768]={
394 1299,1300,1301,1302,1303,1304,1305,1306,1308,1309,1310,1311,1313,1314,1315,1316,
395 1318,1319,1320,1321,1322,1323,1324,1325,1327,1328,1329,1330,1332,1333,1334,1335,
396 1337,1338,1339,1340,1341,1342,1343,1344,1346,1347,1348,1349,1351,1352,1353,1354,
397 1356,1357,1358,1359,1361,1362,1363,1364,1366,1367,1368,1369,1371,1372,1373,1374,
398 1376,1377,1378,1379,1381,1382,1383,1384,1386,1387,1388,1389,1391,1392,1393,1394,
399 1396,1397,1398,1399,1401,1402,1403,1404,1406,1407,1408,1409,1411,1412,1413,1414,
400 1416,1417,1418,1419,1421,1422,1423,1424,1426,1427,1429,1430,1431,1432,1434,1435,
401 1437,1438,1439,1440,1442,1443,1444,1445,1447,1448,1449,1450,1452,1453,1454,1455,
402 1458,1459,1460,1461,1463,1464,1465,1466,1468,1469,1471,1472,1473,1474,1476,1477,
403 1479,1480,1481,1482,1484,1485,1486,1487,1489,1490,1492,1493,1494,1495,1497,1498,
404 1501,1502,1503,1504,1506,1507,1509,1510,1512,1513,1514,1515,1517,1518,1520,1521,
405 1523,1524,1525,1526,1528,1529,1531,1532,1534,1535,1536,1537,1539,1540,1542,1543,
406 1545,1546,1547,1548,1550,1551,1553,1554,1556,1557,1558,1559,1561,1562,1564,1565,
407 1567,1568,1569,1570,1572,1573,1575,1576,1578,1579,1580,1581,1583,1584,1586,1587,
408 1590,1591,1592,1593,1595,1596,1598,1599,1601,1602,1604,1605,1607,1608,1609,1610,
409 1613,1614,1615,1616,1618,1619,1621,1622,1624,1625,1627,1628,1630,1631,1632,1633,
410 1637,1638,1639,1640,1642,1643,1645,1646,1648,1649,1651,1652,1654,1655,1656,1657,
411 1660,1661,1663,1664,1666,1667,1669,1670,1672,1673,1675,1676,1678,1679,1681,1682,
412 1685,1686,1688,1689,1691,1692,1694,1695,1697,1698,1700,1701,1703,1704,1706,1707,
413 1709,1710,1712,1713,1715,1716,1718,1719,1721,1722,1724,1725,1727,1728,1730,1731,
414 1734,1735,1737,1738,1740,1741,1743,1744,1746,1748,1749,1751,1752,1754,1755,1757,
415 1759,1760,1762,1763,1765,1766,1768,1769,1771,1773,1774,1776,1777,1779,1780,1782,
416 1785,1786,1788,1789,1791,1793,1794,1796,1798,1799,1801,1802,1804,1806,1807,1809,
417 1811,1812,1814,1815,1817,1819,1820,1822,1824,1825,1827,1828,1830,1832,1833,1835,
418 1837,1838,1840,1841,1843,1845,1846,1848,1850,1851,1853,1854,1856,1858,1859,1861,
419 1864,1865,1867,1868,1870,1872,1873,1875,1877,1879,1880,1882,1884,1885,1887,1888,
420 1891,1892,1894,1895,1897,1899,1900,1902,1904,1906,1907,1909,1911,1912,1914,1915,
421 1918,1919,1921,1923,1925,1926,1928,1930,1932,1933,1935,1937,1939,1940,1942,1944,
422 1946,1947,1949,1951,1953,1954,1956,1958,1960,1961,1963,1965,1967,1968,1970,1972,
423 1975,1976,1978,1980,1982,1983,1985,1987,1989,1990,1992,1994,1996,1997,1999,2001,
424 2003,2004,2006,2008,2010,2011,2013,2015,2017,2019,2021,2022,2024,2026,2028,2029,
425 2032,2033,2035,2037,2039,2041,2043,2044,2047,2048,2050,2052,2054,2056,2058,2059,
426 2062,2063,2065,2067,2069,2071,2073,2074,2077,2078,2080,2082,2084,2086,2088,2089,
427 2092,2093,2095,2097,2099,2101,2103,2104,2107,2108,2110,2112,2114,2116,2118,2119,
428 2122,2123,2125,2127,2129,2131,2133,2134,2137,2139,2141,2142,2145,2146,2148,2150,
429 2153,2154,2156,2158,2160,2162,2164,2165,2168,2170,2172,2173,2176,2177,2179,2181,
430 2185,2186,2188,2190,2192,2194,2196,2197,2200,2202,2204,2205,2208,2209,2211,2213,
431 2216,2218,2220,2222,2223,2226,2227,2230,2232,2234,2236,2238,2239,2242,2243,2246,
432 2249,2251,2253,2255,2256,2259,2260,2263,2265,2267,2269,2271,2272,2275,2276,2279,
433 2281,2283,2285,2287,2288,2291,2292,2295,2297,2299,2301,2303,2304,2307,2308,2311,
434 2315,2317,2319,2321,2322,2325,2326,2329,2331,2333,2335,2337,2338,2341,2342,2345,
435 2348,2350,2352,2354,2355,2358,2359,2362,2364,2366,2368,2370,2371,2374,2375,2378,
436 2382,2384,2386,2388,2389,2392,2393,2396,2398,2400,2402,2404,2407,2410,2411,2414,
437 2417,2419,2421,2423,2424,2427,2428,2431,2433,2435,2437,2439,2442,2445,2446,2449,
438 2452,2454,2456,2458,2459,2462,2463,2466,2468,2470,2472,2474,2477,2480,2481,2484,
439 2488,2490,2492,2494,2495,2498,2499,2502,2504,2506,2508,2510,2513,2516,2517,2520,
440 2524,2526,2528,2530,2531,2534,2535,2538,2540,2542,2544,2546,2549,2552,2553,2556,
441 2561,2563,2565,2567,2568,2571,2572,2575,2577,2579,2581,2583,2586,2589,2590,2593
442 };
443
444
445 /*
446 Noise LFO waveform.
447
448 Here are just 256 samples out of much longer data.
449
450 It does NOT repeat every 256 samples on real chip and I wasnt able to find
451 the point where it repeats (even in strings as long as 131072 samples).
452
453 I only put it here because its better than nothing and perhaps
454 someone might be able to figure out the real algorithm.
455
456
457 Note that (due to the way the LFO output is calculated) it is quite
458 possible that two values: 0x80 and 0x00 might be wrong in this table.
459 To be exact:
460 some 0x80 could be 0x81 as well as some 0x00 could be 0x01.
461 */
462
463 static const UINT8 lfo_noise_waveform[256] = {
464 0xFF,0xEE,0xD3,0x80,0x58,0xDA,0x7F,0x94,0x9E,0xE3,0xFA,0x00,0x4D,0xFA,0xFF,0x6A,
465 0x7A,0xDE,0x49,0xF6,0x00,0x33,0xBB,0x63,0x91,0x60,0x51,0xFF,0x00,0xD8,0x7F,0xDE,
466 0xDC,0x73,0x21,0x85,0xB2,0x9C,0x5D,0x24,0xCD,0x91,0x9E,0x76,0x7F,0x20,0xFB,0xF3,
467 0x00,0xA6,0x3E,0x42,0x27,0x69,0xAE,0x33,0x45,0x44,0x11,0x41,0x72,0x73,0xDF,0xA2,
468
469 0x32,0xBD,0x7E,0xA8,0x13,0xEB,0xD3,0x15,0xDD,0xFB,0xC9,0x9D,0x61,0x2F,0xBE,0x9D,
470 0x23,0x65,0x51,0x6A,0x84,0xF9,0xC9,0xD7,0x23,0xBF,0x65,0x19,0xDC,0x03,0xF3,0x24,
471 0x33,0xB6,0x1E,0x57,0x5C,0xAC,0x25,0x89,0x4D,0xC5,0x9C,0x99,0x15,0x07,0xCF,0xBA,
472 0xC5,0x9B,0x15,0x4D,0x8D,0x2A,0x1E,0x1F,0xEA,0x2B,0x2F,0x64,0xA9,0x50,0x3D,0xAB,
473
474 0x50,0x77,0xE9,0xC0,0xAC,0x6D,0x3F,0xCA,0xCF,0x71,0x7D,0x80,0xA6,0xFD,0xFF,0xB5,
475 0xBD,0x6F,0x24,0x7B,0x00,0x99,0x5D,0xB1,0x48,0xB0,0x28,0x7F,0x80,0xEC,0xBF,0x6F,
476 0x6E,0x39,0x90,0x42,0xD9,0x4E,0x2E,0x12,0x66,0xC8,0xCF,0x3B,0x3F,0x10,0x7D,0x79,
477 0x00,0xD3,0x1F,0x21,0x93,0x34,0xD7,0x19,0x22,0xA2,0x08,0x20,0xB9,0xB9,0xEF,0x51,
478
479 0x99,0xDE,0xBF,0xD4,0x09,0x75,0xE9,0x8A,0xEE,0xFD,0xE4,0x4E,0x30,0x17,0xDF,0xCE,
480 0x11,0xB2,0x28,0x35,0xC2,0x7C,0x64,0xEB,0x91,0x5F,0x32,0x0C,0x6E,0x00,0xF9,0x92,
481 0x19,0xDB,0x8F,0xAB,0xAE,0xD6,0x12,0xC4,0x26,0x62,0xCE,0xCC,0x0A,0x03,0xE7,0xDD,
482 0xE2,0x4D,0x8A,0xA6,0x46,0x95,0x0F,0x8F,0xF5,0x15,0x97,0x32,0xD4,0x28,0x1E,0x55
483 };
484
485
486
487 /* these variables stay here for speedup purposes only */
488 static YM2151 * PSG;
489 static signed int chanout[8];
490 static signed int m2,c1,c2; /* Phase Modulation input for operators 2,3,4 */
491 static signed int mem; /* one sample delay memory */
492
493
494 /* save output as raw 16-bit sample */
495 // #define SAVE_SAMPLE
496 // #define SAVE_SEPARATE_CHANNELS
497 #if defined SAVE_SAMPLE || defined SAVE_SEPARATE_CHANNELS
498 #include <stdio.h>
499
500 static FILE *sample[9];
501 #endif
502
503
504
505
init_tables(void)506 static void init_tables(void)
507 {
508 signed int i,x,n;
509 double o,m;
510
511 for (x=0; x<TL_RES_LEN; x++)
512 {
513 m = (1<<16) / pow(2, (x+1) * (ENV_STEP/4.0) / 8.0);
514 m = floor(m);
515
516 /* we never reach (1<<16) here due to the (x+1) */
517 /* result fits within 16 bits at maximum */
518
519 n = (int)m; /* 16 bits here */
520 n >>= 4; /* 12 bits here */
521 if (n&1) /* round to closest */
522 n = (n>>1)+1;
523 else
524 n = n>>1;
525 /* 11 bits here (rounded) */
526 n <<= 2; /* 13 bits here (as in real chip) */
527 tl_tab[ x*2 + 0 ] = n;
528 tl_tab[ x*2 + 1 ] = -tl_tab[ x*2 + 0 ];
529
530 for (i=1; i<13; i++)
531 {
532 tl_tab[ x*2+0 + i*2*TL_RES_LEN ] = tl_tab[ x*2+0 ]>>i;
533 tl_tab[ x*2+1 + i*2*TL_RES_LEN ] = -tl_tab[ x*2+0 + i*2*TL_RES_LEN ];
534 }
535 #if 0
536 logerror("tl %04i", x*2);
537 for (i=0; i<13; i++)
538 logerror(", [%02i] %4i", i*2, tl_tab[ x*2 /*+1*/ + i*2*TL_RES_LEN ]);
539 logerror("\n");
540 #endif
541 }
542 /*logerror("TL_TAB_LEN = %i (%i bytes)\n",TL_TAB_LEN, (int)sizeof(tl_tab));*/
543 /*logerror("ENV_QUIET= %i\n",ENV_QUIET );*/
544
545
546 for (i=0; i<SIN_LEN; i++)
547 {
548 /* non-standard sinus */
549 m = sin( ((i*2)+1) * M_PI / SIN_LEN ); /* verified on the real chip */
550
551 /* we never reach zero here due to ((i*2)+1) */
552
553 if (m>0.0)
554 o = 8*log(1.0/m)/log(2.0); /* convert to 'decibels' */
555 else
556 o = 8*log(-1.0/m)/log(2.0); /* convert to 'decibels' */
557
558 o = o / (ENV_STEP/4);
559
560 n = (int)(2.0*o);
561 if (n&1) /* round to closest */
562 n = (n>>1)+1;
563 else
564 n = n>>1;
565
566 sin_tab[ i ] = n*2 + (m>=0.0? 0: 1 );
567 /*logerror("sin [0x%4x]= %4i (tl_tab value=%8x)\n", i, sin_tab[i],tl_tab[sin_tab[i]]);*/
568 }
569
570
571 /* calculate d1l_tab table */
572 for (i=0; i<16; i++)
573 {
574 m = (i!=15 ? i : i+16) * (4.0/ENV_STEP); /* every 3 'dB' except for all bits = 1 = 45+48 'dB' */
575 d1l_tab[i] = m;
576 /*logerror("d1l_tab[%02x]=%08x\n",i,d1l_tab[i] );*/
577 }
578
579 #ifdef SAVE_SAMPLE
580 sample[8]=fopen("sampsum.pcm","wb");
581 #endif
582 #ifdef SAVE_SEPARATE_CHANNELS
583 sample[0]=fopen("samp0.pcm","wb");
584 sample[1]=fopen("samp1.pcm","wb");
585 sample[2]=fopen("samp2.pcm","wb");
586 sample[3]=fopen("samp3.pcm","wb");
587 sample[4]=fopen("samp4.pcm","wb");
588 sample[5]=fopen("samp5.pcm","wb");
589 sample[6]=fopen("samp6.pcm","wb");
590 sample[7]=fopen("samp7.pcm","wb");
591 #endif
592 }
593
594
init_chip_tables(YM2151 * chip)595 static void init_chip_tables(YM2151 *chip)
596 {
597 int i,j;
598 double mult,phaseinc,Hz;
599 double scaler;
600 //attotime pom;
601 double pom;
602
603 scaler = ( (double)chip->clock / 64.0 ) / ( (double)chip->sampfreq );
604 /*logerror("scaler = %20.15f\n", scaler);*/
605
606
607 /* this loop calculates Hertz values for notes from c-0 to b-7 */
608 /* including 64 'cents' (100/64 that is 1.5625 of real cent) per note */
609 /* i*100/64/1200 is equal to i/768 */
610
611 /* real chip works with 10 bits fixed point values (10.10) */
612 mult = (1<<(FREQ_SH-10)); /* -10 because phaseinc_rom table values are already in 10.10 format */
613
614 for (i=0; i<768; i++)
615 {
616 /* 3.4375 Hz is note A; C# is 4 semitones higher */
617 Hz = 1000;
618 #if 0
619 /* Hz is close, but not perfect */
620 //Hz = scaler * 3.4375 * pow (2, (i + 4 * 64 ) / 768.0 );
621 /* calculate phase increment */
622 phaseinc = (Hz*SIN_LEN) / (double)chip->sampfreq;
623 #endif
624
625 phaseinc = phaseinc_rom[i]; /* real chip phase increment */
626 phaseinc *= scaler; /* adjust */
627
628
629 /* octave 2 - reference octave */
630 chip->freq[ 768+2*768+i ] = ((int)(phaseinc*mult)) & 0xffffffc0; /* adjust to X.10 fixed point */
631 /* octave 0 and octave 1 */
632 for (j=0; j<2; j++)
633 {
634 chip->freq[768 + j*768 + i] = (chip->freq[ 768+2*768+i ] >> (2-j) ) & 0xffffffc0; /* adjust to X.10 fixed point */
635 }
636 /* octave 3 to 7 */
637 for (j=3; j<8; j++)
638 {
639 chip->freq[768 + j*768 + i] = chip->freq[ 768+2*768+i ] << (j-2);
640 }
641
642 #if 0
643 pom = (double)chip->freq[ 768+2*768+i ] / ((double)(1<<FREQ_SH));
644 pom = pom * (double)chip->sampfreq / (double)SIN_LEN;
645 logerror("1freq[%4i][%08x]= real %20.15f Hz emul %20.15f Hz\n", i, chip->freq[ 768+2*768+i ], Hz, pom);
646 #endif
647 }
648
649 /* octave -1 (all equal to: oct 0, _KC_00_, _KF_00_) */
650 for (i=0; i<768; i++)
651 {
652 chip->freq[ 0*768 + i ] = chip->freq[1*768+0];
653 }
654
655 /* octave 8 and 9 (all equal to: oct 7, _KC_14_, _KF_63_) */
656 for (j=8; j<10; j++)
657 {
658 for (i=0; i<768; i++)
659 {
660 chip->freq[768+ j*768 + i ] = chip->freq[768 + 8*768 -1];
661 }
662 }
663
664 #if 0
665 for (i=0; i<11*768; i++)
666 {
667 pom = (double)chip->freq[i] / ((double)(1<<FREQ_SH));
668 pom = pom * (double)chip->sampfreq / (double)SIN_LEN;
669 logerror("freq[%4i][%08x]= emul %20.15f Hz\n", i, chip->freq[i], pom);
670 }
671 #endif
672
673 mult = (1<<FREQ_SH);
674 for (j=0; j<4; j++)
675 {
676 for (i=0; i<32; i++)
677 {
678 Hz = ( (double)dt1_tab[j*32+i] * ((double)chip->clock/64.0) ) / (double)(1<<20);
679
680 /*calculate phase increment*/
681 phaseinc = (Hz*SIN_LEN) / (double)chip->sampfreq;
682
683 /*positive and negative values*/
684 chip->dt1_freq[ (j+0)*32 + i ] = phaseinc * mult;
685 chip->dt1_freq[ (j+4)*32 + i ] = -chip->dt1_freq[ (j+0)*32 + i ];
686
687 #if 0
688 {
689 int x = j*32 + i;
690 pom = (double)chip->dt1_freq[x] / mult;
691 pom = pom * (double)chip->sampfreq / (double)SIN_LEN;
692 logerror("DT1(%03i)[%02i %02i][%08x]= real %19.15f Hz emul %19.15f Hz\n",
693 x, j, i, chip->dt1_freq[x], Hz, pom);
694 }
695 #endif
696 }
697 }
698
699
700 /* calculate timers' deltas */
701 /* User's Manual pages 15,16 */
702 mult = (1<<TIMER_SH);
703 for (i=0; i<1024; i++)
704 {
705 /* ASG 980324: changed to compute both tim_A_tab and timer_A_time */
706 //pom= attotime_mul(ATTOTIME_IN_HZ(chip->clock), 64 * (1024 - i));
707 pom = ((double)64 * (1024 - i) / chip->clock);
708 #ifdef USE_MAME_TIMERS
709 chip->timer_A_time[i] = pom;
710 #else
711 //chip->tim_A_tab[i] = attotime_to_double(pom) * (double)chip->sampfreq * mult; /* number of samples that timer period takes (fixed point) */
712 chip->tim_A_tab[i] = pom * (double)chip->sampfreq * mult; /* number of samples that timer period takes (fixed point) */
713 #endif
714 }
715 for (i=0; i<256; i++)
716 {
717 /* ASG 980324: changed to compute both tim_B_tab and timer_B_time */
718 //pom= attotime_mul(ATTOTIME_IN_HZ(chip->clock), 1024 * (256 - i));
719 pom = ((double)1024 * (256 - i) / chip->clock);
720 #ifdef USE_MAME_TIMERS
721 chip->timer_B_time[i] = pom;
722 #else
723 //chip->tim_B_tab[i] = attotime_to_double(pom) * (double)chip->sampfreq * mult; /* number of samples that timer period takes (fixed point) */
724 chip->tim_B_tab[i] = pom * (double)chip->sampfreq * mult; /* number of samples that timer period takes (fixed point) */
725 #endif
726 }
727
728 /* calculate noise periods table */
729 scaler = ( (double)chip->clock / 64.0 ) / ( (double)chip->sampfreq );
730 for (i=0; i<32; i++)
731 {
732 j = (i!=31 ? i : 30); /* rate 30 and 31 are the same */
733 j = 32-j;
734 j = (65536.0 / (double)(j*32.0)); /* number of samples per one shift of the shift register */
735 /*chip->noise_tab[i] = j * 64;*/ /* number of chip clock cycles per one shift */
736 chip->noise_tab[i] = j * 64 * scaler;
737 /*logerror("noise_tab[%02x]=%08x\n", i, chip->noise_tab[i]);*/
738 }
739 }
740
741 #define KEY_ON(op, key_set){ \
742 if (!(op)->key) \
743 { \
744 (op)->phase = 0; /* clear phase */ \
745 (op)->state = EG_ATT; /* KEY ON = attack */ \
746 (op)->volume += (~(op)->volume * \
747 (eg_inc[(op)->eg_sel_ar + ((PSG->eg_cnt>>(op)->eg_sh_ar)&7)]) \
748 ) >>4; \
749 if ((op)->volume <= MIN_ATT_INDEX) \
750 { \
751 (op)->volume = MIN_ATT_INDEX; \
752 (op)->state = EG_DEC; \
753 } \
754 } \
755 (op)->key |= key_set; \
756 }
757
758 #define KEY_OFF(op, key_clr){ \
759 if ((op)->key) \
760 { \
761 (op)->key &= key_clr; \
762 if (!(op)->key) \
763 { \
764 if ((op)->state>EG_REL) \
765 (op)->state = EG_REL;/* KEY OFF = release */\
766 } \
767 } \
768 }
769
envelope_KONKOFF(YM2151Operator * op,int v)770 INLINE void envelope_KONKOFF(YM2151Operator * op, int v)
771 {
772 if (v&0x08) /* M1 */
773 KEY_ON (op+0, 1)
774 else
775 KEY_OFF(op+0,~1)
776
777 if (v&0x20) /* M2 */
778 KEY_ON (op+1, 1)
779 else
780 KEY_OFF(op+1,~1)
781
782 if (v&0x10) /* C1 */
783 KEY_ON (op+2, 1)
784 else
785 KEY_OFF(op+2,~1)
786
787 if (v&0x40) /* C2 */
788 KEY_ON (op+3, 1)
789 else
790 KEY_OFF(op+3,~1)
791 }
792
793
794 #ifdef USE_MAME_TIMERS
795
796 /*static TIMER_CALLBACK( irqAon_callback )
797 {
798 YM2151 *chip = (YM2151 *)ptr;
799 int oldstate = chip->irqlinestate;
800
801 chip->irqlinestate |= 1;
802
803 if (oldstate == 0 && chip->irqhandler) (*chip->irqhandler)(chip->device, 1);
804 }
805
806 static TIMER_CALLBACK( irqBon_callback )
807 {
808 YM2151 *chip = (YM2151 *)ptr;
809 int oldstate = chip->irqlinestate;
810
811 chip->irqlinestate |= 2;
812
813 if (oldstate == 0 && chip->irqhandler) (*chip->irqhandler)(chip->device, 1);
814 }
815
816 static TIMER_CALLBACK( irqAoff_callback )
817 {
818 YM2151 *chip = (YM2151 *)ptr;
819 int oldstate = chip->irqlinestate;
820
821 chip->irqlinestate &= ~1;
822
823 if (oldstate == 1 && chip->irqhandler) (*chip->irqhandler)(chip->device, 0);
824 }
825
826 static TIMER_CALLBACK( irqBoff_callback )
827 {
828 YM2151 *chip = (YM2151 *)ptr;
829 int oldstate = chip->irqlinestate;
830
831 chip->irqlinestate &= ~2;
832
833 if (oldstate == 2 && chip->irqhandler) (*chip->irqhandler)(chip->device, 0);
834 }
835
836 static TIMER_CALLBACK( timer_callback_a )
837 {
838 YM2151 *chip = (YM2151 *)ptr;
839 timer_adjust_oneshot(chip->timer_A, chip->timer_A_time[ chip->timer_A_index ], 0);
840 chip->timer_A_index_old = chip->timer_A_index;
841 if (chip->irq_enable & 0x04)
842 {
843 chip->status |= 1;
844 timer_set(machine, attotime_zero,chip,0,irqAon_callback);
845 }
846 if (chip->irq_enable & 0x80)
847 chip->csm_req = 2; // request KEY ON / KEY OFF sequence
848 }
849 static TIMER_CALLBACK( timer_callback_b )
850 {
851 YM2151 *chip = (YM2151 *)ptr;
852 timer_adjust_oneshot(chip->timer_B, chip->timer_B_time[ chip->timer_B_index ], 0);
853 chip->timer_B_index_old = chip->timer_B_index;
854 if (chip->irq_enable & 0x08)
855 {
856 chip->status |= 2;
857 timer_set(machine, attotime_zero,chip,0,irqBon_callback);
858 }
859 }*/
860 #if 0
861 static TIMER_CALLBACK( timer_callback_chip_busy )
862 {
863 YM2151 *chip = (YM2151 *)ptr;
864 chip->status &= 0x7f; /* reset busy flag */
865 }
866 #endif
867 #endif
868
869
870
871
872
873
set_connect(YM2151Operator * om1,int cha,int v)874 INLINE void set_connect( YM2151Operator *om1, int cha, int v)
875 {
876 YM2151Operator *om2 = om1+1;
877 YM2151Operator *oc1 = om1+2;
878
879 /* set connect algorithm */
880
881 /* MEM is simply one sample delay */
882
883 switch( v&7 )
884 {
885 case 0:
886 /* M1---C1---MEM---M2---C2---OUT */
887 om1->connect = &c1;
888 oc1->connect = &mem;
889 om2->connect = &c2;
890 om1->mem_connect = &m2;
891 break;
892
893 case 1:
894 /* M1------+-MEM---M2---C2---OUT */
895 /* C1-+ */
896 om1->connect = &mem;
897 oc1->connect = &mem;
898 om2->connect = &c2;
899 om1->mem_connect = &m2;
900 break;
901
902 case 2:
903 /* M1-----------------+-C2---OUT */
904 /* C1---MEM---M2-+ */
905 om1->connect = &c2;
906 oc1->connect = &mem;
907 om2->connect = &c2;
908 om1->mem_connect = &m2;
909 break;
910
911 case 3:
912 /* M1---C1---MEM------+-C2---OUT */
913 /* M2-+ */
914 om1->connect = &c1;
915 oc1->connect = &mem;
916 om2->connect = &c2;
917 om1->mem_connect = &c2;
918 break;
919
920 case 4:
921 /* M1---C1-+-OUT */
922 /* M2---C2-+ */
923 /* MEM: not used */
924 om1->connect = &c1;
925 oc1->connect = &chanout[cha];
926 om2->connect = &c2;
927 om1->mem_connect = &mem; /* store it anywhere where it will not be used */
928 break;
929
930 case 5:
931 /* +----C1----+ */
932 /* M1-+-MEM---M2-+-OUT */
933 /* +----C2----+ */
934 om1->connect = 0; /* special mark */
935 oc1->connect = &chanout[cha];
936 om2->connect = &chanout[cha];
937 om1->mem_connect = &m2;
938 break;
939
940 case 6:
941 /* M1---C1-+ */
942 /* M2-+-OUT */
943 /* C2-+ */
944 /* MEM: not used */
945 om1->connect = &c1;
946 oc1->connect = &chanout[cha];
947 om2->connect = &chanout[cha];
948 om1->mem_connect = &mem; /* store it anywhere where it will not be used */
949 break;
950
951 case 7:
952 /* M1-+ */
953 /* C1-+-OUT */
954 /* M2-+ */
955 /* C2-+ */
956 /* MEM: not used*/
957 om1->connect = &chanout[cha];
958 oc1->connect = &chanout[cha];
959 om2->connect = &chanout[cha];
960 om1->mem_connect = &mem; /* store it anywhere where it will not be used */
961 break;
962 }
963 }
964
965
refresh_EG(YM2151Operator * op)966 INLINE void refresh_EG(YM2151Operator * op)
967 {
968 UINT32 kc;
969 UINT32 v;
970
971 kc = op->kc;
972
973 /* v = 32 + 2*RATE + RKS = max 126 */
974
975 v = kc >> op->ks;
976 if ((op->ar+v) < 32+62)
977 {
978 op->eg_sh_ar = eg_rate_shift [op->ar + v ];
979 op->eg_sel_ar = eg_rate_select[op->ar + v ];
980 }
981 else
982 {
983 op->eg_sh_ar = 0;
984 op->eg_sel_ar = 17*RATE_STEPS;
985 }
986 op->eg_sh_d1r = eg_rate_shift [op->d1r + v];
987 op->eg_sel_d1r= eg_rate_select[op->d1r + v];
988 op->eg_sh_d2r = eg_rate_shift [op->d2r + v];
989 op->eg_sel_d2r= eg_rate_select[op->d2r + v];
990 op->eg_sh_rr = eg_rate_shift [op->rr + v];
991 op->eg_sel_rr = eg_rate_select[op->rr + v];
992
993
994 op+=1;
995
996 v = kc >> op->ks;
997 if ((op->ar+v) < 32+62)
998 {
999 op->eg_sh_ar = eg_rate_shift [op->ar + v ];
1000 op->eg_sel_ar = eg_rate_select[op->ar + v ];
1001 }
1002 else
1003 {
1004 op->eg_sh_ar = 0;
1005 op->eg_sel_ar = 17*RATE_STEPS;
1006 }
1007 op->eg_sh_d1r = eg_rate_shift [op->d1r + v];
1008 op->eg_sel_d1r= eg_rate_select[op->d1r + v];
1009 op->eg_sh_d2r = eg_rate_shift [op->d2r + v];
1010 op->eg_sel_d2r= eg_rate_select[op->d2r + v];
1011 op->eg_sh_rr = eg_rate_shift [op->rr + v];
1012 op->eg_sel_rr = eg_rate_select[op->rr + v];
1013
1014 op+=1;
1015
1016 v = kc >> op->ks;
1017 if ((op->ar+v) < 32+62)
1018 {
1019 op->eg_sh_ar = eg_rate_shift [op->ar + v ];
1020 op->eg_sel_ar = eg_rate_select[op->ar + v ];
1021 }
1022 else
1023 {
1024 op->eg_sh_ar = 0;
1025 op->eg_sel_ar = 17*RATE_STEPS;
1026 }
1027 op->eg_sh_d1r = eg_rate_shift [op->d1r + v];
1028 op->eg_sel_d1r= eg_rate_select[op->d1r + v];
1029 op->eg_sh_d2r = eg_rate_shift [op->d2r + v];
1030 op->eg_sel_d2r= eg_rate_select[op->d2r + v];
1031 op->eg_sh_rr = eg_rate_shift [op->rr + v];
1032 op->eg_sel_rr = eg_rate_select[op->rr + v];
1033
1034 op+=1;
1035
1036 v = kc >> op->ks;
1037 if ((op->ar+v) < 32+62)
1038 {
1039 op->eg_sh_ar = eg_rate_shift [op->ar + v ];
1040 op->eg_sel_ar = eg_rate_select[op->ar + v ];
1041 }
1042 else
1043 {
1044 op->eg_sh_ar = 0;
1045 op->eg_sel_ar = 17*RATE_STEPS;
1046 }
1047 op->eg_sh_d1r = eg_rate_shift [op->d1r + v];
1048 op->eg_sel_d1r= eg_rate_select[op->d1r + v];
1049 op->eg_sh_d2r = eg_rate_shift [op->d2r + v];
1050 op->eg_sel_d2r= eg_rate_select[op->d2r + v];
1051 op->eg_sh_rr = eg_rate_shift [op->rr + v];
1052 op->eg_sel_rr = eg_rate_select[op->rr + v];
1053 }
1054
1055
1056 /* write a register on YM2151 chip number 'n' */
ym2151_write_reg(void * _chip,int r,int v)1057 void ym2151_write_reg(void *_chip, int r, int v)
1058 {
1059 YM2151 *chip = (YM2151 *)_chip;
1060 YM2151Operator *op = &chip->oper[ (r&0x07)*4+((r&0x18)>>3) ];
1061
1062 /* adjust bus to 8 bits */
1063 r &= 0xff;
1064 v &= 0xff;
1065
1066 #if 0
1067 /* There is no info on what YM2151 really does when busy flag is set */
1068 if ( chip->status & 0x80 ) return;
1069 timer_set ( attotime_mul(ATTOTIME_IN_HZ(chip->clock), 64), chip, 0, timer_callback_chip_busy);
1070 chip->status |= 0x80; /* set busy flag for 64 chip clock cycles */
1071 #endif
1072
1073 /*if (LOG_CYM_FILE && (cymfile) && (r!=0) )
1074 {
1075 fputc( (unsigned char)r, cymfile );
1076 fputc( (unsigned char)v, cymfile );
1077 }*/
1078
1079
1080 switch(r & 0xe0){
1081 case 0x00:
1082 switch(r){
1083 case 0x01: /* LFO reset(bit 1), Test Register (other bits) */
1084 chip->test = v;
1085 if (v&2) chip->lfo_phase = 0;
1086 break;
1087
1088 case 0x08:
1089 PSG = chip; /* PSG is used in KEY_ON macro */
1090 envelope_KONKOFF(&chip->oper[ (v&7)*4 ], v );
1091 break;
1092
1093 case 0x0f: /* noise mode enable, noise period */
1094 chip->noise = v;
1095 chip->noise_f = chip->noise_tab[ v & 0x1f ];
1096 break;
1097
1098 case 0x10: /* timer A hi */
1099 chip->timer_A_index = (chip->timer_A_index & 0x003) | (v<<2);
1100 break;
1101
1102 case 0x11: /* timer A low */
1103 chip->timer_A_index = (chip->timer_A_index & 0x3fc) | (v & 3);
1104 break;
1105
1106 case 0x12: /* timer B */
1107 chip->timer_B_index = v;
1108 break;
1109
1110 case 0x14: /* CSM, irq flag reset, irq enable, timer start/stop */
1111
1112 chip->irq_enable = v; /* bit 3-timer B, bit 2-timer A, bit 7 - CSM */
1113
1114 if (v&0x10) /* reset timer A irq flag */
1115 {
1116 #ifdef USE_MAME_TIMERS
1117 chip->status &= ~1;
1118 timer_set(chip->device->machine, attotime_zero,chip,0,irqAoff_callback);
1119 #else
1120 int oldstate = chip->status & 3;
1121 chip->status &= ~1;
1122 //if ((oldstate==1) && (chip->irqhandler)) (*chip->irqhandler)(chip->device, 0);
1123 #endif
1124 }
1125
1126 if (v&0x20) /* reset timer B irq flag */
1127 {
1128 #ifdef USE_MAME_TIMERS
1129 chip->status &= ~2;
1130 timer_set(chip->device->machine, attotime_zero,chip,0,irqBoff_callback);
1131 #else
1132 int oldstate = chip->status & 3;
1133 chip->status &= ~2;
1134 //if ((oldstate==2) && (chip->irqhandler)) (*chip->irqhandler)(chip->device, 0);
1135 #endif
1136 }
1137
1138 if (v&0x02){ /* load and start timer B */
1139 #ifdef USE_MAME_TIMERS
1140 /* ASG 980324: added a real timer */
1141 /* start timer _only_ if it wasn't already started (it will reload time value next round) */
1142 if (!timer_enable(chip->timer_B, 1))
1143 {
1144 timer_adjust_oneshot(chip->timer_B, chip->timer_B_time[ chip->timer_B_index ], 0);
1145 chip->timer_B_index_old = chip->timer_B_index;
1146 }
1147 #else
1148 if (!chip->tim_B)
1149 {
1150 chip->tim_B = 1;
1151 chip->tim_B_val = chip->tim_B_tab[ chip->timer_B_index ];
1152 }
1153 #endif
1154 }else{ /* stop timer B */
1155 #ifdef USE_MAME_TIMERS
1156 /* ASG 980324: added a real timer */
1157 timer_enable(chip->timer_B, 0);
1158 #else
1159 chip->tim_B = 0;
1160 #endif
1161 }
1162
1163 if (v&0x01){ /* load and start timer A */
1164 #ifdef USE_MAME_TIMERS
1165 /* ASG 980324: added a real timer */
1166 /* start timer _only_ if it wasn't already started (it will reload time value next round) */
1167 if (!timer_enable(chip->timer_A, 1))
1168 {
1169 timer_adjust_oneshot(chip->timer_A, chip->timer_A_time[ chip->timer_A_index ], 0);
1170 chip->timer_A_index_old = chip->timer_A_index;
1171 }
1172 #else
1173 if (!chip->tim_A)
1174 {
1175 chip->tim_A = 1;
1176 chip->tim_A_val = chip->tim_A_tab[ chip->timer_A_index ];
1177 }
1178 #endif
1179 }else{ /* stop timer A */
1180 #ifdef USE_MAME_TIMERS
1181 /* ASG 980324: added a real timer */
1182 timer_enable(chip->timer_A, 0);
1183 #else
1184 chip->tim_A = 0;
1185 #endif
1186 }
1187 break;
1188
1189 case 0x18: /* LFO frequency */
1190 {
1191 chip->lfo_overflow = ( 1 << ((15-(v>>4))+3) ) * (1<<LFO_SH);
1192 chip->lfo_counter_add = 0x10 + (v & 0x0f);
1193 }
1194 break;
1195
1196 case 0x19: /* PMD (bit 7==1) or AMD (bit 7==0) */
1197 if (v&0x80)
1198 chip->pmd = v & 0x7f;
1199 else
1200 chip->amd = v & 0x7f;
1201 break;
1202
1203 case 0x1b: /* CT2, CT1, LFO waveform */
1204 chip->ct = v >> 6;
1205 chip->lfo_wsel = v & 3;
1206 //if (chip->porthandler) (*chip->porthandler)(chip->device, 0 , chip->ct );
1207 break;
1208
1209 default:
1210 #ifdef _DEBUG
1211 //logerror("YM2151 Write %02x to undocumented register #%02x\n",v,r);
1212 #endif
1213 break;
1214 }
1215 break;
1216
1217 case 0x20:
1218 op = &chip->oper[ (r&7) * 4 ];
1219 switch(r & 0x18){
1220 case 0x00: /* RL enable, Feedback, Connection */
1221 op->fb_shift = ((v>>3)&7) ? ((v>>3)&7)+6:0;
1222 chip->pan[ (r&7)*2 ] = (v & 0x40) ? ~0 : 0;
1223 chip->pan[ (r&7)*2 +1 ] = (v & 0x80) ? ~0 : 0;
1224 chip->connect[r&7] = v&7;
1225 set_connect(op, r&7, v&7);
1226 break;
1227
1228 case 0x08: /* Key Code */
1229 v &= 0x7f;
1230 if (v != op->kc)
1231 {
1232 UINT32 kc, kc_channel;
1233
1234 kc_channel = (v - (v>>2))*64;
1235 kc_channel += 768;
1236 kc_channel |= (op->kc_i & 63);
1237
1238 (op+0)->kc = v;
1239 (op+0)->kc_i = kc_channel;
1240 (op+1)->kc = v;
1241 (op+1)->kc_i = kc_channel;
1242 (op+2)->kc = v;
1243 (op+2)->kc_i = kc_channel;
1244 (op+3)->kc = v;
1245 (op+3)->kc_i = kc_channel;
1246
1247 kc = v>>2;
1248
1249 (op+0)->dt1 = chip->dt1_freq[ (op+0)->dt1_i + kc ];
1250 (op+0)->freq = ( (chip->freq[ kc_channel + (op+0)->dt2 ] + (op+0)->dt1) * (op+0)->mul ) >> 1;
1251
1252 (op+1)->dt1 = chip->dt1_freq[ (op+1)->dt1_i + kc ];
1253 (op+1)->freq = ( (chip->freq[ kc_channel + (op+1)->dt2 ] + (op+1)->dt1) * (op+1)->mul ) >> 1;
1254
1255 (op+2)->dt1 = chip->dt1_freq[ (op+2)->dt1_i + kc ];
1256 (op+2)->freq = ( (chip->freq[ kc_channel + (op+2)->dt2 ] + (op+2)->dt1) * (op+2)->mul ) >> 1;
1257
1258 (op+3)->dt1 = chip->dt1_freq[ (op+3)->dt1_i + kc ];
1259 (op+3)->freq = ( (chip->freq[ kc_channel + (op+3)->dt2 ] + (op+3)->dt1) * (op+3)->mul ) >> 1;
1260
1261 refresh_EG( op );
1262 }
1263 break;
1264
1265 case 0x10: /* Key Fraction */
1266 v >>= 2;
1267 if (v != (op->kc_i & 63))
1268 {
1269 UINT32 kc_channel;
1270
1271 kc_channel = v;
1272 kc_channel |= (op->kc_i & ~63);
1273
1274 (op+0)->kc_i = kc_channel;
1275 (op+1)->kc_i = kc_channel;
1276 (op+2)->kc_i = kc_channel;
1277 (op+3)->kc_i = kc_channel;
1278
1279 (op+0)->freq = ( (chip->freq[ kc_channel + (op+0)->dt2 ] + (op+0)->dt1) * (op+0)->mul ) >> 1;
1280 (op+1)->freq = ( (chip->freq[ kc_channel + (op+1)->dt2 ] + (op+1)->dt1) * (op+1)->mul ) >> 1;
1281 (op+2)->freq = ( (chip->freq[ kc_channel + (op+2)->dt2 ] + (op+2)->dt1) * (op+2)->mul ) >> 1;
1282 (op+3)->freq = ( (chip->freq[ kc_channel + (op+3)->dt2 ] + (op+3)->dt1) * (op+3)->mul ) >> 1;
1283 }
1284 break;
1285
1286 case 0x18: /* PMS, AMS */
1287 op->pms = (v>>4) & 7;
1288 op->ams = (v & 3);
1289 break;
1290 }
1291 break;
1292
1293 case 0x40: /* DT1, MUL */
1294 {
1295 UINT32 olddt1_i = op->dt1_i;
1296 UINT32 oldmul = op->mul;
1297
1298 op->dt1_i = (v&0x70)<<1;
1299 op->mul = (v&0x0f) ? (v&0x0f)<<1: 1;
1300
1301 if (olddt1_i != op->dt1_i)
1302 op->dt1 = chip->dt1_freq[ op->dt1_i + (op->kc>>2) ];
1303
1304 if ( (olddt1_i != op->dt1_i) || (oldmul != op->mul) )
1305 op->freq = ( (chip->freq[ op->kc_i + op->dt2 ] + op->dt1) * op->mul ) >> 1;
1306 }
1307 break;
1308
1309 case 0x60: /* TL */
1310 op->tl = (v&0x7f)<<(ENV_BITS-7); /* 7bit TL */
1311 break;
1312
1313 case 0x80: /* KS, AR */
1314 {
1315 UINT32 oldks = op->ks;
1316 UINT32 oldar = op->ar;
1317
1318 op->ks = 5-(v>>6);
1319 op->ar = (v&0x1f) ? 32 + ((v&0x1f)<<1) : 0;
1320
1321 if ( (op->ar != oldar) || (op->ks != oldks) )
1322 {
1323 if ((op->ar + (op->kc>>op->ks)) < 32+62)
1324 {
1325 op->eg_sh_ar = eg_rate_shift [op->ar + (op->kc>>op->ks) ];
1326 op->eg_sel_ar = eg_rate_select[op->ar + (op->kc>>op->ks) ];
1327 }
1328 else
1329 {
1330 op->eg_sh_ar = 0;
1331 op->eg_sel_ar = 17*RATE_STEPS;
1332 }
1333 }
1334
1335 if (op->ks != oldks)
1336 {
1337 op->eg_sh_d1r = eg_rate_shift [op->d1r + (op->kc>>op->ks) ];
1338 op->eg_sel_d1r= eg_rate_select[op->d1r + (op->kc>>op->ks) ];
1339 op->eg_sh_d2r = eg_rate_shift [op->d2r + (op->kc>>op->ks) ];
1340 op->eg_sel_d2r= eg_rate_select[op->d2r + (op->kc>>op->ks) ];
1341 op->eg_sh_rr = eg_rate_shift [op->rr + (op->kc>>op->ks) ];
1342 op->eg_sel_rr = eg_rate_select[op->rr + (op->kc>>op->ks) ];
1343 }
1344 }
1345 break;
1346
1347 case 0xa0: /* LFO AM enable, D1R */
1348 op->AMmask = (v&0x80) ? ~0 : 0;
1349 op->d1r = (v&0x1f) ? 32 + ((v&0x1f)<<1) : 0;
1350 op->eg_sh_d1r = eg_rate_shift [op->d1r + (op->kc>>op->ks) ];
1351 op->eg_sel_d1r= eg_rate_select[op->d1r + (op->kc>>op->ks) ];
1352 break;
1353
1354 case 0xc0: /* DT2, D2R */
1355 {
1356 UINT32 olddt2 = op->dt2;
1357 op->dt2 = dt2_tab[ v>>6 ];
1358 if (op->dt2 != olddt2)
1359 op->freq = ( (chip->freq[ op->kc_i + op->dt2 ] + op->dt1) * op->mul ) >> 1;
1360 }
1361 op->d2r = (v&0x1f) ? 32 + ((v&0x1f)<<1) : 0;
1362 op->eg_sh_d2r = eg_rate_shift [op->d2r + (op->kc>>op->ks) ];
1363 op->eg_sel_d2r= eg_rate_select[op->d2r + (op->kc>>op->ks) ];
1364 break;
1365
1366 case 0xe0: /* D1L, RR */
1367 op->d1l = d1l_tab[ v>>4 ];
1368 op->rr = 34 + ((v&0x0f)<<2);
1369 op->eg_sh_rr = eg_rate_shift [op->rr + (op->kc>>op->ks) ];
1370 op->eg_sel_rr = eg_rate_select[op->rr + (op->kc>>op->ks) ];
1371 break;
1372 }
1373 }
1374
1375
1376 /*static TIMER_CALLBACK( cymfile_callback )
1377 {
1378 if (cymfile)
1379 fputc( (unsigned char)0, cymfile );
1380 }*/
1381
1382
ym2151_read_status(void * _chip)1383 int ym2151_read_status( void *_chip )
1384 {
1385 YM2151 *chip = (YM2151 *)_chip;
1386 return chip->status;
1387 }
1388
1389
1390
1391 //#ifdef USE_MAME_TIMERS
1392 #if 1 // disabled for now due to crashing with winalloc.c (ERROR_NOT_ENOUGH_MEMORY)
1393 /*
1394 * state save support for MAME
1395 */
1396 //STATE_POSTLOAD( ym2151_postload )
1397 /*void ym2151_postload(void *param)
1398 {
1399 YM2151 *YM2151_chip = (YM2151 *)param;
1400 int j;
1401
1402 for (j=0; j<8; j++)
1403 set_connect(&YM2151_chip->oper[j*4], j, YM2151_chip->connect[j]);
1404 }
1405
1406 static void ym2151_state_save_register( YM2151 *chip, const device_config *device )
1407 {
1408 int j;
1409
1410 // save all 32 operators of chip #i
1411 for (j=0; j<32; j++)
1412 {
1413 YM2151Operator *op;
1414
1415 op = &chip->oper[(j&7)*4+(j>>3)];
1416
1417 state_save_register_device_item(device, j, op->phase);
1418 state_save_register_device_item(device, j, op->freq);
1419 state_save_register_device_item(device, j, op->dt1);
1420 state_save_register_device_item(device, j, op->mul);
1421 state_save_register_device_item(device, j, op->dt1_i);
1422 state_save_register_device_item(device, j, op->dt2);
1423 // operators connection is saved in chip data block
1424 state_save_register_device_item(device, j, op->mem_value);
1425
1426 state_save_register_device_item(device, j, op->fb_shift);
1427 state_save_register_device_item(device, j, op->fb_out_curr);
1428 state_save_register_device_item(device, j, op->fb_out_prev);
1429 state_save_register_device_item(device, j, op->kc);
1430 state_save_register_device_item(device, j, op->kc_i);
1431 state_save_register_device_item(device, j, op->pms);
1432 state_save_register_device_item(device, j, op->ams);
1433 state_save_register_device_item(device, j, op->AMmask);
1434
1435 state_save_register_device_item(device, j, op->state);
1436 state_save_register_device_item(device, j, op->eg_sh_ar);
1437 state_save_register_device_item(device, j, op->eg_sel_ar);
1438 state_save_register_device_item(device, j, op->tl);
1439 state_save_register_device_item(device, j, op->volume);
1440 state_save_register_device_item(device, j, op->eg_sh_d1r);
1441 state_save_register_device_item(device, j, op->eg_sel_d1r);
1442 state_save_register_device_item(device, j, op->d1l);
1443 state_save_register_device_item(device, j, op->eg_sh_d2r);
1444 state_save_register_device_item(device, j, op->eg_sel_d2r);
1445 state_save_register_device_item(device, j, op->eg_sh_rr);
1446 state_save_register_device_item(device, j, op->eg_sel_rr);
1447
1448 state_save_register_device_item(device, j, op->key);
1449 state_save_register_device_item(device, j, op->ks);
1450 state_save_register_device_item(device, j, op->ar);
1451 state_save_register_device_item(device, j, op->d1r);
1452 state_save_register_device_item(device, j, op->d2r);
1453 state_save_register_device_item(device, j, op->rr);
1454
1455 state_save_register_device_item(device, j, op->reserved0);
1456 state_save_register_device_item(device, j, op->reserved1);
1457 }
1458
1459 state_save_register_device_item_array(device, 0, chip->pan);
1460
1461 state_save_register_device_item(device, 0, chip->eg_cnt);
1462 state_save_register_device_item(device, 0, chip->eg_timer);
1463 state_save_register_device_item(device, 0, chip->eg_timer_add);
1464 state_save_register_device_item(device, 0, chip->eg_timer_overflow);
1465
1466 state_save_register_device_item(device, 0, chip->lfo_phase);
1467 state_save_register_device_item(device, 0, chip->lfo_timer);
1468 state_save_register_device_item(device, 0, chip->lfo_timer_add);
1469 state_save_register_device_item(device, 0, chip->lfo_overflow);
1470 state_save_register_device_item(device, 0, chip->lfo_counter);
1471 state_save_register_device_item(device, 0, chip->lfo_counter_add);
1472 state_save_register_device_item(device, 0, chip->lfo_wsel);
1473 state_save_register_device_item(device, 0, chip->amd);
1474 state_save_register_device_item(device, 0, chip->pmd);
1475 state_save_register_device_item(device, 0, chip->lfa);
1476 state_save_register_device_item(device, 0, chip->lfp);
1477
1478 state_save_register_device_item(device, 0, chip->test);
1479 state_save_register_device_item(device, 0, chip->ct);
1480
1481 state_save_register_device_item(device, 0, chip->noise);
1482 state_save_register_device_item(device, 0, chip->noise_rng);
1483 state_save_register_device_item(device, 0, chip->noise_p);
1484 state_save_register_device_item(device, 0, chip->noise_f);
1485
1486 state_save_register_device_item(device, 0, chip->csm_req);
1487 state_save_register_device_item(device, 0, chip->irq_enable);
1488 state_save_register_device_item(device, 0, chip->status);
1489
1490 state_save_register_device_item(device, 0, chip->timer_A_index);
1491 state_save_register_device_item(device, 0, chip->timer_B_index);
1492 state_save_register_device_item(device, 0, chip->timer_A_index_old);
1493 state_save_register_device_item(device, 0, chip->timer_B_index_old);
1494
1495 #ifdef USE_MAME_TIMERS
1496 state_save_register_device_item(device, 0, chip->irqlinestate);
1497 #endif
1498
1499 state_save_register_device_item_array(device, 0, chip->connect);
1500
1501 state_save_register_postload(device->machine, ym2151_postload, chip);
1502 }*/
1503 #else
1504 /*STATE_POSTLOAD( ym2151_postload )
1505 {
1506 }
1507
1508 static void ym2151_state_save_register( YM2151 *chip, const device_config *device )
1509 {
1510 }*/
1511 #endif
1512
1513
1514 /*
1515 * Initialize YM2151 emulator(s).
1516 *
1517 * 'num' is the number of virtual YM2151's to allocate
1518 * 'clock' is the chip clock in Hz
1519 * 'rate' is sampling rate
1520 */
ym2151_init(int clock,int rate)1521 void * ym2151_init(int clock, int rate)
1522 {
1523 YM2151 *PSG;
1524 int chn;
1525
1526 PSG = (YM2151 *)malloc(sizeof(YM2151));
1527 if (PSG == NULL)
1528 return NULL;
1529
1530 memset(PSG, 0, sizeof(YM2151));
1531
1532 //ym2151_state_save_register( PSG, device );
1533
1534 init_tables();
1535
1536 //PSG->device = device;
1537 PSG->clock = clock;
1538 /*rate = clock/64;*/
1539 PSG->sampfreq = rate ? rate : 44100; /* avoid division by 0 in init_chip_tables() */
1540 //PSG->irqhandler = NULL; /* interrupt handler */
1541 //PSG->porthandler = NULL; /* port write handler */
1542 init_chip_tables( PSG );
1543
1544 PSG->lfo_timer_add = (1<<LFO_SH) * (clock/64.0) / PSG->sampfreq;
1545
1546 PSG->eg_timer_add = (1<<EG_SH) * (clock/64.0) / PSG->sampfreq;
1547 PSG->eg_timer_overflow = ( 3 ) * (1<<EG_SH);
1548 /*logerror("YM2151[init] eg_timer_add=%8x eg_timer_overflow=%8x\n", PSG->eg_timer_add, PSG->eg_timer_overflow);*/
1549
1550 #ifdef USE_MAME_TIMERS
1551 /* this must be done _before_ a call to ym2151_reset_chip() */
1552 PSG->timer_A = timer_alloc(device->machine, timer_callback_a, PSG);
1553 PSG->timer_B = timer_alloc(device->machine, timer_callback_b, PSG);
1554 #else
1555 PSG->tim_A = 0;
1556 PSG->tim_B = 0;
1557 #endif
1558 for (chn = 0; chn < 8; chn ++)
1559 PSG->Muted[chn] = 0x00;
1560 //ym2151_reset_chip(PSG);
1561 /*logerror("YM2151[init] clock=%i sampfreq=%i\n", PSG->clock, PSG->sampfreq);*/
1562
1563 /*LOG_CYM_FILE = (options_get_int(mame_options(), OPTION_VGMWRITE) > 0x00);
1564 if (LOG_CYM_FILE)
1565 {
1566 cymfile = fopen("2151_.cym","wb");
1567 if (cymfile)
1568 timer_pulse ( device->machine, ATTOTIME_IN_HZ(60), NULL, 0, cymfile_callback); //110 Hz pulse timer
1569 else
1570 logerror("Could not create file 2151_.cym\n");
1571 }*/
1572
1573 return PSG;
1574 }
1575
1576
1577
ym2151_shutdown(void * _chip)1578 void ym2151_shutdown(void *_chip)
1579 {
1580 YM2151 *chip = (YM2151 *)_chip;
1581
1582 free (chip);
1583
1584 /*if (cymfile)
1585 fclose (cymfile);
1586 cymfile = NULL;*/
1587
1588 #ifdef SAVE_SAMPLE
1589 fclose(sample[8]);
1590 #endif
1591 #ifdef SAVE_SEPARATE_CHANNELS
1592 fclose(sample[0]);
1593 fclose(sample[1]);
1594 fclose(sample[2]);
1595 fclose(sample[3]);
1596 fclose(sample[4]);
1597 fclose(sample[5]);
1598 fclose(sample[6]);
1599 fclose(sample[7]);
1600 #endif
1601 }
1602
1603
1604
1605 /*
1606 * Reset chip number 'n'.
1607 */
ym2151_reset_chip(void * _chip)1608 void ym2151_reset_chip(void *_chip)
1609 {
1610 int i;
1611 YM2151 *chip = (YM2151 *)_chip;
1612
1613
1614 /* initialize hardware registers */
1615 for (i=0; i<32; i++)
1616 {
1617 memset(&chip->oper[i],'\0',sizeof(YM2151Operator));
1618 chip->oper[i].volume = MAX_ATT_INDEX;
1619 chip->oper[i].kc_i = 768; /* min kc_i value */
1620 }
1621
1622 chip->eg_timer = 0;
1623 chip->eg_cnt = 0;
1624
1625 chip->lfo_timer = 0;
1626 chip->lfo_counter= 0;
1627 chip->lfo_phase = 0;
1628 chip->lfo_wsel = 0;
1629 chip->pmd = 0;
1630 chip->amd = 0;
1631 chip->lfa = 0;
1632 chip->lfp = 0;
1633
1634 chip->test= 0;
1635
1636 chip->irq_enable = 0;
1637 #ifdef USE_MAME_TIMERS
1638 /* ASG 980324 -- reset the timers before writing to the registers */
1639 timer_enable(chip->timer_A, 0);
1640 timer_enable(chip->timer_B, 0);
1641 #else
1642 chip->tim_A = 0;
1643 chip->tim_B = 0;
1644 chip->tim_A_val = 0;
1645 chip->tim_B_val = 0;
1646 #endif
1647 chip->timer_A_index = 0;
1648 chip->timer_B_index = 0;
1649 chip->timer_A_index_old = 0;
1650 chip->timer_B_index_old = 0;
1651
1652 chip->noise = 0;
1653 chip->noise_rng = 0;
1654 chip->noise_p = 0;
1655 chip->noise_f = chip->noise_tab[0];
1656
1657 chip->csm_req = 0;
1658 chip->status = 0;
1659
1660 ym2151_write_reg(chip, 0x1b, 0); /* only because of CT1, CT2 output pins */
1661 ym2151_write_reg(chip, 0x18, 0); /* set LFO frequency */
1662 for (i=0x20; i<0x100; i++) /* set the operators */
1663 {
1664 ym2151_write_reg(chip, i, 0);
1665 }
1666 }
1667
1668
1669
op_calc(YM2151Operator * OP,unsigned int env,signed int pm)1670 INLINE signed int op_calc(YM2151Operator * OP, unsigned int env, signed int pm)
1671 {
1672 UINT32 p;
1673
1674
1675 p = (env<<3) + sin_tab[ ( ((signed int)((OP->phase & ~FREQ_MASK) + (pm<<15))) >> FREQ_SH ) & SIN_MASK ];
1676
1677 if (p >= TL_TAB_LEN)
1678 return 0;
1679
1680 return tl_tab[p];
1681 }
1682
op_calc1(YM2151Operator * OP,unsigned int env,signed int pm)1683 INLINE signed int op_calc1(YM2151Operator * OP, unsigned int env, signed int pm)
1684 {
1685 UINT32 p;
1686 INT32 i;
1687
1688
1689 i = (OP->phase & ~FREQ_MASK) + pm;
1690
1691 /*logerror("i=%08x (i>>16)&511=%8i phase=%i [pm=%08x] ",i, (i>>16)&511, OP->phase>>FREQ_SH, pm);*/
1692
1693 p = (env<<3) + sin_tab[ (i>>FREQ_SH) & SIN_MASK];
1694
1695 /*logerror("(p&255=%i p>>8=%i) out= %i\n", p&255,p>>8, tl_tab[p&255]>>(p>>8) );*/
1696
1697 if (p >= TL_TAB_LEN)
1698 return 0;
1699
1700 return tl_tab[p];
1701 }
1702
1703
1704
1705 #define volume_calc(OP) ((OP)->tl + ((UINT32)(OP)->volume) + (AM & (OP)->AMmask))
1706
chan_calc(unsigned int chan)1707 INLINE void chan_calc(unsigned int chan)
1708 {
1709 YM2151Operator *op;
1710 unsigned int env;
1711 UINT32 AM = 0;
1712
1713 if (PSG->Muted[chan])
1714 return;
1715
1716 m2 = c1 = c2 = mem = 0;
1717 op = &PSG->oper[chan*4]; /* M1 */
1718
1719 *op->mem_connect = op->mem_value; /* restore delayed sample (MEM) value to m2 or c2 */
1720
1721 if (op->ams)
1722 AM = PSG->lfa << (op->ams-1);
1723 env = volume_calc(op);
1724 {
1725 INT32 out = op->fb_out_prev + op->fb_out_curr;
1726 op->fb_out_prev = op->fb_out_curr;
1727
1728 if (!op->connect)
1729 /* algorithm 5 */
1730 mem = c1 = c2 = op->fb_out_prev;
1731 else
1732 /* other algorithms */
1733 *op->connect = op->fb_out_prev;
1734
1735 op->fb_out_curr = 0;
1736 if (env < ENV_QUIET)
1737 {
1738 if (!op->fb_shift)
1739 out=0;
1740 op->fb_out_curr = op_calc1(op, env, (out<<op->fb_shift) );
1741 }
1742 }
1743
1744 env = volume_calc(op+1); /* M2 */
1745 if (env < ENV_QUIET)
1746 *(op+1)->connect += op_calc(op+1, env, m2);
1747
1748 env = volume_calc(op+2); /* C1 */
1749 if (env < ENV_QUIET)
1750 *(op+2)->connect += op_calc(op+2, env, c1);
1751
1752 env = volume_calc(op+3); /* C2 */
1753 if (env < ENV_QUIET)
1754 chanout[chan] += op_calc(op+3, env, c2);
1755 if (chanout[chan] > +16384) chanout[chan] = +16384;
1756 else if (chanout[chan] < -16384) chanout[chan] = -16384;
1757
1758 /* M1 */
1759 op->mem_value = mem;
1760 }
chan7_calc(void)1761 INLINE void chan7_calc(void)
1762 {
1763 YM2151Operator *op;
1764 unsigned int env;
1765 UINT32 AM = 0;
1766
1767 if (PSG->Muted[7])
1768 return;
1769
1770 m2 = c1 = c2 = mem = 0;
1771 op = &PSG->oper[7*4]; /* M1 */
1772
1773 *op->mem_connect = op->mem_value; /* restore delayed sample (MEM) value to m2 or c2 */
1774
1775 if (op->ams)
1776 AM = PSG->lfa << (op->ams-1);
1777 env = volume_calc(op);
1778 {
1779 INT32 out = op->fb_out_prev + op->fb_out_curr;
1780 op->fb_out_prev = op->fb_out_curr;
1781
1782 if (!op->connect)
1783 /* algorithm 5 */
1784 mem = c1 = c2 = op->fb_out_prev;
1785 else
1786 /* other algorithms */
1787 *op->connect = op->fb_out_prev;
1788
1789 op->fb_out_curr = 0;
1790 if (env < ENV_QUIET)
1791 {
1792 if (!op->fb_shift)
1793 out=0;
1794 op->fb_out_curr = op_calc1(op, env, (out<<op->fb_shift) );
1795 }
1796 }
1797
1798 env = volume_calc(op+1); /* M2 */
1799 if (env < ENV_QUIET)
1800 *(op+1)->connect += op_calc(op+1, env, m2);
1801
1802 env = volume_calc(op+2); /* C1 */
1803 if (env < ENV_QUIET)
1804 *(op+2)->connect += op_calc(op+2, env, c1);
1805
1806 env = volume_calc(op+3); /* C2 */
1807 if (PSG->noise & 0x80)
1808 {
1809 INT32 noiseout;
1810
1811 noiseout = 0;
1812 if (env < 0x3ff)
1813 noiseout = (env ^ 0x3ff) * 2; /* range of the YM2151 noise output is -2044 to 2040 */
1814 chanout[7] += ((PSG->noise_rng&0x10000) ? noiseout: -noiseout); /* bit 16 -> output */
1815 }
1816 else
1817 {
1818 if (env < ENV_QUIET)
1819 chanout[7] += op_calc(op+3, env, c2);
1820 }
1821 if (chanout[7] > +16384) chanout[7] = +16384;
1822 else if (chanout[7] < -16384) chanout[7] = -16384;
1823 /* M1 */
1824 op->mem_value = mem;
1825 }
1826
1827
1828
1829
1830
1831
1832 /*
1833 The 'rate' is calculated from following formula (example on decay rate):
1834 rks = notecode after key scaling (a value from 0 to 31)
1835 DR = value written to the chip register
1836 rate = 2*DR + rks; (max rate = 2*31+31 = 93)
1837 Four MSBs of the 'rate' above are the 'main' rate (from 00 to 15)
1838 Two LSBs of the 'rate' above are the value 'x' (the shape type).
1839 (eg. '11 2' means that 'rate' is 11*4+2=46)
1840
1841 NOTE: A 'sample' in the description below is actually 3 output samples,
1842 thats because the Envelope Generator clock is equal to internal_clock/3.
1843
1844 Single '-' (minus) character in the diagrams below represents one sample
1845 on the output; this is for rates 11 x (11 0, 11 1, 11 2 and 11 3)
1846
1847 these 'main' rates:
1848 00 x: single '-' = 2048 samples; (ie. level can change every 2048 samples)
1849 01 x: single '-' = 1024 samples;
1850 02 x: single '-' = 512 samples;
1851 03 x: single '-' = 256 samples;
1852 04 x: single '-' = 128 samples;
1853 05 x: single '-' = 64 samples;
1854 06 x: single '-' = 32 samples;
1855 07 x: single '-' = 16 samples;
1856 08 x: single '-' = 8 samples;
1857 09 x: single '-' = 4 samples;
1858 10 x: single '-' = 2 samples;
1859 11 x: single '-' = 1 sample; (ie. level can change every 1 sample)
1860
1861 Shapes for rates 11 x look like this:
1862 rate: step:
1863 11 0 01234567
1864
1865 level:
1866 0 --
1867 1 --
1868 2 --
1869 3 --
1870
1871 rate: step:
1872 11 1 01234567
1873
1874 level:
1875 0 --
1876 1 --
1877 2 -
1878 3 -
1879 4 --
1880
1881 rate: step:
1882 11 2 01234567
1883
1884 level:
1885 0 --
1886 1 -
1887 2 -
1888 3 --
1889 4 -
1890 5 -
1891
1892 rate: step:
1893 11 3 01234567
1894
1895 level:
1896 0 --
1897 1 -
1898 2 -
1899 3 -
1900 4 -
1901 5 -
1902 6 -
1903
1904
1905 For rates 12 x, 13 x, 14 x and 15 x output level changes on every
1906 sample - this means that the waveform looks like this: (but the level
1907 changes by different values on different steps)
1908 12 3 01234567
1909
1910 0 -
1911 2 -
1912 4 -
1913 8 -
1914 10 -
1915 12 -
1916 14 -
1917 18 -
1918 20 -
1919
1920 Notes about the timing:
1921 ----------------------
1922
1923 1. Synchronism
1924
1925 Output level of each two (or more) voices running at the same 'main' rate
1926 (eg 11 0 and 11 1 in the diagram below) will always be changing in sync,
1927 even if there're started with some delay.
1928
1929 Note that, in the diagram below, the decay phase in channel 0 starts at
1930 sample #2, while in channel 1 it starts at sample #6. Anyway, both channels
1931 will always change their levels at exactly the same (following) samples.
1932
1933 (S - start point of this channel, A-attack phase, D-decay phase):
1934
1935 step:
1936 01234567012345670123456
1937
1938 channel 0:
1939 --
1940 | --
1941 | -
1942 | -
1943 | --
1944 | --
1945 | --
1946 | -
1947 | -
1948 | --
1949 AADDDDDDDDDDDDDDDD
1950 S
1951
1952 01234567012345670123456
1953 channel 1:
1954 -
1955 | -
1956 | --
1957 | --
1958 | --
1959 | -
1960 | -
1961 | --
1962 | --
1963 | --
1964 AADDDDDDDDDDDDDDDD
1965 S
1966 01234567012345670123456
1967
1968
1969 2. Shifted (delayed) synchronism
1970
1971 Output of each two (or more) voices running at different 'main' rate
1972 (9 1, 10 1 and 11 1 in the diagrams below) will always be changing
1973 in 'delayed-sync' (even if there're started with some delay as in "1.")
1974
1975 Note that the shapes are delayed by exactly one sample per one 'main' rate
1976 increment. (Normally one would expect them to start at the same samples.)
1977
1978 See diagram below (* - start point of the shape).
1979
1980 cycle:
1981 0123456701234567012345670123456701234567012345670123456701234567
1982
1983 rate 09 1
1984 *-------
1985 --------
1986 ----
1987 ----
1988 --------
1989 *-------
1990 | --------
1991 | ----
1992 | ----
1993 | --------
1994 rate 10 1 |
1995 -- |
1996 *--- |
1997 ---- |
1998 -- |
1999 -- |
2000 ---- |
2001 *--- |
2002 | ---- |
2003 | -- | | <- one step (two samples) delay between 9 1 and 10 1
2004 | -- | |
2005 | ----|
2006 | *---
2007 | ----
2008 | --
2009 | --
2010 | ----
2011 rate 11 1 |
2012 - |
2013 -- |
2014 *- |
2015 -- |
2016 - |
2017 - |
2018 -- |
2019 *- |
2020 -- |
2021 - || <- one step (one sample) delay between 10 1 and 11 1
2022 - ||
2023 --|
2024 *-
2025 --
2026 -
2027 -
2028 --
2029 *-
2030 --
2031 -
2032 -
2033 --
2034 */
2035
advance_eg(void)2036 INLINE void advance_eg(void)
2037 {
2038 YM2151Operator *op;
2039 unsigned int i;
2040
2041
2042
2043 PSG->eg_timer += PSG->eg_timer_add;
2044
2045 while (PSG->eg_timer >= PSG->eg_timer_overflow)
2046 {
2047 PSG->eg_timer -= PSG->eg_timer_overflow;
2048
2049 PSG->eg_cnt++;
2050
2051 /* envelope generator */
2052 op = &PSG->oper[0]; /* CH 0 M1 */
2053 i = 32;
2054 do
2055 {
2056 switch(op->state)
2057 {
2058 case EG_ATT: /* attack phase */
2059 if ( !(PSG->eg_cnt & ((1<<op->eg_sh_ar)-1) ) )
2060 {
2061 op->volume += (~op->volume *
2062 (eg_inc[op->eg_sel_ar + ((PSG->eg_cnt>>op->eg_sh_ar)&7)])
2063 ) >>4;
2064
2065 if (op->volume <= MIN_ATT_INDEX)
2066 {
2067 op->volume = MIN_ATT_INDEX;
2068 op->state = EG_DEC;
2069 }
2070
2071 }
2072 break;
2073
2074 case EG_DEC: /* decay phase */
2075 if ( !(PSG->eg_cnt & ((1<<op->eg_sh_d1r)-1) ) )
2076 {
2077 op->volume += eg_inc[op->eg_sel_d1r + ((PSG->eg_cnt>>op->eg_sh_d1r)&7)];
2078
2079 if ( op->volume >= op->d1l )
2080 op->state = EG_SUS;
2081
2082 }
2083 break;
2084
2085 case EG_SUS: /* sustain phase */
2086 if ( !(PSG->eg_cnt & ((1<<op->eg_sh_d2r)-1) ) )
2087 {
2088 op->volume += eg_inc[op->eg_sel_d2r + ((PSG->eg_cnt>>op->eg_sh_d2r)&7)];
2089
2090 if ( op->volume >= MAX_ATT_INDEX )
2091 {
2092 op->volume = MAX_ATT_INDEX;
2093 op->state = EG_OFF;
2094 }
2095
2096 }
2097 break;
2098
2099 case EG_REL: /* release phase */
2100 if ( !(PSG->eg_cnt & ((1<<op->eg_sh_rr)-1) ) )
2101 {
2102 op->volume += eg_inc[op->eg_sel_rr + ((PSG->eg_cnt>>op->eg_sh_rr)&7)];
2103
2104 if ( op->volume >= MAX_ATT_INDEX )
2105 {
2106 op->volume = MAX_ATT_INDEX;
2107 op->state = EG_OFF;
2108 }
2109
2110 }
2111 break;
2112 }
2113 op++;
2114 i--;
2115 }while (i);
2116 }
2117 }
2118
2119
advance(void)2120 INLINE void advance(void)
2121 {
2122 YM2151Operator *op;
2123 unsigned int i;
2124 int a,p;
2125
2126 /* LFO */
2127 if (PSG->test&2)
2128 PSG->lfo_phase = 0;
2129 else
2130 {
2131 PSG->lfo_timer += PSG->lfo_timer_add;
2132 if (PSG->lfo_timer >= PSG->lfo_overflow)
2133 {
2134 PSG->lfo_timer -= PSG->lfo_overflow;
2135 PSG->lfo_counter += PSG->lfo_counter_add;
2136 PSG->lfo_phase += (PSG->lfo_counter>>4);
2137 PSG->lfo_phase &= 255;
2138 PSG->lfo_counter &= 15;
2139 }
2140 }
2141
2142 i = PSG->lfo_phase;
2143 /* calculate LFO AM and PM waveform value (all verified on real chip, except for noise algorithm which is impossible to analyse)*/
2144 switch (PSG->lfo_wsel)
2145 {
2146 case 0:
2147 /* saw */
2148 /* AM: 255 down to 0 */
2149 /* PM: 0 to 127, -127 to 0 (at PMD=127: LFP = 0 to 126, -126 to 0) */
2150 a = 255 - i;
2151 if (i<128)
2152 p = i;
2153 else
2154 p = i - 255;
2155 break;
2156 case 1:
2157 /* square */
2158 /* AM: 255, 0 */
2159 /* PM: 128,-128 (LFP = exactly +PMD, -PMD) */
2160 if (i<128){
2161 a = 255;
2162 p = 128;
2163 }else{
2164 a = 0;
2165 p = -128;
2166 }
2167 break;
2168 case 2:
2169 /* triangle */
2170 /* AM: 255 down to 1 step -2; 0 up to 254 step +2 */
2171 /* PM: 0 to 126 step +2, 127 to 1 step -2, 0 to -126 step -2, -127 to -1 step +2*/
2172 if (i<128)
2173 a = 255 - (i*2);
2174 else
2175 a = (i*2) - 256;
2176
2177 if (i<64) /* i = 0..63 */
2178 p = i*2; /* 0 to 126 step +2 */
2179 else if (i<128) /* i = 64..127 */
2180 p = 255 - i*2; /* 127 to 1 step -2 */
2181 else if (i<192) /* i = 128..191 */
2182 p = 256 - i*2; /* 0 to -126 step -2*/
2183 else /* i = 192..255 */
2184 p = i*2 - 511; /*-127 to -1 step +2*/
2185 break;
2186 case 3:
2187 default: /*keep the compiler happy*/
2188 /* random */
2189 /* the real algorithm is unknown !!!
2190 We just use a snapshot of data from real chip */
2191
2192 /* AM: range 0 to 255 */
2193 /* PM: range -128 to 127 */
2194
2195 a = lfo_noise_waveform[i];
2196 p = a-128;
2197 break;
2198 }
2199 PSG->lfa = a * PSG->amd / 128;
2200 PSG->lfp = p * PSG->pmd / 128;
2201
2202
2203 /* The Noise Generator of the YM2151 is 17-bit shift register.
2204 * Input to the bit16 is negated (bit0 XOR bit3) (EXNOR).
2205 * Output of the register is negated (bit0 XOR bit3).
2206 * Simply use bit16 as the noise output.
2207 */
2208 PSG->noise_p += PSG->noise_f;
2209 i = (PSG->noise_p>>16); /* number of events (shifts of the shift register) */
2210 PSG->noise_p &= 0xffff;
2211 while (i)
2212 {
2213 UINT32 j;
2214 j = ( (PSG->noise_rng ^ (PSG->noise_rng>>3) ) & 1) ^ 1;
2215 PSG->noise_rng = (j<<16) | (PSG->noise_rng>>1);
2216 i--;
2217 }
2218
2219
2220 /* phase generator */
2221 op = &PSG->oper[0]; /* CH 0 M1 */
2222 i = 8;
2223 do
2224 {
2225 if (op->pms) /* only when phase modulation from LFO is enabled for this channel */
2226 {
2227 INT32 mod_ind = PSG->lfp; /* -128..+127 (8bits signed) */
2228 if (op->pms < 6)
2229 mod_ind >>= (6 - op->pms);
2230 else
2231 mod_ind <<= (op->pms - 5);
2232
2233 if (mod_ind)
2234 {
2235 UINT32 kc_channel = op->kc_i + mod_ind;
2236 (op+0)->phase += ( (PSG->freq[ kc_channel + (op+0)->dt2 ] + (op+0)->dt1) * (op+0)->mul ) >> 1;
2237 (op+1)->phase += ( (PSG->freq[ kc_channel + (op+1)->dt2 ] + (op+1)->dt1) * (op+1)->mul ) >> 1;
2238 (op+2)->phase += ( (PSG->freq[ kc_channel + (op+2)->dt2 ] + (op+2)->dt1) * (op+2)->mul ) >> 1;
2239 (op+3)->phase += ( (PSG->freq[ kc_channel + (op+3)->dt2 ] + (op+3)->dt1) * (op+3)->mul ) >> 1;
2240 }
2241 else /* phase modulation from LFO is equal to zero */
2242 {
2243 (op+0)->phase += (op+0)->freq;
2244 (op+1)->phase += (op+1)->freq;
2245 (op+2)->phase += (op+2)->freq;
2246 (op+3)->phase += (op+3)->freq;
2247 }
2248 }
2249 else /* phase modulation from LFO is disabled */
2250 {
2251 (op+0)->phase += (op+0)->freq;
2252 (op+1)->phase += (op+1)->freq;
2253 (op+2)->phase += (op+2)->freq;
2254 (op+3)->phase += (op+3)->freq;
2255 }
2256
2257 op+=4;
2258 i--;
2259 }while (i);
2260
2261
2262 /* CSM is calculated *after* the phase generator calculations (verified on real chip)
2263 * CSM keyon line seems to be ORed with the KO line inside of the chip.
2264 * The result is that it only works when KO (register 0x08) is off, ie. 0
2265 *
2266 * Interesting effect is that when timer A is set to 1023, the KEY ON happens
2267 * on every sample, so there is no KEY OFF at all - the result is that
2268 * the sound played is the same as after normal KEY ON.
2269 */
2270
2271 if (PSG->csm_req) /* CSM KEYON/KEYOFF seqeunce request */
2272 {
2273 if (PSG->csm_req==2) /* KEY ON */
2274 {
2275 op = &PSG->oper[0]; /* CH 0 M1 */
2276 i = 32;
2277 do
2278 {
2279 KEY_ON(op, 2);
2280 op++;
2281 i--;
2282 }while (i);
2283 PSG->csm_req = 1;
2284 }
2285 else /* KEY OFF */
2286 {
2287 op = &PSG->oper[0]; /* CH 0 M1 */
2288 i = 32;
2289 do
2290 {
2291 KEY_OFF(op,~2);
2292 op++;
2293 i--;
2294 }while (i);
2295 PSG->csm_req = 0;
2296 }
2297 }
2298 }
2299
2300 #if 0
2301 INLINE signed int acc_calc(signed int value)
2302 {
2303 if (value>=0)
2304 {
2305 if (value < 0x0200)
2306 return (value & ~0);
2307 if (value < 0x0400)
2308 return (value & ~1);
2309 if (value < 0x0800)
2310 return (value & ~3);
2311 if (value < 0x1000)
2312 return (value & ~7);
2313 if (value < 0x2000)
2314 return (value & ~15);
2315 if (value < 0x4000)
2316 return (value & ~31);
2317 return (value & ~63);
2318 }
2319 /*else value < 0*/
2320 if (value > -0x0200)
2321 return (~abs(value) & ~0);
2322 if (value > -0x0400)
2323 return (~abs(value) & ~1);
2324 if (value > -0x0800)
2325 return (~abs(value) & ~3);
2326 if (value > -0x1000)
2327 return (~abs(value) & ~7);
2328 if (value > -0x2000)
2329 return (~abs(value) & ~15);
2330 if (value > -0x4000)
2331 return (~abs(value) & ~31);
2332 return (~abs(value) & ~63);
2333 }
2334 #endif
2335
2336 /* first macro saves left and right channels to mono file */
2337 /* second macro saves left and right channels to stereo file */
2338 #if 0 /*MONO*/
2339 #ifdef SAVE_SEPARATE_CHANNELS
2340 #define SAVE_SINGLE_CHANNEL(j) \
2341 { signed int pom= -(chanout[j] & PSG->pan[j*2]); \
2342 if (pom > 32767) pom = 32767; else if (pom < -32768) pom = -32768; \
2343 fputc((unsigned short)pom&0xff,sample[j]); \
2344 fputc(((unsigned short)pom>>8)&0xff,sample[j]); \
2345 }
2346 #else
2347 #define SAVE_SINGLE_CHANNEL(j)
2348 #endif
2349 #else /*STEREO*/
2350 #ifdef SAVE_SEPARATE_CHANNELS
2351 #define SAVE_SINGLE_CHANNEL(j) \
2352 { signed int pom = -(chanout[j] & PSG->pan[j*2]); \
2353 if (pom > 32767) pom = 32767; else if (pom < -32768) pom = -32768; \
2354 fputc((unsigned short)pom&0xff,sample[j]); \
2355 fputc(((unsigned short)pom>>8)&0xff,sample[j]); \
2356 pom = -(chanout[j] & PSG->pan[j*2+1]); \
2357 if (pom > 32767) pom = 32767; else if (pom < -32768) pom = -32768; \
2358 fputc((unsigned short)pom&0xff,sample[j]); \
2359 fputc(((unsigned short)pom>>8)&0xff,sample[j]); \
2360 }
2361 #else
2362 #define SAVE_SINGLE_CHANNEL(j)
2363 #endif
2364 #endif
2365
2366 /* first macro saves left and right channels to mono file */
2367 /* second macro saves left and right channels to stereo file */
2368 #if 1 /*MONO*/
2369 #ifdef SAVE_SAMPLE
2370 #define SAVE_ALL_CHANNELS \
2371 { signed int pom = outl; \
2372 /*pom = acc_calc(pom);*/ \
2373 /*fprintf(sample[8]," %i\n",pom);*/ \
2374 fputc((unsigned short)pom&0xff,sample[8]); \
2375 fputc(((unsigned short)pom>>8)&0xff,sample[8]); \
2376 }
2377 #else
2378 #define SAVE_ALL_CHANNELS
2379 #endif
2380 #else /*STEREO*/
2381 #ifdef SAVE_SAMPLE
2382 #define SAVE_ALL_CHANNELS \
2383 { signed int pom = outl; \
2384 fputc((unsigned short)pom&0xff,sample[8]); \
2385 fputc(((unsigned short)pom>>8)&0xff,sample[8]); \
2386 pom = outr; \
2387 fputc((unsigned short)pom&0xff,sample[8]); \
2388 fputc(((unsigned short)pom>>8)&0xff,sample[8]); \
2389 }
2390 #else
2391 #define SAVE_ALL_CHANNELS
2392 #endif
2393 #endif
2394
2395
2396 /* Generate samples for one of the YM2151's
2397 *
2398 * 'num' is the number of virtual YM2151
2399 * '**buffers' is table of pointers to the buffers: left and right
2400 * 'length' is the number of samples that should be generated
2401 */
ym2151_update_one(void * chip,SAMP ** buffers,int length)2402 void ym2151_update_one(void *chip, SAMP **buffers, int length)
2403 {
2404 int i, chn;
2405 signed int outl,outr;
2406 SAMP *bufL, *bufR;
2407
2408 bufL = buffers[0];
2409 bufR = buffers[1];
2410
2411 PSG = (YM2151 *)chip;
2412
2413 #ifdef USE_MAME_TIMERS
2414 /* ASG 980324 - handled by real timers now */
2415 #else
2416 if (PSG->tim_B)
2417 {
2418 PSG->tim_B_val -= ( length << TIMER_SH );
2419 if (PSG->tim_B_val<=0)
2420 {
2421 PSG->tim_B_val += PSG->tim_B_tab[ PSG->timer_B_index ];
2422 if ( PSG->irq_enable & 0x08 )
2423 {
2424 int oldstate = PSG->status & 3;
2425 PSG->status |= 2;
2426 //if ((!oldstate) && (PSG->irqhandler)) (*PSG->irqhandler)(chip->device, 1);
2427 }
2428 }
2429 }
2430 #endif
2431
2432 for (i=0; i<length; i++)
2433 {
2434 advance_eg();
2435
2436 chanout[0] = 0;
2437 chanout[1] = 0;
2438 chanout[2] = 0;
2439 chanout[3] = 0;
2440 chanout[4] = 0;
2441 chanout[5] = 0;
2442 chanout[6] = 0;
2443 chanout[7] = 0;
2444
2445 chan_calc(0);
2446 SAVE_SINGLE_CHANNEL(0)
2447 chan_calc(1);
2448 SAVE_SINGLE_CHANNEL(1)
2449 chan_calc(2);
2450 SAVE_SINGLE_CHANNEL(2)
2451 chan_calc(3);
2452 SAVE_SINGLE_CHANNEL(3)
2453 chan_calc(4);
2454 SAVE_SINGLE_CHANNEL(4)
2455 chan_calc(5);
2456 SAVE_SINGLE_CHANNEL(5)
2457 chan_calc(6);
2458 SAVE_SINGLE_CHANNEL(6)
2459 chan7_calc();
2460 SAVE_SINGLE_CHANNEL(7)
2461
2462 outl = chanout[0] & PSG->pan[0];
2463 outr = chanout[0] & PSG->pan[1];
2464 outl += (chanout[1] & PSG->pan[2]);
2465 outr += (chanout[1] & PSG->pan[3]);
2466 outl += (chanout[2] & PSG->pan[4]);
2467 outr += (chanout[2] & PSG->pan[5]);
2468 outl += (chanout[3] & PSG->pan[6]);
2469 outr += (chanout[3] & PSG->pan[7]);
2470 outl += (chanout[4] & PSG->pan[8]);
2471 outr += (chanout[4] & PSG->pan[9]);
2472 outl += (chanout[5] & PSG->pan[10]);
2473 outr += (chanout[5] & PSG->pan[11]);
2474 outl += (chanout[6] & PSG->pan[12]);
2475 outr += (chanout[6] & PSG->pan[13]);
2476 outl += (chanout[7] & PSG->pan[14]);
2477 outr += (chanout[7] & PSG->pan[15]);
2478
2479 outl >>= FINAL_SH;
2480 outr >>= FINAL_SH;
2481 //if (outl > MAXOUT) outl = MAXOUT;
2482 // else if (outl < MINOUT) outl = MINOUT;
2483 //if (outr > MAXOUT) outr = MAXOUT;
2484 // else if (outr < MINOUT) outr = MINOUT;
2485 ((SAMP*)bufL)[i] = (SAMP)outl;
2486 ((SAMP*)bufR)[i] = (SAMP)outr;
2487
2488 SAVE_ALL_CHANNELS
2489
2490 #ifdef USE_MAME_TIMERS
2491 /* ASG 980324 - handled by real timers now */
2492 #else
2493 /* calculate timer A */
2494 if (PSG->tim_A)
2495 {
2496 PSG->tim_A_val -= ( 1 << TIMER_SH );
2497 if (PSG->tim_A_val <= 0)
2498 {
2499 PSG->tim_A_val += PSG->tim_A_tab[ PSG->timer_A_index ];
2500 if (PSG->irq_enable & 0x04)
2501 {
2502 int oldstate = PSG->status & 3;
2503 PSG->status |= 1;
2504 //if ((!oldstate) && (PSG->irqhandler)) (*PSG->irqhandler)(chip->device, 1);
2505 }
2506 if (PSG->irq_enable & 0x80)
2507 PSG->csm_req = 2; /* request KEY ON / KEY OFF sequence */
2508 }
2509 }
2510 #endif
2511 advance();
2512 }
2513 }
2514
2515 /*void ym2151_set_irq_handler(void *chip, void(*handler)(int irq))
2516 {
2517 YM2151 *PSG = (YM2151 *)chip;
2518 PSG->irqhandler = handler;
2519 }
2520
2521 void ym2151_set_port_write_handler(void *chip, write8_device_func handler)
2522 {
2523 YM2151 *PSG = (YM2151 *)chip;
2524 PSG->porthandler = handler;
2525 }*/
2526
ym2151_set_mutemask(void * chip,UINT32 MuteMask)2527 void ym2151_set_mutemask(void *chip, UINT32 MuteMask)
2528 {
2529 YM2151 *PSG = (YM2151 *)chip;
2530 UINT8 CurChn;
2531
2532 for (CurChn = 0; CurChn < 8; CurChn ++)
2533 PSG->Muted[CurChn] = (MuteMask >> CurChn) & 0x01;
2534
2535 return;
2536 }
2537
2538