1 /*
2 * Copyright (C) 2017-2018 Alexey Khokholov (Nuke.YKT)
3 *
4 * This library is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU Lesser General Public
6 * License as published by the Free Software Foundation; either
7 * version 2.1 of the License, or (at your option) any later version.
8 *
9 * This library is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * Lesser General Public License for more details.
13 *
14 * You should have received a copy of the GNU Lesser General Public
15 * License along with this library; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
17 *
18 *
19 * Nuked OPN2(Yamaha YM3438) emulator.
20 * Thanks:
21 * Silicon Pr0n:
22 * Yamaha YM3438 decap and die shot(digshadow).
23 * OPLx decapsulated(Matthew Gambrell, Olli Niemitalo):
24 * OPL2 ROMs.
25 *
26 * version: 1.0.9
27 */
28
29 #include <string.h>
30 #include "ym3438.h"
31
32 enum {
33 eg_num_attack = 0,
34 eg_num_decay = 1,
35 eg_num_sustain = 2,
36 eg_num_release = 3
37 };
38
39 /* logsin table */
40 static const Bit16u logsinrom[256] = {
41 0x859, 0x6c3, 0x607, 0x58b, 0x52e, 0x4e4, 0x4a6, 0x471,
42 0x443, 0x41a, 0x3f5, 0x3d3, 0x3b5, 0x398, 0x37e, 0x365,
43 0x34e, 0x339, 0x324, 0x311, 0x2ff, 0x2ed, 0x2dc, 0x2cd,
44 0x2bd, 0x2af, 0x2a0, 0x293, 0x286, 0x279, 0x26d, 0x261,
45 0x256, 0x24b, 0x240, 0x236, 0x22c, 0x222, 0x218, 0x20f,
46 0x206, 0x1fd, 0x1f5, 0x1ec, 0x1e4, 0x1dc, 0x1d4, 0x1cd,
47 0x1c5, 0x1be, 0x1b7, 0x1b0, 0x1a9, 0x1a2, 0x19b, 0x195,
48 0x18f, 0x188, 0x182, 0x17c, 0x177, 0x171, 0x16b, 0x166,
49 0x160, 0x15b, 0x155, 0x150, 0x14b, 0x146, 0x141, 0x13c,
50 0x137, 0x133, 0x12e, 0x129, 0x125, 0x121, 0x11c, 0x118,
51 0x114, 0x10f, 0x10b, 0x107, 0x103, 0x0ff, 0x0fb, 0x0f8,
52 0x0f4, 0x0f0, 0x0ec, 0x0e9, 0x0e5, 0x0e2, 0x0de, 0x0db,
53 0x0d7, 0x0d4, 0x0d1, 0x0cd, 0x0ca, 0x0c7, 0x0c4, 0x0c1,
54 0x0be, 0x0bb, 0x0b8, 0x0b5, 0x0b2, 0x0af, 0x0ac, 0x0a9,
55 0x0a7, 0x0a4, 0x0a1, 0x09f, 0x09c, 0x099, 0x097, 0x094,
56 0x092, 0x08f, 0x08d, 0x08a, 0x088, 0x086, 0x083, 0x081,
57 0x07f, 0x07d, 0x07a, 0x078, 0x076, 0x074, 0x072, 0x070,
58 0x06e, 0x06c, 0x06a, 0x068, 0x066, 0x064, 0x062, 0x060,
59 0x05e, 0x05c, 0x05b, 0x059, 0x057, 0x055, 0x053, 0x052,
60 0x050, 0x04e, 0x04d, 0x04b, 0x04a, 0x048, 0x046, 0x045,
61 0x043, 0x042, 0x040, 0x03f, 0x03e, 0x03c, 0x03b, 0x039,
62 0x038, 0x037, 0x035, 0x034, 0x033, 0x031, 0x030, 0x02f,
63 0x02e, 0x02d, 0x02b, 0x02a, 0x029, 0x028, 0x027, 0x026,
64 0x025, 0x024, 0x023, 0x022, 0x021, 0x020, 0x01f, 0x01e,
65 0x01d, 0x01c, 0x01b, 0x01a, 0x019, 0x018, 0x017, 0x017,
66 0x016, 0x015, 0x014, 0x014, 0x013, 0x012, 0x011, 0x011,
67 0x010, 0x00f, 0x00f, 0x00e, 0x00d, 0x00d, 0x00c, 0x00c,
68 0x00b, 0x00a, 0x00a, 0x009, 0x009, 0x008, 0x008, 0x007,
69 0x007, 0x007, 0x006, 0x006, 0x005, 0x005, 0x005, 0x004,
70 0x004, 0x004, 0x003, 0x003, 0x003, 0x002, 0x002, 0x002,
71 0x002, 0x001, 0x001, 0x001, 0x001, 0x001, 0x001, 0x001,
72 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000, 0x000
73 };
74
75 /* exp table */
76 static const Bit16u exprom[256] = {
77 0x000, 0x003, 0x006, 0x008, 0x00b, 0x00e, 0x011, 0x014,
78 0x016, 0x019, 0x01c, 0x01f, 0x022, 0x025, 0x028, 0x02a,
79 0x02d, 0x030, 0x033, 0x036, 0x039, 0x03c, 0x03f, 0x042,
80 0x045, 0x048, 0x04b, 0x04e, 0x051, 0x054, 0x057, 0x05a,
81 0x05d, 0x060, 0x063, 0x066, 0x069, 0x06c, 0x06f, 0x072,
82 0x075, 0x078, 0x07b, 0x07e, 0x082, 0x085, 0x088, 0x08b,
83 0x08e, 0x091, 0x094, 0x098, 0x09b, 0x09e, 0x0a1, 0x0a4,
84 0x0a8, 0x0ab, 0x0ae, 0x0b1, 0x0b5, 0x0b8, 0x0bb, 0x0be,
85 0x0c2, 0x0c5, 0x0c8, 0x0cc, 0x0cf, 0x0d2, 0x0d6, 0x0d9,
86 0x0dc, 0x0e0, 0x0e3, 0x0e7, 0x0ea, 0x0ed, 0x0f1, 0x0f4,
87 0x0f8, 0x0fb, 0x0ff, 0x102, 0x106, 0x109, 0x10c, 0x110,
88 0x114, 0x117, 0x11b, 0x11e, 0x122, 0x125, 0x129, 0x12c,
89 0x130, 0x134, 0x137, 0x13b, 0x13e, 0x142, 0x146, 0x149,
90 0x14d, 0x151, 0x154, 0x158, 0x15c, 0x160, 0x163, 0x167,
91 0x16b, 0x16f, 0x172, 0x176, 0x17a, 0x17e, 0x181, 0x185,
92 0x189, 0x18d, 0x191, 0x195, 0x199, 0x19c, 0x1a0, 0x1a4,
93 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc, 0x1c0, 0x1c4,
94 0x1c8, 0x1cc, 0x1d0, 0x1d4, 0x1d8, 0x1dc, 0x1e0, 0x1e4,
95 0x1e8, 0x1ec, 0x1f0, 0x1f5, 0x1f9, 0x1fd, 0x201, 0x205,
96 0x209, 0x20e, 0x212, 0x216, 0x21a, 0x21e, 0x223, 0x227,
97 0x22b, 0x230, 0x234, 0x238, 0x23c, 0x241, 0x245, 0x249,
98 0x24e, 0x252, 0x257, 0x25b, 0x25f, 0x264, 0x268, 0x26d,
99 0x271, 0x276, 0x27a, 0x27f, 0x283, 0x288, 0x28c, 0x291,
100 0x295, 0x29a, 0x29e, 0x2a3, 0x2a8, 0x2ac, 0x2b1, 0x2b5,
101 0x2ba, 0x2bf, 0x2c4, 0x2c8, 0x2cd, 0x2d2, 0x2d6, 0x2db,
102 0x2e0, 0x2e5, 0x2e9, 0x2ee, 0x2f3, 0x2f8, 0x2fd, 0x302,
103 0x306, 0x30b, 0x310, 0x315, 0x31a, 0x31f, 0x324, 0x329,
104 0x32e, 0x333, 0x338, 0x33d, 0x342, 0x347, 0x34c, 0x351,
105 0x356, 0x35b, 0x360, 0x365, 0x36a, 0x370, 0x375, 0x37a,
106 0x37f, 0x384, 0x38a, 0x38f, 0x394, 0x399, 0x39f, 0x3a4,
107 0x3a9, 0x3ae, 0x3b4, 0x3b9, 0x3bf, 0x3c4, 0x3c9, 0x3cf,
108 0x3d4, 0x3da, 0x3df, 0x3e4, 0x3ea, 0x3ef, 0x3f5, 0x3fa
109 };
110
111 /* Note table */
112 static const Bit32u fn_note[16] = {
113 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 3, 3, 3, 3, 3, 3
114 };
115
116 /* Envelope generator */
117 static const Bit32u eg_stephi[4][4] = {
118 { 0, 0, 0, 0 },
119 { 1, 0, 0, 0 },
120 { 1, 0, 1, 0 },
121 { 1, 1, 1, 0 }
122 };
123
124 static const Bit8u eg_am_shift[4] = {
125 7, 3, 1, 0
126 };
127
128 /* Phase generator */
129 static const Bit32u pg_detune[8] = { 16, 17, 19, 20, 22, 24, 27, 29 };
130
131 static const Bit32u pg_lfo_sh1[8][8] = {
132 { 7, 7, 7, 7, 7, 7, 7, 7 },
133 { 7, 7, 7, 7, 7, 7, 7, 7 },
134 { 7, 7, 7, 7, 7, 7, 1, 1 },
135 { 7, 7, 7, 7, 1, 1, 1, 1 },
136 { 7, 7, 7, 1, 1, 1, 1, 0 },
137 { 7, 7, 1, 1, 0, 0, 0, 0 },
138 { 7, 7, 1, 1, 0, 0, 0, 0 },
139 { 7, 7, 1, 1, 0, 0, 0, 0 }
140 };
141
142 static const Bit32u pg_lfo_sh2[8][8] = {
143 { 7, 7, 7, 7, 7, 7, 7, 7 },
144 { 7, 7, 7, 7, 2, 2, 2, 2 },
145 { 7, 7, 7, 2, 2, 2, 7, 7 },
146 { 7, 7, 2, 2, 7, 7, 2, 2 },
147 { 7, 7, 2, 7, 7, 7, 2, 7 },
148 { 7, 7, 7, 2, 7, 7, 2, 1 },
149 { 7, 7, 7, 2, 7, 7, 2, 1 },
150 { 7, 7, 7, 2, 7, 7, 2, 1 }
151 };
152
153 /* Address decoder */
154 static const Bit32u op_offset[12] = {
155 0x000, /* Ch1 OP1/OP2 */
156 0x001, /* Ch2 OP1/OP2 */
157 0x002, /* Ch3 OP1/OP2 */
158 0x100, /* Ch4 OP1/OP2 */
159 0x101, /* Ch5 OP1/OP2 */
160 0x102, /* Ch6 OP1/OP2 */
161 0x004, /* Ch1 OP3/OP4 */
162 0x005, /* Ch2 OP3/OP4 */
163 0x006, /* Ch3 OP3/OP4 */
164 0x104, /* Ch4 OP3/OP4 */
165 0x105, /* Ch5 OP3/OP4 */
166 0x106 /* Ch6 OP3/OP4 */
167 };
168
169 static const Bit32u ch_offset[6] = {
170 0x000, /* Ch1 */
171 0x001, /* Ch2 */
172 0x002, /* Ch3 */
173 0x100, /* Ch4 */
174 0x101, /* Ch5 */
175 0x102 /* Ch6 */
176 };
177
178 /* LFO */
179 static const Bit32u lfo_cycles[8] = {
180 108, 77, 71, 67, 62, 44, 8, 5
181 };
182
183 /* FM algorithm */
184 static const Bit32u fm_algorithm[4][6][8] = {
185 {
186 { 1, 1, 1, 1, 1, 1, 1, 1 }, /* OP1_0 */
187 { 1, 1, 1, 1, 1, 1, 1, 1 }, /* OP1_1 */
188 { 0, 0, 0, 0, 0, 0, 0, 0 }, /* OP2 */
189 { 0, 0, 0, 0, 0, 0, 0, 0 }, /* Last operator */
190 { 0, 0, 0, 0, 0, 0, 0, 0 }, /* Last operator */
191 { 0, 0, 0, 0, 0, 0, 0, 1 } /* Out */
192 },
193 {
194 { 0, 1, 0, 0, 0, 1, 0, 0 }, /* OP1_0 */
195 { 0, 0, 0, 0, 0, 0, 0, 0 }, /* OP1_1 */
196 { 1, 1, 1, 0, 0, 0, 0, 0 }, /* OP2 */
197 { 0, 0, 0, 0, 0, 0, 0, 0 }, /* Last operator */
198 { 0, 0, 0, 0, 0, 0, 0, 0 }, /* Last operator */
199 { 0, 0, 0, 0, 0, 1, 1, 1 } /* Out */
200 },
201 {
202 { 0, 0, 0, 0, 0, 0, 0, 0 }, /* OP1_0 */
203 { 0, 0, 0, 0, 0, 0, 0, 0 }, /* OP1_1 */
204 { 0, 0, 0, 0, 0, 0, 0, 0 }, /* OP2 */
205 { 1, 0, 0, 1, 1, 1, 1, 0 }, /* Last operator */
206 { 0, 0, 0, 0, 0, 0, 0, 0 }, /* Last operator */
207 { 0, 0, 0, 0, 1, 1, 1, 1 } /* Out */
208 },
209 {
210 { 0, 0, 1, 0, 0, 1, 0, 0 }, /* OP1_0 */
211 { 0, 0, 0, 0, 0, 0, 0, 0 }, /* OP1_1 */
212 { 0, 0, 0, 1, 0, 0, 0, 0 }, /* OP2 */
213 { 1, 1, 0, 1, 1, 0, 0, 0 }, /* Last operator */
214 { 0, 0, 1, 0, 0, 0, 0, 0 }, /* Last operator */
215 { 1, 1, 1, 1, 1, 1, 1, 1 } /* Out */
216 }
217 };
218
219 /*
220 * Pan law table
221 */
222
223 static const Bit16u panlawtable[] =
224 {
225 65535, 65529, 65514, 65489, 65454, 65409, 65354, 65289,
226 65214, 65129, 65034, 64929, 64814, 64689, 64554, 64410,
227 64255, 64091, 63917, 63733, 63540, 63336, 63123, 62901,
228 62668, 62426, 62175, 61914, 61644, 61364, 61075, 60776,
229 60468, 60151, 59825, 59489, 59145, 58791, 58428, 58057,
230 57676, 57287, 56889, 56482, 56067, 55643, 55211, 54770,
231 54320, 53863, 53397, 52923, 52441, 51951, 51453, 50947,
232 50433, 49912, 49383, 48846, 48302, 47750, 47191,
233 46340, /* Center left */
234 46340, /* Center right */
235 45472, 44885, 44291, 43690, 43083, 42469, 41848, 41221,
236 40588, 39948, 39303, 38651, 37994, 37330, 36661, 35986,
237 35306, 34621, 33930, 33234, 32533, 31827, 31116, 30400,
238 29680, 28955, 28225, 27492, 26754, 26012, 25266, 24516,
239 23762, 23005, 22244, 21480, 20713, 19942, 19169, 18392,
240 17613, 16831, 16046, 15259, 14469, 13678, 12884, 12088,
241 11291, 10492, 9691, 8888, 8085, 7280, 6473, 5666,
242 4858, 4050, 3240, 2431, 1620, 810, 0
243 };
244
245 static Bit32u chip_type = ym3438_mode_readmode;
246
OPN2_DoIO(ym3438_t * chip)247 void OPN2_DoIO(ym3438_t *chip)
248 {
249 /* Write signal check */
250 chip->write_a_en = (chip->write_a & 0x03) == 0x01;
251 chip->write_d_en = (chip->write_d & 0x03) == 0x01;
252 chip->write_a <<= 1;
253 chip->write_d <<= 1;
254 /* Busy counter */
255 chip->busy = chip->write_busy;
256 chip->write_busy_cnt += chip->write_busy;
257 chip->write_busy = (chip->write_busy && !(chip->write_busy_cnt >> 5)) || chip->write_d_en;
258 chip->write_busy_cnt &= 0x1f;
259 }
260
OPN2_DoRegWrite(ym3438_t * chip)261 void OPN2_DoRegWrite(ym3438_t *chip)
262 {
263 Bit32u i;
264 Bit32u slot = chip->cycles % 12;
265 Bit32u address;
266 Bit32u channel = chip->channel;
267 /* Update registers */
268 if (chip->write_fm_data)
269 {
270 /* Slot */
271 if (op_offset[slot] == (chip->address & 0x107))
272 {
273 if (chip->address & 0x08)
274 {
275 /* OP2, OP4 */
276 slot += 12;
277 }
278 address = chip->address & 0xf0;
279 switch (address)
280 {
281 case 0x30: /* DT, MULTI */
282 chip->multi[slot] = chip->data & 0x0f;
283 if (!chip->multi[slot])
284 {
285 chip->multi[slot] = 1;
286 }
287 else
288 {
289 chip->multi[slot] <<= 1;
290 }
291 chip->dt[slot] = (chip->data >> 4) & 0x07;
292 break;
293 case 0x40: /* TL */
294 chip->tl[slot] = chip->data & 0x7f;
295 break;
296 case 0x50: /* KS, AR */
297 chip->ar[slot] = chip->data & 0x1f;
298 chip->ks[slot] = (chip->data >> 6) & 0x03;
299 break;
300 case 0x60: /* AM, DR */
301 chip->dr[slot] = chip->data & 0x1f;
302 chip->am[slot] = (chip->data >> 7) & 0x01;
303 break;
304 case 0x70: /* SR */
305 chip->sr[slot] = chip->data & 0x1f;
306 break;
307 case 0x80: /* SL, RR */
308 chip->rr[slot] = chip->data & 0x0f;
309 chip->sl[slot] = (chip->data >> 4) & 0x0f;
310 chip->sl[slot] |= (chip->sl[slot] + 1) & 0x10;
311 break;
312 case 0x90: /* SSG-EG */
313 chip->ssg_eg[slot] = chip->data & 0x0f;
314 break;
315 default:
316 break;
317 }
318 }
319
320 /* Channel */
321 if (ch_offset[channel] == (chip->address & 0x103))
322 {
323 address = chip->address & 0xfc;
324 switch (address)
325 {
326 case 0xa0:
327 chip->fnum[channel] = (chip->data & 0xff) | ((chip->reg_a4 & 0x07) << 8);
328 chip->block[channel] = (chip->reg_a4 >> 3) & 0x07;
329 chip->kcode[channel] = (chip->block[channel] << 2) | fn_note[chip->fnum[channel] >> 7];
330 break;
331 case 0xa4:
332 chip->reg_a4 = chip->data & 0xff;
333 break;
334 case 0xa8:
335 chip->fnum_3ch[channel] = (chip->data & 0xff) | ((chip->reg_ac & 0x07) << 8);
336 chip->block_3ch[channel] = (chip->reg_ac >> 3) & 0x07;
337 chip->kcode_3ch[channel] = (chip->block_3ch[channel] << 2) | fn_note[chip->fnum_3ch[channel] >> 7];
338 break;
339 case 0xac:
340 chip->reg_ac = chip->data & 0xff;
341 break;
342 case 0xb0:
343 chip->connect[channel] = chip->data & 0x07;
344 chip->fb[channel] = (chip->data >> 3) & 0x07;
345 break;
346 case 0xb4:
347 chip->pms[channel] = chip->data & 0x07;
348 chip->ams[channel] = (chip->data >> 4) & 0x03;
349 chip->pan_l[channel] = (chip->data >> 7) & 0x01;
350 chip->pan_r[channel] = (chip->data >> 6) & 0x01;
351 break;
352 default:
353 break;
354 }
355 }
356 }
357
358 if (chip->write_a_en || chip->write_d_en)
359 {
360 /* Data */
361 if (chip->write_a_en)
362 {
363 chip->write_fm_data = 0;
364 }
365
366 if (chip->write_fm_address && chip->write_d_en)
367 {
368 chip->write_fm_data = 1;
369 }
370
371 /* Address */
372 if (chip->write_a_en)
373 {
374 if ((chip->write_data & 0xf0) != 0x00)
375 {
376 /* FM Write */
377 chip->address = chip->write_data;
378 chip->write_fm_address = 1;
379 }
380 else
381 {
382 /* SSG write */
383 chip->write_fm_address = 0;
384 }
385 }
386
387 /* FM Mode */
388 /* Data */
389 if (chip->write_d_en && (chip->write_data & 0x100) == 0)
390 {
391 switch (chip->write_fm_mode_a)
392 {
393 case 0x21: /* LSI test 1 */
394 for (i = 0; i < 8; i++)
395 {
396 chip->mode_test_21[i] = (chip->write_data >> i) & 0x01;
397 }
398 break;
399 case 0x22: /* LFO control */
400 if ((chip->write_data >> 3) & 0x01)
401 {
402 chip->lfo_en = 0x7f;
403 }
404 else
405 {
406 chip->lfo_en = 0;
407 }
408 chip->lfo_freq = chip->write_data & 0x07;
409 break;
410 case 0x24: /* Timer A */
411 chip->timer_a_reg &= 0x03;
412 chip->timer_a_reg |= (chip->write_data & 0xff) << 2;
413 break;
414 case 0x25:
415 chip->timer_a_reg &= 0x3fc;
416 chip->timer_a_reg |= chip->write_data & 0x03;
417 break;
418 case 0x26: /* Timer B */
419 chip->timer_b_reg = chip->write_data & 0xff;
420 break;
421 case 0x27: /* CSM, Timer control */
422 chip->mode_ch3 = (chip->write_data & 0xc0) >> 6;
423 chip->mode_csm = chip->mode_ch3 == 2;
424 chip->timer_a_load = chip->write_data & 0x01;
425 chip->timer_a_enable = (chip->write_data >> 2) & 0x01;
426 chip->timer_a_reset = (chip->write_data >> 4) & 0x01;
427 chip->timer_b_load = (chip->write_data >> 1) & 0x01;
428 chip->timer_b_enable = (chip->write_data >> 3) & 0x01;
429 chip->timer_b_reset = (chip->write_data >> 5) & 0x01;
430 break;
431 case 0x28: /* Key on/off */
432 for (i = 0; i < 4; i++)
433 {
434 chip->mode_kon_operator[i] = (chip->write_data >> (4 + i)) & 0x01;
435 }
436 if ((chip->write_data & 0x03) == 0x03)
437 {
438 /* Invalid address */
439 chip->mode_kon_channel = 0xff;
440 }
441 else
442 {
443 chip->mode_kon_channel = (chip->write_data & 0x03) + ((chip->write_data >> 2) & 1) * 3;
444 }
445 break;
446 case 0x2a: /* DAC data */
447 chip->dacdata &= 0x01;
448 chip->dacdata |= (chip->write_data ^ 0x80) << 1;
449 break;
450 case 0x2b: /* DAC enable */
451 chip->dacen = chip->write_data >> 7;
452 break;
453 case 0x2c: /* LSI test 2 */
454 for (i = 0; i < 8; i++)
455 {
456 chip->mode_test_2c[i] = (chip->write_data >> i) & 0x01;
457 }
458 chip->dacdata &= 0x1fe;
459 chip->dacdata |= chip->mode_test_2c[3];
460 chip->eg_custom_timer = !chip->mode_test_2c[7] && chip->mode_test_2c[6];
461 break;
462 default:
463 break;
464 }
465 }
466
467 /* Address */
468 if (chip->write_a_en)
469 {
470 chip->write_fm_mode_a = chip->write_data & 0x1ff;
471 }
472 }
473
474 if (chip->write_fm_data)
475 {
476 chip->data = chip->write_data & 0xff;
477 }
478 }
479
OPN2_PhaseCalcIncrement(ym3438_t * chip)480 void OPN2_PhaseCalcIncrement(ym3438_t *chip)
481 {
482 Bit32u chan = chip->channel;
483 Bit32u slot = chip->cycles;
484 Bit32u fnum = chip->pg_fnum;
485 Bit32u fnum_h = fnum >> 4;
486 Bit32u fm;
487 Bit32u basefreq;
488 Bit8u lfo = chip->lfo_pm;
489 Bit8u lfo_l = lfo & 0x0f;
490 Bit8u pms = chip->pms[chan];
491 Bit8u dt = chip->dt[slot];
492 Bit8u dt_l = dt & 0x03;
493 Bit8u detune = 0;
494 Bit8u block, note;
495 Bit8u sum, sum_h, sum_l;
496 Bit8u kcode = chip->pg_kcode;
497
498 fnum <<= 1;
499 /* Apply LFO */
500 if (lfo_l & 0x08)
501 {
502 lfo_l ^= 0x0f;
503 }
504 fm = (fnum_h >> pg_lfo_sh1[pms][lfo_l]) + (fnum_h >> pg_lfo_sh2[pms][lfo_l]);
505 if (pms > 5)
506 {
507 fm <<= pms - 5;
508 }
509 fm >>= 2;
510 if (lfo & 0x10)
511 {
512 fnum -= fm;
513 }
514 else
515 {
516 fnum += fm;
517 }
518 fnum &= 0xfff;
519
520 basefreq = (fnum << chip->pg_block) >> 2;
521
522 /* Apply detune */
523 if (dt_l)
524 {
525 if (kcode > 0x1c)
526 {
527 kcode = 0x1c;
528 }
529 block = kcode >> 2;
530 note = kcode & 0x03;
531 sum = block + 9 + ((dt_l == 3) | (dt_l & 0x02));
532 sum_h = sum >> 1;
533 sum_l = sum & 0x01;
534 detune = pg_detune[(sum_l << 2) | note] >> (9 - sum_h);
535 }
536 if (dt & 0x04)
537 {
538 basefreq -= detune;
539 }
540 else
541 {
542 basefreq += detune;
543 }
544 basefreq &= 0x1ffff;
545 chip->pg_inc[slot] = (basefreq * chip->multi[slot]) >> 1;
546 chip->pg_inc[slot] &= 0xfffff;
547 }
548
OPN2_PhaseGenerate(ym3438_t * chip)549 void OPN2_PhaseGenerate(ym3438_t *chip)
550 {
551 Bit32u slot;
552 /* Mask increment */
553 slot = (chip->cycles + 20) % 24;
554 if (chip->pg_reset[slot])
555 {
556 chip->pg_inc[slot] = 0;
557 }
558 /* Phase step */
559 slot = (chip->cycles + 19) % 24;
560 chip->pg_phase[slot] += chip->pg_inc[slot];
561 chip->pg_phase[slot] &= 0xfffff;
562 if (chip->pg_reset[slot] || chip->mode_test_21[3])
563 {
564 chip->pg_phase[slot] = 0;
565 }
566 }
567
OPN2_EnvelopeSSGEG(ym3438_t * chip)568 void OPN2_EnvelopeSSGEG(ym3438_t *chip)
569 {
570 Bit32u slot = chip->cycles;
571 Bit8u direction = 0;
572 chip->eg_ssg_pgrst_latch[slot] = 0;
573 chip->eg_ssg_repeat_latch[slot] = 0;
574 chip->eg_ssg_hold_up_latch[slot] = 0;
575 chip->eg_ssg_inv[slot] = 0;
576 if (chip->ssg_eg[slot] & 0x08)
577 {
578 direction = chip->eg_ssg_dir[slot];
579 if (chip->eg_level[slot] & 0x200)
580 {
581 /* Reset */
582 if ((chip->ssg_eg[slot] & 0x03) == 0x00)
583 {
584 chip->eg_ssg_pgrst_latch[slot] = 1;
585 }
586 /* Repeat */
587 if ((chip->ssg_eg[slot] & 0x01) == 0x00)
588 {
589 chip->eg_ssg_repeat_latch[slot] = 1;
590 }
591 /* Inverse */
592 if ((chip->ssg_eg[slot] & 0x03) == 0x02)
593 {
594 direction ^= 1;
595 }
596 if ((chip->ssg_eg[slot] & 0x03) == 0x03)
597 {
598 direction = 1;
599 }
600 }
601 /* Hold up */
602 if (chip->eg_kon_latch[slot]
603 && ((chip->ssg_eg[slot] & 0x07) == 0x05 || (chip->ssg_eg[slot] & 0x07) == 0x03))
604 {
605 chip->eg_ssg_hold_up_latch[slot] = 1;
606 }
607 direction &= chip->eg_kon[slot];
608 chip->eg_ssg_inv[slot] = (chip->eg_ssg_dir[slot] ^ ((chip->ssg_eg[slot] >> 2) & 0x01))
609 & chip->eg_kon[slot];
610 }
611 chip->eg_ssg_dir[slot] = direction;
612 chip->eg_ssg_enable[slot] = (chip->ssg_eg[slot] >> 3) & 0x01;
613 }
614
OPN2_EnvelopeADSR(ym3438_t * chip)615 void OPN2_EnvelopeADSR(ym3438_t *chip)
616 {
617 Bit32u slot = (chip->cycles + 22) % 24;
618
619 Bit8u nkon = chip->eg_kon_latch[slot];
620 Bit8u okon = chip->eg_kon[slot];
621 Bit8u kon_event;
622 Bit8u koff_event;
623 Bit8u eg_off;
624 Bit16s level;
625 Bit16s nextlevel = 0;
626 Bit16s ssg_level;
627 Bit8u nextstate = chip->eg_state[slot];
628 Bit16s inc = 0;
629 chip->eg_read[0] = chip->eg_read_inc;
630 chip->eg_read_inc = chip->eg_inc > 0;
631
632 /* Reset phase generator */
633 chip->pg_reset[slot] = (nkon && !okon) || chip->eg_ssg_pgrst_latch[slot];
634
635 /* KeyOn/Off */
636 kon_event = (nkon && !okon) || (okon && chip->eg_ssg_repeat_latch[slot]);
637 koff_event = okon && !nkon;
638
639 ssg_level = level = (Bit16s)chip->eg_level[slot];
640
641 if (chip->eg_ssg_inv[slot])
642 {
643 /* Inverse */
644 ssg_level = 512 - level;
645 ssg_level &= 0x3ff;
646 }
647 if (koff_event)
648 {
649 level = ssg_level;
650 }
651 if (chip->eg_ssg_enable[slot])
652 {
653 eg_off = level >> 9;
654 }
655 else
656 {
657 eg_off = (level & 0x3f0) == 0x3f0;
658 }
659 nextlevel = level;
660 if (kon_event)
661 {
662 nextstate = eg_num_attack;
663 /* Instant attack */
664 if (chip->eg_ratemax)
665 {
666 nextlevel = 0;
667 }
668 else if (chip->eg_state[slot] == eg_num_attack && level != 0 && chip->eg_inc && nkon)
669 {
670 inc = (~level << chip->eg_inc) >> 5;
671 }
672 }
673 else
674 {
675 switch (chip->eg_state[slot])
676 {
677 case eg_num_attack:
678 if (level == 0)
679 {
680 nextstate = eg_num_decay;
681 }
682 else if(chip->eg_inc && !chip->eg_ratemax && nkon)
683 {
684 inc = (~level << chip->eg_inc) >> 5;
685 }
686 break;
687 case eg_num_decay:
688 if ((level >> 5) == chip->eg_sl[1])
689 {
690 nextstate = eg_num_sustain;
691 }
692 else if (!eg_off && chip->eg_inc)
693 {
694 inc = 1 << (chip->eg_inc - 1);
695 if (chip->eg_ssg_enable[slot])
696 {
697 inc <<= 2;
698 }
699 }
700 break;
701 case eg_num_sustain:
702 case eg_num_release:
703 if (!eg_off && chip->eg_inc)
704 {
705 inc = 1 << (chip->eg_inc - 1);
706 if (chip->eg_ssg_enable[slot])
707 {
708 inc <<= 2;
709 }
710 }
711 break;
712 default:
713 break;
714 }
715 if (!nkon)
716 {
717 nextstate = eg_num_release;
718 }
719 }
720 if (chip->eg_kon_csm[slot])
721 {
722 nextlevel |= chip->eg_tl[1] << 3;
723 }
724
725 /* Envelope off */
726 if (!kon_event && !chip->eg_ssg_hold_up_latch[slot] && chip->eg_state[slot] != eg_num_attack && eg_off)
727 {
728 nextstate = eg_num_release;
729 nextlevel = 0x3ff;
730 }
731
732 nextlevel += inc;
733
734 chip->eg_kon[slot] = chip->eg_kon_latch[slot];
735 chip->eg_level[slot] = (Bit16u)nextlevel & 0x3ff;
736 chip->eg_state[slot] = nextstate;
737 }
738
OPN2_EnvelopePrepare(ym3438_t * chip)739 void OPN2_EnvelopePrepare(ym3438_t *chip)
740 {
741 Bit8u rate;
742 Bit8u sum;
743 Bit8u inc = 0;
744 Bit32u slot = chip->cycles;
745 Bit8u rate_sel;
746
747 /* Prepare increment */
748 rate = (chip->eg_rate << 1) + chip->eg_ksv;
749
750 if (rate > 0x3f)
751 {
752 rate = 0x3f;
753 }
754
755 sum = ((rate >> 2) + chip->eg_shift_lock) & 0x0f;
756 if (chip->eg_rate != 0 && chip->eg_quotient == 2)
757 {
758 if (rate < 48)
759 {
760 switch (sum)
761 {
762 case 12:
763 inc = 1;
764 break;
765 case 13:
766 inc = (rate >> 1) & 0x01;
767 break;
768 case 14:
769 inc = rate & 0x01;
770 break;
771 default:
772 break;
773 }
774 }
775 else
776 {
777 inc = eg_stephi[rate & 0x03][chip->eg_timer_low_lock] + (rate >> 2) - 11;
778 if (inc > 4)
779 {
780 inc = 4;
781 }
782 }
783 }
784 chip->eg_inc = inc;
785 chip->eg_ratemax = (rate >> 1) == 0x1f;
786
787 /* Prepare rate & ksv */
788 rate_sel = chip->eg_state[slot];
789 if ((chip->eg_kon[slot] && chip->eg_ssg_repeat_latch[slot])
790 || (!chip->eg_kon[slot] && chip->eg_kon_latch[slot]))
791 {
792 rate_sel = eg_num_attack;
793 }
794 switch (rate_sel)
795 {
796 case eg_num_attack:
797 chip->eg_rate = chip->ar[slot];
798 break;
799 case eg_num_decay:
800 chip->eg_rate = chip->dr[slot];
801 break;
802 case eg_num_sustain:
803 chip->eg_rate = chip->sr[slot];
804 break;
805 case eg_num_release:
806 chip->eg_rate = (chip->rr[slot] << 1) | 0x01;
807 break;
808 default:
809 break;
810 }
811 chip->eg_ksv = chip->pg_kcode >> (chip->ks[slot] ^ 0x03);
812 if (chip->am[slot])
813 {
814 chip->eg_lfo_am = chip->lfo_am >> eg_am_shift[chip->ams[chip->channel]];
815 }
816 else
817 {
818 chip->eg_lfo_am = 0;
819 }
820 /* Delay TL & SL value */
821 chip->eg_tl[1] = chip->eg_tl[0];
822 chip->eg_tl[0] = chip->tl[slot];
823 chip->eg_sl[1] = chip->eg_sl[0];
824 chip->eg_sl[0] = chip->sl[slot];
825 }
826
OPN2_EnvelopeGenerate(ym3438_t * chip)827 void OPN2_EnvelopeGenerate(ym3438_t *chip)
828 {
829 Bit32u slot = (chip->cycles + 23) % 24;
830 Bit16u level;
831
832 level = chip->eg_level[slot];
833
834 if (chip->eg_ssg_inv[slot])
835 {
836 /* Inverse */
837 level = 512 - level;
838 }
839 if (chip->mode_test_21[5])
840 {
841 level = 0;
842 }
843 level &= 0x3ff;
844
845 /* Apply AM LFO */
846 level += chip->eg_lfo_am;
847
848 /* Apply TL */
849 if (!(chip->mode_csm && chip->channel == 2 + 1))
850 {
851 level += chip->eg_tl[0] << 3;
852 }
853 if (level > 0x3ff)
854 {
855 level = 0x3ff;
856 }
857 chip->eg_out[slot] = level;
858 }
859
OPN2_UpdateLFO(ym3438_t * chip)860 void OPN2_UpdateLFO(ym3438_t *chip)
861 {
862 if ((chip->lfo_quotient & lfo_cycles[chip->lfo_freq]) == lfo_cycles[chip->lfo_freq])
863 {
864 chip->lfo_quotient = 0;
865 chip->lfo_cnt++;
866 }
867 else
868 {
869 chip->lfo_quotient += chip->lfo_inc;
870 }
871 chip->lfo_cnt &= chip->lfo_en;
872 }
873
OPN2_FMPrepare(ym3438_t * chip)874 void OPN2_FMPrepare(ym3438_t *chip)
875 {
876 Bit32u slot = (chip->cycles + 6) % 24;
877 Bit32u channel = chip->channel;
878 Bit16s mod, mod1, mod2;
879 Bit32u op = slot / 6;
880 Bit8u connect = chip->connect[channel];
881 Bit32u prevslot = (chip->cycles + 18) % 24;
882
883 /* Calculate modulation */
884 mod1 = mod2 = 0;
885
886 if (fm_algorithm[op][0][connect])
887 {
888 mod2 |= chip->fm_op1[channel][0];
889 }
890 if (fm_algorithm[op][1][connect])
891 {
892 mod1 |= chip->fm_op1[channel][1];
893 }
894 if (fm_algorithm[op][2][connect])
895 {
896 mod1 |= chip->fm_op2[channel];
897 }
898 if (fm_algorithm[op][3][connect])
899 {
900 mod2 |= chip->fm_out[prevslot];
901 }
902 if (fm_algorithm[op][4][connect])
903 {
904 mod1 |= chip->fm_out[prevslot];
905 }
906 mod = mod1 + mod2;
907 if (op == 0)
908 {
909 /* Feedback */
910 mod = mod >> (10 - chip->fb[channel]);
911 if (!chip->fb[channel])
912 {
913 mod = 0;
914 }
915 }
916 else
917 {
918 mod >>= 1;
919 }
920 chip->fm_mod[slot] = mod;
921
922 slot = (chip->cycles + 18) % 24;
923 /* OP1 */
924 if (slot / 6 == 0)
925 {
926 chip->fm_op1[channel][1] = chip->fm_op1[channel][0];
927 chip->fm_op1[channel][0] = chip->fm_out[slot];
928 }
929 /* OP2 */
930 if (slot / 6 == 2)
931 {
932 chip->fm_op2[channel] = chip->fm_out[slot];
933 }
934 }
935
OPN2_ChGenerate(ym3438_t * chip)936 void OPN2_ChGenerate(ym3438_t *chip)
937 {
938 Bit32u slot = (chip->cycles + 18) % 24;
939 Bit32u channel = chip->channel;
940 Bit32u op = slot / 6;
941 Bit32u test_dac = chip->mode_test_2c[5];
942 Bit16s acc = chip->ch_acc[channel];
943 Bit16s add = test_dac;
944 Bit16s sum = 0;
945 if (op == 0 && !test_dac)
946 {
947 acc = 0;
948 }
949 if (fm_algorithm[op][5][chip->connect[channel]] && !test_dac)
950 {
951 add += chip->fm_out[slot] >> 5;
952 }
953 sum = acc + add;
954 /* Clamp */
955 if (sum > 255)
956 {
957 sum = 255;
958 }
959 else if(sum < -256)
960 {
961 sum = -256;
962 }
963
964 if (op == 0 || test_dac)
965 {
966 chip->ch_out[channel] = chip->ch_acc[channel];
967 }
968 chip->ch_acc[channel] = sum;
969 }
970
OPN2_ChOutput(ym3438_t * chip)971 void OPN2_ChOutput(ym3438_t *chip)
972 {
973 Bit32u cycles = chip->cycles;
974 Bit32u slot = chip->cycles;
975 Bit32u channel = chip->channel;
976 Bit32u test_dac = chip->mode_test_2c[5];
977 Bit16s out;
978 Bit16s sign;
979 Bit32u out_en;
980 chip->ch_read = chip->ch_lock;
981 if (slot < 12)
982 {
983 /* Ch 4,5,6 */
984 channel++;
985 }
986 if ((cycles & 3) == 0)
987 {
988 if (!test_dac)
989 {
990 /* Lock value */
991 chip->ch_lock = chip->ch_out[channel];
992 }
993 chip->ch_lock_l = chip->pan_l[channel];
994 chip->ch_lock_r = chip->pan_r[channel];
995 }
996 /* Ch 6 */
997 if (((cycles >> 2) == 1 && chip->dacen) || test_dac)
998 {
999 out = (Bit16s)chip->dacdata;
1000 out <<= 7;
1001 out >>= 7;
1002 }
1003 else
1004 {
1005 out = chip->ch_lock;
1006 }
1007 chip->mol = 0;
1008 chip->mor = 0;
1009
1010 if (chip_type & ym3438_mode_ym2612)
1011 {
1012 out_en = ((cycles & 3) == 3) || test_dac;
1013 /* YM2612 DAC emulation(not verified) */
1014 sign = out >> 8;
1015 if (out >= 0)
1016 {
1017 out++;
1018 sign++;
1019 }
1020 if (chip->ch_lock_l && out_en)
1021 {
1022 chip->mol = out;
1023 }
1024 else
1025 {
1026 chip->mol = sign;
1027 }
1028 if (chip->ch_lock_r && out_en)
1029 {
1030 chip->mor = out;
1031 }
1032 else
1033 {
1034 chip->mor = sign;
1035 }
1036 /* Amplify signal */
1037 chip->mol *= 3;
1038 chip->mor *= 3;
1039 }
1040 else
1041 {
1042 out_en = ((cycles & 3) != 0) || test_dac;
1043 if (chip->ch_lock_l && out_en)
1044 {
1045 chip->mol = out;
1046 }
1047 if (chip->ch_lock_r && out_en)
1048 {
1049 chip->mor = out;
1050 }
1051 }
1052 }
1053
OPN2_FMGenerate(ym3438_t * chip)1054 void OPN2_FMGenerate(ym3438_t *chip)
1055 {
1056 Bit32u slot = (chip->cycles + 19) % 24;
1057 /* Calculate phase */
1058 Bit16u phase = (chip->fm_mod[slot] + (chip->pg_phase[slot] >> 10)) & 0x3ff;
1059 Bit16u quarter;
1060 Bit16u level;
1061 Bit16s output;
1062 if (phase & 0x100)
1063 {
1064 quarter = (phase ^ 0xff) & 0xff;
1065 }
1066 else
1067 {
1068 quarter = phase & 0xff;
1069 }
1070 level = logsinrom[quarter];
1071 /* Apply envelope */
1072 level += chip->eg_out[slot] << 2;
1073 /* Transform */
1074 if (level > 0x1fff)
1075 {
1076 level = 0x1fff;
1077 }
1078 output = ((exprom[(level & 0xff) ^ 0xff] | 0x400) << 2) >> (level >> 8);
1079 if (phase & 0x200)
1080 {
1081 output = ((~output) ^ (chip->mode_test_21[4] << 13)) + 1;
1082 }
1083 else
1084 {
1085 output = output ^ (chip->mode_test_21[4] << 13);
1086 }
1087 output <<= 2;
1088 output >>= 2;
1089 chip->fm_out[slot] = output;
1090 }
1091
OPN2_DoTimerA(ym3438_t * chip)1092 void OPN2_DoTimerA(ym3438_t *chip)
1093 {
1094 Bit16u time;
1095 Bit8u load;
1096 load = chip->timer_a_overflow;
1097 if (chip->cycles == 2)
1098 {
1099 /* Lock load value */
1100 load |= (!chip->timer_a_load_lock && chip->timer_a_load);
1101 chip->timer_a_load_lock = chip->timer_a_load;
1102 if (chip->mode_csm)
1103 {
1104 /* CSM KeyOn */
1105 chip->mode_kon_csm = load;
1106 }
1107 else
1108 {
1109 chip->mode_kon_csm = 0;
1110 }
1111 }
1112 /* Load counter */
1113 if (chip->timer_a_load_latch)
1114 {
1115 time = chip->timer_a_reg;
1116 }
1117 else
1118 {
1119 time = chip->timer_a_cnt;
1120 }
1121 chip->timer_a_load_latch = load;
1122 /* Increase counter */
1123 if ((chip->cycles == 1 && chip->timer_a_load_lock) || chip->mode_test_21[2])
1124 {
1125 time++;
1126 }
1127 /* Set overflow flag */
1128 if (chip->timer_a_reset)
1129 {
1130 chip->timer_a_reset = 0;
1131 chip->timer_a_overflow_flag = 0;
1132 }
1133 else
1134 {
1135 chip->timer_a_overflow_flag |= chip->timer_a_overflow & chip->timer_a_enable;
1136 }
1137 chip->timer_a_overflow = (time >> 10);
1138 chip->timer_a_cnt = time & 0x3ff;
1139 }
1140
OPN2_DoTimerB(ym3438_t * chip)1141 void OPN2_DoTimerB(ym3438_t *chip)
1142 {
1143 Bit16u time;
1144 Bit8u load;
1145 load = chip->timer_b_overflow;
1146 if (chip->cycles == 2)
1147 {
1148 /* Lock load value */
1149 load |= (!chip->timer_b_load_lock && chip->timer_b_load);
1150 chip->timer_b_load_lock = chip->timer_b_load;
1151 }
1152 /* Load counter */
1153 if (chip->timer_b_load_latch)
1154 {
1155 time = chip->timer_b_reg;
1156 }
1157 else
1158 {
1159 time = chip->timer_b_cnt;
1160 }
1161 chip->timer_b_load_latch = load;
1162 /* Increase counter */
1163 if (chip->cycles == 1)
1164 {
1165 chip->timer_b_subcnt++;
1166 }
1167 if ((chip->timer_b_subcnt == 0x10 && chip->timer_b_load_lock) || chip->mode_test_21[2])
1168 {
1169 time++;
1170 }
1171 chip->timer_b_subcnt &= 0x0f;
1172 /* Set overflow flag */
1173 if (chip->timer_b_reset)
1174 {
1175 chip->timer_b_reset = 0;
1176 chip->timer_b_overflow_flag = 0;
1177 }
1178 else
1179 {
1180 chip->timer_b_overflow_flag |= chip->timer_b_overflow & chip->timer_b_enable;
1181 }
1182 chip->timer_b_overflow = (time >> 8);
1183 chip->timer_b_cnt = time & 0xff;
1184 }
1185
OPN2_KeyOn(ym3438_t * chip)1186 void OPN2_KeyOn(ym3438_t*chip)
1187 {
1188 Bit32u slot = chip->cycles;
1189 Bit32u chan = chip->channel;
1190 /* Key On */
1191 chip->eg_kon_latch[slot] = chip->mode_kon[slot];
1192 chip->eg_kon_csm[slot] = 0;
1193 if (chip->channel == 2 && chip->mode_kon_csm)
1194 {
1195 /* CSM Key On */
1196 chip->eg_kon_latch[slot] = 1;
1197 chip->eg_kon_csm[slot] = 1;
1198 }
1199 if (chip->cycles == chip->mode_kon_channel)
1200 {
1201 /* OP1 */
1202 chip->mode_kon[chan] = chip->mode_kon_operator[0];
1203 /* OP2 */
1204 chip->mode_kon[chan + 12] = chip->mode_kon_operator[1];
1205 /* OP3 */
1206 chip->mode_kon[chan + 6] = chip->mode_kon_operator[2];
1207 /* OP4 */
1208 chip->mode_kon[chan + 18] = chip->mode_kon_operator[3];
1209 }
1210 }
1211
OPN2_Reset(ym3438_t * chip,Bit32u rate,Bit32u clock)1212 void OPN2_Reset(ym3438_t *chip, Bit32u rate, Bit32u clock)
1213 {
1214 Bit32u i, rateratio;
1215 rateratio = (Bit32u)chip->rateratio;
1216 memset(chip, 0, sizeof(ym3438_t));
1217 for (i = 0; i < 24; i++)
1218 {
1219 chip->eg_out[i] = 0x3ff;
1220 chip->eg_level[i] = 0x3ff;
1221 chip->eg_state[i] = eg_num_release;
1222 chip->multi[i] = 1;
1223 }
1224 for (i = 0; i < 6; i++)
1225 {
1226 chip->pan_l[i] = 1;
1227 chip->pan_r[i] = 1;
1228 chip->pan_volume_l[i] = 46340;
1229 chip->pan_volume_r[i] = 46340;
1230 }
1231
1232 if (rate != 0)
1233 {
1234 chip->rateratio = (Bit32s)(Bit32u)((((Bit64u)144 * rate) << RSM_FRAC) / clock);
1235 }
1236 else
1237 {
1238 chip->rateratio = (Bit32s)rateratio;
1239 }
1240 }
1241
OPN2_SetChipType(Bit32u type)1242 void OPN2_SetChipType(Bit32u type)
1243 {
1244 chip_type = type;
1245 }
1246
OPN2_Clock(ym3438_t * chip,Bit16s * buffer)1247 void OPN2_Clock(ym3438_t *chip, Bit16s *buffer)
1248 {
1249 Bit32u slot = chip->cycles;
1250 chip->lfo_inc = chip->mode_test_21[1];
1251 chip->pg_read >>= 1;
1252 chip->eg_read[1] >>= 1;
1253 chip->eg_cycle++;
1254 /* Lock envelope generator timer value */
1255 if (chip->cycles == 1 && chip->eg_quotient == 2)
1256 {
1257 if (chip->eg_cycle_stop)
1258 {
1259 chip->eg_shift_lock = 0;
1260 }
1261 else
1262 {
1263 chip->eg_shift_lock = chip->eg_shift + 1;
1264 }
1265 chip->eg_timer_low_lock = chip->eg_timer & 0x03;
1266 }
1267 /* Cycle specific functions */
1268 switch (chip->cycles)
1269 {
1270 case 0:
1271 chip->lfo_pm = chip->lfo_cnt >> 2;
1272 if (chip->lfo_cnt & 0x40)
1273 {
1274 chip->lfo_am = chip->lfo_cnt & 0x3f;
1275 }
1276 else
1277 {
1278 chip->lfo_am = chip->lfo_cnt ^ 0x3f;
1279 }
1280 chip->lfo_am <<= 1;
1281 break;
1282 case 1:
1283 chip->eg_quotient++;
1284 chip->eg_quotient %= 3;
1285 chip->eg_cycle = 0;
1286 chip->eg_cycle_stop = 1;
1287 chip->eg_shift = 0;
1288 chip->eg_timer_inc |= chip->eg_quotient >> 1;
1289 chip->eg_timer = chip->eg_timer + chip->eg_timer_inc;
1290 chip->eg_timer_inc = chip->eg_timer >> 12;
1291 chip->eg_timer &= 0xfff;
1292 break;
1293 case 2:
1294 chip->pg_read = chip->pg_phase[21] & 0x3ff;
1295 chip->eg_read[1] = chip->eg_out[0];
1296 break;
1297 case 13:
1298 chip->eg_cycle = 0;
1299 chip->eg_cycle_stop = 1;
1300 chip->eg_shift = 0;
1301 chip->eg_timer = chip->eg_timer + chip->eg_timer_inc;
1302 chip->eg_timer_inc = chip->eg_timer >> 12;
1303 chip->eg_timer &= 0xfff;
1304 break;
1305 case 23:
1306 chip->lfo_inc |= 1;
1307 break;
1308 }
1309 chip->eg_timer &= ~(chip->mode_test_21[5] << chip->eg_cycle);
1310 if (((chip->eg_timer >> chip->eg_cycle) | (chip->pin_test_in & chip->eg_custom_timer)) & chip->eg_cycle_stop)
1311 {
1312 chip->eg_shift = chip->eg_cycle;
1313 chip->eg_cycle_stop = 0;
1314 }
1315
1316 OPN2_DoIO(chip);
1317
1318 OPN2_DoTimerA(chip);
1319 OPN2_DoTimerB(chip);
1320 OPN2_KeyOn(chip);
1321
1322 OPN2_ChOutput(chip);
1323 OPN2_ChGenerate(chip);
1324
1325 OPN2_FMPrepare(chip);
1326 OPN2_FMGenerate(chip);
1327
1328 OPN2_PhaseGenerate(chip);
1329 OPN2_PhaseCalcIncrement(chip);
1330
1331 OPN2_EnvelopeADSR(chip);
1332 OPN2_EnvelopeGenerate(chip);
1333 OPN2_EnvelopeSSGEG(chip);
1334 OPN2_EnvelopePrepare(chip);
1335
1336 /* Prepare fnum & block */
1337 if (chip->mode_ch3)
1338 {
1339 /* Channel 3 special mode */
1340 switch (slot)
1341 {
1342 case 1: /* OP1 */
1343 chip->pg_fnum = chip->fnum_3ch[1];
1344 chip->pg_block = chip->block_3ch[1];
1345 chip->pg_kcode = chip->kcode_3ch[1];
1346 break;
1347 case 7: /* OP3 */
1348 chip->pg_fnum = chip->fnum_3ch[0];
1349 chip->pg_block = chip->block_3ch[0];
1350 chip->pg_kcode = chip->kcode_3ch[0];
1351 break;
1352 case 13: /* OP2 */
1353 chip->pg_fnum = chip->fnum_3ch[2];
1354 chip->pg_block = chip->block_3ch[2];
1355 chip->pg_kcode = chip->kcode_3ch[2];
1356 break;
1357 case 19: /* OP4 */
1358 default:
1359 chip->pg_fnum = chip->fnum[(chip->channel + 1) % 6];
1360 chip->pg_block = chip->block[(chip->channel + 1) % 6];
1361 chip->pg_kcode = chip->kcode[(chip->channel + 1) % 6];
1362 break;
1363 }
1364 }
1365 else
1366 {
1367 chip->pg_fnum = chip->fnum[(chip->channel + 1) % 6];
1368 chip->pg_block = chip->block[(chip->channel + 1) % 6];
1369 chip->pg_kcode = chip->kcode[(chip->channel + 1) % 6];
1370 }
1371
1372 OPN2_UpdateLFO(chip);
1373 OPN2_DoRegWrite(chip);
1374 chip->cycles = (chip->cycles + 1) % 24;
1375 chip->channel = chip->cycles % 6;
1376
1377 buffer[0] = chip->mol;
1378 buffer[1] = chip->mor;
1379
1380 if (chip->status_time)
1381 chip->status_time--;
1382 }
1383
OPN2_Write(ym3438_t * chip,Bit32u port,Bit8u data)1384 void OPN2_Write(ym3438_t *chip, Bit32u port, Bit8u data)
1385 {
1386 port &= 3;
1387 chip->write_data = ((port << 7) & 0x100) | data;
1388 if (port & 1)
1389 {
1390 /* Data */
1391 chip->write_d |= 1;
1392 }
1393 else
1394 {
1395 /* Address */
1396 chip->write_a |= 1;
1397 }
1398 }
1399
OPN2_SetTestPin(ym3438_t * chip,Bit32u value)1400 void OPN2_SetTestPin(ym3438_t *chip, Bit32u value)
1401 {
1402 chip->pin_test_in = value & 1;
1403 }
1404
OPN2_ReadTestPin(ym3438_t * chip)1405 Bit32u OPN2_ReadTestPin(ym3438_t *chip)
1406 {
1407 if (!chip->mode_test_2c[7])
1408 {
1409 return 0;
1410 }
1411 return chip->cycles == 23;
1412 }
1413
OPN2_ReadIRQPin(ym3438_t * chip)1414 Bit32u OPN2_ReadIRQPin(ym3438_t *chip)
1415 {
1416 return chip->timer_a_overflow_flag | chip->timer_b_overflow_flag;
1417 }
1418
OPN2_Read(ym3438_t * chip,Bit32u port)1419 Bit8u OPN2_Read(ym3438_t *chip, Bit32u port)
1420 {
1421 if ((port & 3) == 0 || (chip_type & ym3438_mode_readmode))
1422 {
1423 if (chip->mode_test_21[6])
1424 {
1425 /* Read test data */
1426 Bit32u slot = (chip->cycles + 18) % 24;
1427 Bit16u testdata = ((chip->pg_read & 0x01) << 15)
1428 | ((chip->eg_read[chip->mode_test_21[0]] & 0x01) << 14);
1429 if (chip->mode_test_2c[4])
1430 {
1431 testdata |= chip->ch_read & 0x1ff;
1432 }
1433 else
1434 {
1435 testdata |= chip->fm_out[slot] & 0x3fff;
1436 }
1437 if (chip->mode_test_21[7])
1438 {
1439 chip->status = testdata & 0xff;
1440 }
1441 else
1442 {
1443 chip->status = testdata >> 8;
1444 }
1445 }
1446 else
1447 {
1448 chip->status = (chip->busy << 7) | (chip->timer_b_overflow_flag << 1)
1449 | chip->timer_a_overflow_flag;
1450 }
1451 if (chip_type & ym3438_mode_ym2612)
1452 {
1453 chip->status_time = 300000;
1454 }
1455 else
1456 {
1457 chip->status_time = 40000000;
1458 }
1459 }
1460 if (chip->status_time)
1461 {
1462 return chip->status;
1463 }
1464 return 0;
1465 }
1466
OPN2_WritePan(ym3438_t * chip,Bit32u channel,Bit8u data)1467 void OPN2_WritePan(ym3438_t *chip, Bit32u channel, Bit8u data)
1468 {
1469 chip->pan_volume_l[channel] = panlawtable[data & 0x7F];
1470 chip->pan_volume_r[channel] = panlawtable[0x7F - (data & 0x7F)];
1471 }
1472
OPN2_WriteBuffered(ym3438_t * chip,Bit32u port,Bit8u data)1473 void OPN2_WriteBuffered(ym3438_t *chip, Bit32u port, Bit8u data)
1474 {
1475 Bit64u time1, time2;
1476 Bit16s buffer[2];
1477 Bit64u skip;
1478
1479 if (chip->writebuf[chip->writebuf_last].port & 0x04)
1480 {
1481 OPN2_Write(chip, chip->writebuf[chip->writebuf_last].port & 0X03,
1482 chip->writebuf[chip->writebuf_last].data);
1483
1484 chip->writebuf_cur = (chip->writebuf_last + 1) % OPN_WRITEBUF_SIZE;
1485 skip = chip->writebuf[chip->writebuf_last].time - chip->writebuf_samplecnt;
1486 chip->writebuf_samplecnt = chip->writebuf[chip->writebuf_last].time;
1487 while (skip--)
1488 {
1489 OPN2_Clock(chip, buffer);
1490 }
1491 }
1492
1493 chip->writebuf[chip->writebuf_last].port = (port & 0x03) | 0x04;
1494 chip->writebuf[chip->writebuf_last].data = data;
1495 time1 = chip->writebuf_lasttime + OPN_WRITEBUF_DELAY;
1496 time2 = chip->writebuf_samplecnt;
1497
1498 if (time1 < time2)
1499 {
1500 time1 = time2;
1501 }
1502
1503 chip->writebuf[chip->writebuf_last].time = time1;
1504 chip->writebuf_lasttime = time1;
1505 chip->writebuf_last = (chip->writebuf_last + 1) % OPN_WRITEBUF_SIZE;
1506 }
1507
OPN2_Generate(ym3438_t * chip,Bit16s * buf)1508 void OPN2_Generate(ym3438_t *chip, Bit16s *buf)
1509 {
1510 Bit32u i;
1511 Bit16s buffer[2];
1512 Bit32u mute;
1513 Bit32s channel = -1;
1514
1515 buf[0] = 0;
1516 buf[1] = 0;
1517
1518 for (i = 0; i < 24; i++)
1519 {
1520 switch (chip->cycles >> 2)
1521 {
1522 case 0: /* Ch 2 */
1523 mute = chip->mute[1];
1524 channel = 1;
1525 break;
1526 case 1: /* Ch 6, DAC */
1527 mute = chip->mute[5 + chip->dacen];
1528 channel = 5;
1529 break;
1530 case 2: /* Ch 4 */
1531 mute = chip->mute[3];
1532 channel = 3;
1533 break;
1534 case 3: /* Ch 1 */
1535 mute = chip->mute[0];
1536 channel = 0;
1537 break;
1538 case 4: /* Ch 5 */
1539 mute = chip->mute[4];
1540 channel = 4;
1541 break;
1542 case 5: /* Ch 3 */
1543 mute = chip->mute[2];
1544 channel = 2;
1545 break;
1546 default:
1547 mute = 0;
1548 break;
1549 }
1550 OPN2_Clock(chip, buffer);
1551 if (!mute)
1552 {
1553 if (channel >= 0)
1554 {
1555 buffer[0] = buffer[0] * chip->pan_volume_l[channel] / 65535;
1556 buffer[1] = buffer[1] * chip->pan_volume_r[channel] / 65535;
1557 }
1558 buf[0] += buffer[0];
1559 buf[1] += buffer[1];
1560 }
1561
1562 while (chip->writebuf[chip->writebuf_cur].time <= chip->writebuf_samplecnt)
1563 {
1564 if (!(chip->writebuf[chip->writebuf_cur].port & 0x04))
1565 {
1566 break;
1567 }
1568 chip->writebuf[chip->writebuf_cur].port &= 0x03;
1569 OPN2_Write(chip, chip->writebuf[chip->writebuf_cur].port,
1570 chip->writebuf[chip->writebuf_cur].data);
1571 chip->writebuf_cur = (chip->writebuf_cur + 1) % OPN_WRITEBUF_SIZE;
1572 }
1573 chip->writebuf_samplecnt++;
1574 }
1575 }
1576
OPN2_GenerateResampled(ym3438_t * chip,Bit16s * buf)1577 void OPN2_GenerateResampled(ym3438_t *chip, Bit16s *buf)
1578 {
1579 Bit16s buffer[2];
1580
1581 while (chip->samplecnt >= chip->rateratio)
1582 {
1583 chip->oldsamples[0] = chip->samples[0];
1584 chip->oldsamples[1] = chip->samples[1];
1585 OPN2_Generate(chip, buffer);
1586 chip->samples[0] = buffer[0] * 11;
1587 chip->samples[1] = buffer[1] * 11;
1588 chip->samplecnt -= chip->rateratio;
1589 }
1590 buf[0] = (Bit16s)(((chip->oldsamples[0] * (chip->rateratio - chip->samplecnt)
1591 + chip->samples[0] * chip->samplecnt) / chip->rateratio)>>1);
1592 buf[1] = (Bit16s)(((chip->oldsamples[1] * (chip->rateratio - chip->samplecnt)
1593 + chip->samples[1] * chip->samplecnt) / chip->rateratio)>>1);
1594 chip->samplecnt += 1 << RSM_FRAC;
1595 }
1596
OPN2_GenerateStream(ym3438_t * chip,Bit16s * output,Bit32u numsamples)1597 void OPN2_GenerateStream(ym3438_t *chip, Bit16s *output, Bit32u numsamples)
1598 {
1599 Bit32u i;
1600 Bit16s buffer[2];
1601
1602 for (i = 0; i < numsamples; i++)
1603 {
1604 OPN2_GenerateResampled(chip, buffer);
1605 *output++ = buffer[0];
1606 *output++ = buffer[1];
1607 }
1608 }
1609
OPN2_GenerateStreamMix(ym3438_t * chip,Bit16s * output,Bit32u numsamples)1610 void OPN2_GenerateStreamMix(ym3438_t *chip, Bit16s *output, Bit32u numsamples)
1611 {
1612 Bit32u i;
1613 Bit16s buffer[2];
1614
1615 for (i = 0; i < numsamples; i++)
1616 {
1617 OPN2_GenerateResampled(chip, buffer);
1618 *output++ += buffer[0];
1619 *output++ += buffer[1];
1620 }
1621 }
1622
OPN2_SetMute(ym3438_t * chip,Bit32u mute)1623 void OPN2_SetMute(ym3438_t *chip, Bit32u mute)
1624 {
1625 Bit32u i;
1626 for (i = 0; i < 7; i++)
1627 {
1628 chip->mute[i] = (mute >> i) & 0x01;
1629 }
1630 }
1631