1 /*
2 ** Definitions for ARM64 CPUs.
3 ** Copyright (C) 2005-2017 Mike Pall. See Copyright Notice in luajit.h
4 */
5
6 #ifndef _LJ_TARGET_ARM64_H
7 #define _LJ_TARGET_ARM64_H
8
9 /* -- Registers IDs ------------------------------------------------------- */
10
11 #define GPRDEF(_) \
12 _(X0) _(X1) _(X2) _(X3) _(X4) _(X5) _(X6) _(X7) \
13 _(X8) _(X9) _(X10) _(X11) _(X12) _(X13) _(X14) _(X15) \
14 _(X16) _(X17) _(X18) _(X19) _(X20) _(X21) _(X22) _(X23) \
15 _(X24) _(X25) _(X26) _(X27) _(X28) _(FP) _(LR) _(SP)
16 #define FPRDEF(_) \
17 _(D0) _(D1) _(D2) _(D3) _(D4) _(D5) _(D6) _(D7) \
18 _(D8) _(D9) _(D10) _(D11) _(D12) _(D13) _(D14) _(D15) \
19 _(D16) _(D17) _(D18) _(D19) _(D20) _(D21) _(D22) _(D23) \
20 _(D24) _(D25) _(D26) _(D27) _(D28) _(D29) _(D30) _(D31)
21 #define VRIDDEF(_)
22
23 #define RIDENUM(name) RID_##name,
24
25 enum {
26 GPRDEF(RIDENUM) /* General-purpose registers (GPRs). */
27 FPRDEF(RIDENUM) /* Floating-point registers (FPRs). */
28 RID_MAX,
29 RID_TMP = RID_LR,
30 RID_ZERO = RID_SP,
31
32 /* Calling conventions. */
33 RID_RET = RID_X0,
34 RID_FPRET = RID_D0,
35
36 /* These definitions must match with the *.dasc file(s): */
37 RID_BASE = RID_X19, /* Interpreter BASE. */
38 RID_LPC = RID_X21, /* Interpreter PC. */
39 RID_GL = RID_X22, /* Interpreter GL. */
40 RID_LREG = RID_X23, /* Interpreter L. */
41
42 /* Register ranges [min, max) and number of registers. */
43 RID_MIN_GPR = RID_X0,
44 RID_MAX_GPR = RID_SP+1,
45 RID_MIN_FPR = RID_MAX_GPR,
46 RID_MAX_FPR = RID_D31+1,
47 RID_NUM_GPR = RID_MAX_GPR - RID_MIN_GPR,
48 RID_NUM_FPR = RID_MAX_FPR - RID_MIN_FPR
49 };
50
51 #define RID_NUM_KREF RID_NUM_GPR
52 #define RID_MIN_KREF RID_X0
53
54 /* -- Register sets ------------------------------------------------------- */
55
56 /* Make use of all registers, except for x18, fp, lr and sp. */
57 #define RSET_FIXED \
58 (RID2RSET(RID_X18)|RID2RSET(RID_FP)|RID2RSET(RID_LR)|RID2RSET(RID_SP)|\
59 RID2RSET(RID_GL))
60 #define RSET_GPR (RSET_RANGE(RID_MIN_GPR, RID_MAX_GPR) - RSET_FIXED)
61 #define RSET_FPR RSET_RANGE(RID_MIN_FPR, RID_MAX_FPR)
62 #define RSET_ALL (RSET_GPR|RSET_FPR)
63 #define RSET_INIT RSET_ALL
64
65 /* lr is an implicit scratch register. */
66 #define RSET_SCRATCH_GPR (RSET_RANGE(RID_X0, RID_X17+1))
67 #define RSET_SCRATCH_FPR \
68 (RSET_RANGE(RID_D0, RID_D7+1)|RSET_RANGE(RID_D16, RID_D31+1))
69 #define RSET_SCRATCH (RSET_SCRATCH_GPR|RSET_SCRATCH_FPR)
70 #define REGARG_FIRSTGPR RID_X0
71 #define REGARG_LASTGPR RID_X7
72 #define REGARG_NUMGPR 8
73 #define REGARG_FIRSTFPR RID_D0
74 #define REGARG_LASTFPR RID_D7
75 #define REGARG_NUMFPR 8
76
77 /* -- Spill slots --------------------------------------------------------- */
78
79 /* Spill slots are 32 bit wide. An even/odd pair is used for FPRs.
80 **
81 ** SPS_FIXED: Available fixed spill slots in interpreter frame.
82 ** This definition must match with the vm_arm64.dasc file.
83 ** Pre-allocate some slots to avoid sp adjust in every root trace.
84 **
85 ** SPS_FIRST: First spill slot for general use. Reserve min. two 32 bit slots.
86 */
87 #define SPS_FIXED 4
88 #define SPS_FIRST 2
89
90 #define SPOFS_TMP 0
91
92 #define sps_scale(slot) (4 * (int32_t)(slot))
93 #define sps_align(slot) (((slot) - SPS_FIXED + 3) & ~3)
94
95 /* -- Exit state ---------------------------------------------------------- */
96
97 /* This definition must match with the *.dasc file(s). */
98 typedef struct {
99 lua_Number fpr[RID_NUM_FPR]; /* Floating-point registers. */
100 intptr_t gpr[RID_NUM_GPR]; /* General-purpose registers. */
101 int32_t spill[256]; /* Spill slots. */
102 } ExitState;
103
104 /* Highest exit + 1 indicates stack check. */
105 #define EXITSTATE_CHECKEXIT 1
106
107 /* Return the address of a per-trace exit stub. */
exitstub_trace_addr_(uint32_t * p,uint32_t exitno)108 static LJ_AINLINE uint32_t *exitstub_trace_addr_(uint32_t *p, uint32_t exitno)
109 {
110 while (*p == 0xd503201f) p++; /* Skip A64I_NOP. */
111 return p + 3 + exitno;
112 }
113 /* Avoid dependence on lj_jit.h if only including lj_target.h. */
114 #define exitstub_trace_addr(T, exitno) \
115 exitstub_trace_addr_((MCode *)((char *)(T)->mcode + (T)->szmcode), (exitno))
116
117 /* -- Instructions -------------------------------------------------------- */
118
119 /* Instruction fields. */
120 #define A64F_D(r) (r)
121 #define A64F_N(r) ((r) << 5)
122 #define A64F_A(r) ((r) << 10)
123 #define A64F_M(r) ((r) << 16)
124 #define A64F_IMMS(x) ((x) << 10)
125 #define A64F_IMMR(x) ((x) << 16)
126 #define A64F_U16(x) ((x) << 5)
127 #define A64F_U12(x) ((x) << 10)
128 #define A64F_S26(x) (x)
129 #define A64F_S19(x) (((uint32_t)(x) & 0x7ffffu) << 5)
130 #define A64F_S14(x) ((x) << 5)
131 #define A64F_S9(x) ((x) << 12)
132 #define A64F_BIT(x) ((x) << 19)
133 #define A64F_SH(sh, x) (((sh) << 22) | ((x) << 10))
134 #define A64F_EX(ex) (A64I_EX | ((ex) << 13))
135 #define A64F_EXSH(ex,x) (A64I_EX | ((ex) << 13) | ((x) << 10))
136 #define A64F_FP8(x) ((x) << 13)
137 #define A64F_CC(cc) ((cc) << 12)
138 #define A64F_LSL16(x) (((x) / 16) << 21)
139 #define A64F_BSH(sh) ((sh) << 10)
140
141 typedef enum A64Ins {
142 A64I_S = 0x20000000,
143 A64I_X = 0x80000000,
144 A64I_EX = 0x00200000,
145 A64I_ON = 0x00200000,
146 A64I_K12 = 0x1a000000,
147 A64I_K13 = 0x18000000,
148 A64I_LS_U = 0x01000000,
149 A64I_LS_S = 0x00800000,
150 A64I_LS_R = 0x01200800,
151 A64I_LS_SH = 0x00001000,
152 A64I_LS_UXTWx = 0x00004000,
153 A64I_LS_SXTWx = 0x0000c000,
154 A64I_LS_SXTXx = 0x0000e000,
155 A64I_LS_LSLx = 0x00006000,
156
157 A64I_ADDw = 0x0b000000,
158 A64I_ADDx = 0x8b000000,
159 A64I_ADDSw = 0x2b000000,
160 A64I_ADDSx = 0xab000000,
161 A64I_NEGw = 0x4b0003e0,
162 A64I_NEGx = 0xcb0003e0,
163 A64I_SUBw = 0x4b000000,
164 A64I_SUBx = 0xcb000000,
165 A64I_SUBSw = 0x6b000000,
166 A64I_SUBSx = 0xeb000000,
167
168 A64I_MULw = 0x1b007c00,
169 A64I_MULx = 0x9b007c00,
170 A64I_SMULL = 0x9b207c00,
171
172 A64I_ANDw = 0x0a000000,
173 A64I_ANDx = 0x8a000000,
174 A64I_ANDSw = 0x6a000000,
175 A64I_ANDSx = 0xea000000,
176 A64I_EORw = 0x4a000000,
177 A64I_EORx = 0xca000000,
178 A64I_ORRw = 0x2a000000,
179 A64I_ORRx = 0xaa000000,
180 A64I_TSTw = 0x6a00001f,
181 A64I_TSTx = 0xea00001f,
182
183 A64I_CMPw = 0x6b00001f,
184 A64I_CMPx = 0xeb00001f,
185 A64I_CMNw = 0x2b00001f,
186 A64I_CMNx = 0xab00001f,
187 A64I_CCMPw = 0x7a400000,
188 A64I_CCMPx = 0xfa400000,
189 A64I_CSELw = 0x1a800000,
190 A64I_CSELx = 0x9a800000,
191
192 A64I_ASRw = 0x13007c00,
193 A64I_ASRx = 0x9340fc00,
194 A64I_LSLx = 0xd3400000,
195 A64I_LSRx = 0xd340fc00,
196 A64I_SHRw = 0x1ac02000,
197 A64I_SHRx = 0x9ac02000, /* lsl/lsr/asr/ror x0, x0, x0 */
198 A64I_REVw = 0x5ac00800,
199 A64I_REVx = 0xdac00c00,
200
201 A64I_EXTRw = 0x13800000,
202 A64I_EXTRx = 0x93c00000,
203 A64I_SBFMw = 0x13000000,
204 A64I_SBFMx = 0x93400000,
205 A64I_SXTBw = 0x13001c00,
206 A64I_SXTHw = 0x13003c00,
207 A64I_SXTW = 0x93407c00,
208 A64I_UBFMw = 0x53000000,
209 A64I_UBFMx = 0xd3400000,
210 A64I_UXTBw = 0x53001c00,
211 A64I_UXTHw = 0x53003c00,
212
213 A64I_MOVw = 0x2a0003e0,
214 A64I_MOVx = 0xaa0003e0,
215 A64I_MVNw = 0x2a2003e0,
216 A64I_MVNx = 0xaa2003e0,
217 A64I_MOVKw = 0x72800000,
218 A64I_MOVKx = 0xf2800000,
219 A64I_MOVZw = 0x52800000,
220 A64I_MOVZx = 0xd2800000,
221 A64I_MOVNw = 0x12800000,
222 A64I_MOVNx = 0x92800000,
223
224 A64I_LDRB = 0x39400000,
225 A64I_LDRH = 0x79400000,
226 A64I_LDRw = 0xb9400000,
227 A64I_LDRx = 0xf9400000,
228 A64I_LDRLw = 0x18000000,
229 A64I_LDRLx = 0x58000000,
230 A64I_STRB = 0x39000000,
231 A64I_STRH = 0x79000000,
232 A64I_STRw = 0xb9000000,
233 A64I_STRx = 0xf9000000,
234 A64I_STPw = 0x29000000,
235 A64I_STPx = 0xa9000000,
236 A64I_LDPw = 0x29400000,
237 A64I_LDPx = 0xa9400000,
238
239 A64I_B = 0x14000000,
240 A64I_BCC = 0x54000000,
241 A64I_BL = 0x94000000,
242 A64I_BR = 0xd61f0000,
243 A64I_BLR = 0xd63f0000,
244 A64I_TBZ = 0x36000000,
245 A64I_TBNZ = 0x37000000,
246 A64I_CBZ = 0x34000000,
247 A64I_CBNZ = 0x35000000,
248
249 A64I_NOP = 0xd503201f,
250
251 /* FP */
252 A64I_FADDd = 0x1e602800,
253 A64I_FSUBd = 0x1e603800,
254 A64I_FMADDd = 0x1f400000,
255 A64I_FMSUBd = 0x1f408000,
256 A64I_FNMADDd = 0x1f600000,
257 A64I_FNMSUBd = 0x1f608000,
258 A64I_FMULd = 0x1e600800,
259 A64I_FDIVd = 0x1e601800,
260 A64I_FNEGd = 0x1e614000,
261 A64I_FABS = 0x1e60c000,
262 A64I_FSQRTd = 0x1e61c000,
263 A64I_LDRs = 0xbd400000,
264 A64I_LDRd = 0xfd400000,
265 A64I_STRs = 0xbd000000,
266 A64I_STRd = 0xfd000000,
267 A64I_LDPs = 0x2d400000,
268 A64I_LDPd = 0x6d400000,
269 A64I_STPs = 0x2d000000,
270 A64I_STPd = 0x6d000000,
271 A64I_FCMPd = 0x1e602000,
272 A64I_FCMPZd = 0x1e602008,
273 A64I_FCSELd = 0x1e600c00,
274 A64I_FRINTMd = 0x1e654000,
275 A64I_FRINTPd = 0x1e64c000,
276 A64I_FRINTZd = 0x1e65c000,
277
278 A64I_FCVT_F32_F64 = 0x1e624000,
279 A64I_FCVT_F64_F32 = 0x1e22c000,
280 A64I_FCVT_F32_S32 = 0x1e220000,
281 A64I_FCVT_F64_S32 = 0x1e620000,
282 A64I_FCVT_F32_U32 = 0x1e230000,
283 A64I_FCVT_F64_U32 = 0x1e630000,
284 A64I_FCVT_F32_S64 = 0x9e220000,
285 A64I_FCVT_F64_S64 = 0x9e620000,
286 A64I_FCVT_F32_U64 = 0x9e230000,
287 A64I_FCVT_F64_U64 = 0x9e630000,
288 A64I_FCVT_S32_F64 = 0x1e780000,
289 A64I_FCVT_S32_F32 = 0x1e380000,
290 A64I_FCVT_U32_F64 = 0x1e790000,
291 A64I_FCVT_U32_F32 = 0x1e390000,
292 A64I_FCVT_S64_F64 = 0x9e780000,
293 A64I_FCVT_S64_F32 = 0x9e380000,
294 A64I_FCVT_U64_F64 = 0x9e790000,
295 A64I_FCVT_U64_F32 = 0x9e390000,
296
297 A64I_FMOV_S = 0x1e204000,
298 A64I_FMOV_D = 0x1e604000,
299 A64I_FMOV_R_S = 0x1e260000,
300 A64I_FMOV_S_R = 0x1e270000,
301 A64I_FMOV_R_D = 0x9e660000,
302 A64I_FMOV_D_R = 0x9e670000,
303 A64I_FMOV_DI = 0x1e601000,
304 } A64Ins;
305
306 typedef enum A64Shift {
307 A64SH_LSL, A64SH_LSR, A64SH_ASR, A64SH_ROR
308 } A64Shift;
309
310 typedef enum A64Extend {
311 A64EX_UXTB, A64EX_UXTH, A64EX_UXTW, A64EX_UXTX,
312 A64EX_SXTB, A64EX_SXTH, A64EX_SXTW, A64EX_SXTX,
313 } A64Extend;
314
315 /* ARM condition codes. */
316 typedef enum A64CC {
317 CC_EQ, CC_NE, CC_CS, CC_CC, CC_MI, CC_PL, CC_VS, CC_VC,
318 CC_HI, CC_LS, CC_GE, CC_LT, CC_GT, CC_LE, CC_AL,
319 CC_HS = CC_CS, CC_LO = CC_CC
320 } A64CC;
321
322 #endif
323