1 2---------------------------------------------------------------- 3-- 4-- Created by the Synopsys Library Compiler 1999.10 5-- FILENAME : sxlib_FTSM.vhd 6-- FILE CONTENTS: Entity, Structural Architecture(FTSM), 7-- and Configuration 8-- DATE CREATED : Mon May 7 10:19:50 2001 9-- 10-- LIBRARY : sxlib 11-- DATE ENTERED : Thu Dec 21 11:24:55 MET 2000 12-- REVISION : 1.200000 13-- TECHNOLOGY : cmos 14-- TIME SCALE : 1 ns 15-- LOGIC SYSTEM : IEEE-1164 16-- NOTES : FTSM, Timing_mesg(TRUE) 17-- HISTORY : 18-- 19---------------------------------------------------------------- 20 21----- CELL a2_x2 ----- 22library IEEE; 23use IEEE.STD_LOGIC_1164.all; 24library SYNOPSYS; 25use SYNOPSYS.attributes.REAL_NAME; 26 27-- entity declaration -- 28entity a2_x2 is 29 generic( 30 Timing_mesg: Boolean := True; 31 Timing_xgen: Boolean := False; 32 tpdi0_q_R : Time := 0.261 ns; 33 tpdi0_q_F : Time := 0.388 ns; 34 tpdi1_q_R : Time := 0.203 ns; 35 tpdi1_q_F : Time := 0.434 ns; 36 twdi0_R : Time := 0.000 ns; 37 twdi0_F : Time := 0.000 ns; 38 twdi1_R : Time := 0.000 ns; 39 twdi1_F : Time := 0.000 ns); 40 41 port( 42 i0 : in STD_LOGIC; 43 i1 : in STD_LOGIC; 44 q : out STD_LOGIC); 45end a2_x2; 46 47-- architecture body -- 48library IEEE_ASIC; 49use IEEE.STD_LOGIC_MISC.all; 50use SYNOPSYS.attributes.backplane; 51use SYNOPSYS.attributes.PRIVATE; 52use SYNOPSYS.attributes.ASIC_CELL; 53use SYNOPSYS.attributes.PROPAGATE_VALUE; 54 55architecture FTSM of a2_x2 is 56 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 57 attribute PRIVATE of FTSM : architecture is TRUE; 58 attribute ASIC_CELL of FTSM : architecture is TRUE; 59 60 -- Backannotation attributes 61 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; 62 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; 63 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tLH"; 64 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tHL"; 65 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 66 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 67 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 68 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 69 70 signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 71 signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 72 73 component AND2MAC 74 generic( 75 tpdY_R : Time := 0 ns; 76 tpdY_F : Time := 0 ns; 77 strn : STRENGTH := strn_X01); 78 port( 79 I0 : in STD_LOGIC; 80 I1 : in STD_LOGIC; 81 Y : out STD_LOGIC); 82 end component; 83 84begin 85 86 -- Extrinsic delay buffers 87 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 88 generic map( tLH => twdi0_R, tHL => twdi0_F) 89 port map( Input => i0, Output => connect(0)); 90 91 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 92 generic map( tLH => twdi1_R, tHL => twdi1_F) 93 port map( Input => i1, Output => connect(1)); 94 95 -- Intrinsic delay buffers 96 U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 97 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 98 port map( Input => connect(0), Output => prop_q(0)); 99 100 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 101 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 102 port map( Input => connect(1), Output => prop_q(1)); 103 104 -- Netlist 105 U5 : AND2MAC 106 port map( I0 => prop_q(0), I1 => prop_q(1), Y => q); 107 108 109end FTSM; 110 111configuration CFG_a2_x2_FTSM of a2_x2 is 112 for FTSM 113 end for; 114end CFG_a2_x2_FTSM; 115 116 117----- CELL a2_x4 ----- 118library IEEE; 119use IEEE.STD_LOGIC_1164.all; 120library SYNOPSYS; 121use SYNOPSYS.attributes.REAL_NAME; 122 123-- entity declaration -- 124entity a2_x4 is 125 generic( 126 Timing_mesg: Boolean := True; 127 Timing_xgen: Boolean := False; 128 tpdi0_q_R : Time := 0.338 ns; 129 tpdi0_q_F : Time := 0.476 ns; 130 tpdi1_q_R : Time := 0.269 ns; 131 tpdi1_q_F : Time := 0.518 ns; 132 twdi0_R : Time := 0.000 ns; 133 twdi0_F : Time := 0.000 ns; 134 twdi1_R : Time := 0.000 ns; 135 twdi1_F : Time := 0.000 ns); 136 137 port( 138 i0 : in STD_LOGIC; 139 i1 : in STD_LOGIC; 140 q : out STD_LOGIC); 141end a2_x4; 142 143-- architecture body -- 144library IEEE_ASIC; 145use IEEE.STD_LOGIC_MISC.all; 146use SYNOPSYS.attributes.backplane; 147use SYNOPSYS.attributes.PRIVATE; 148use SYNOPSYS.attributes.ASIC_CELL; 149use SYNOPSYS.attributes.PROPAGATE_VALUE; 150 151architecture FTSM of a2_x4 is 152 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 153 attribute PRIVATE of FTSM : architecture is TRUE; 154 attribute ASIC_CELL of FTSM : architecture is TRUE; 155 156 -- Backannotation attributes 157 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; 158 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; 159 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tLH"; 160 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tHL"; 161 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 162 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 163 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 164 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 165 166 signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 167 signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 168 169 component AND2MAC 170 generic( 171 tpdY_R : Time := 0 ns; 172 tpdY_F : Time := 0 ns; 173 strn : STRENGTH := strn_X01); 174 port( 175 I0 : in STD_LOGIC; 176 I1 : in STD_LOGIC; 177 Y : out STD_LOGIC); 178 end component; 179 180begin 181 182 -- Extrinsic delay buffers 183 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 184 generic map( tLH => twdi0_R, tHL => twdi0_F) 185 port map( Input => i0, Output => connect(0)); 186 187 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 188 generic map( tLH => twdi1_R, tHL => twdi1_F) 189 port map( Input => i1, Output => connect(1)); 190 191 -- Intrinsic delay buffers 192 U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 193 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 194 port map( Input => connect(0), Output => prop_q(0)); 195 196 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 197 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 198 port map( Input => connect(1), Output => prop_q(1)); 199 200 -- Netlist 201 U5 : AND2MAC 202 port map( I0 => prop_q(0), I1 => prop_q(1), Y => q); 203 204 205end FTSM; 206 207configuration CFG_a2_x4_FTSM of a2_x4 is 208 for FTSM 209 end for; 210end CFG_a2_x4_FTSM; 211 212 213----- CELL a3_x2 ----- 214library IEEE; 215use IEEE.STD_LOGIC_1164.all; 216library SYNOPSYS; 217use SYNOPSYS.attributes.REAL_NAME; 218 219-- entity declaration -- 220entity a3_x2 is 221 generic( 222 Timing_mesg: Boolean := True; 223 Timing_xgen: Boolean := False; 224 tpdi0_q_R : Time := 0.395 ns; 225 tpdi0_q_F : Time := 0.435 ns; 226 tpdi1_q_R : Time := 0.353 ns; 227 tpdi1_q_F : Time := 0.479 ns; 228 tpdi2_q_R : Time := 0.290 ns; 229 tpdi2_q_F : Time := 0.521 ns; 230 twdi0_R : Time := 0.000 ns; 231 twdi0_F : Time := 0.000 ns; 232 twdi1_R : Time := 0.000 ns; 233 twdi1_F : Time := 0.000 ns; 234 twdi2_R : Time := 0.000 ns; 235 twdi2_F : Time := 0.000 ns); 236 237 port( 238 i0 : in STD_LOGIC; 239 i1 : in STD_LOGIC; 240 i2 : in STD_LOGIC; 241 q : out STD_LOGIC); 242end a3_x2; 243 244-- architecture body -- 245library IEEE_ASIC; 246use IEEE.STD_LOGIC_MISC.all; 247use SYNOPSYS.attributes.backplane; 248use SYNOPSYS.attributes.PRIVATE; 249use SYNOPSYS.attributes.ASIC_CELL; 250use SYNOPSYS.attributes.PROPAGATE_VALUE; 251 252architecture FTSM of a3_x2 is 253 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 254 attribute PRIVATE of FTSM : architecture is TRUE; 255 attribute ASIC_CELL of FTSM : architecture is TRUE; 256 257 -- Backannotation attributes 258 attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; 259 attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; 260 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; 261 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; 262 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; 263 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; 264 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 265 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 266 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 267 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 268 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 269 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 270 271 signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 272 signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 273 274 component AND3MAC 275 generic( 276 tpdY_R : Time := 0 ns; 277 tpdY_F : Time := 0 ns; 278 strn : STRENGTH := strn_X01); 279 port( 280 I0 : in STD_LOGIC; 281 I1 : in STD_LOGIC; 282 I2 : in STD_LOGIC; 283 Y : out STD_LOGIC); 284 end component; 285 286begin 287 288 -- Extrinsic delay buffers 289 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 290 generic map( tLH => twdi0_R, tHL => twdi0_F) 291 port map( Input => i0, Output => connect(0)); 292 293 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 294 generic map( tLH => twdi1_R, tHL => twdi1_F) 295 port map( Input => i1, Output => connect(1)); 296 297 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 298 generic map( tLH => twdi2_R, tHL => twdi2_F) 299 port map( Input => i2, Output => connect(2)); 300 301 -- Intrinsic delay buffers 302 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 303 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 304 port map( Input => connect(0), Output => prop_q(0)); 305 306 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 307 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 308 port map( Input => connect(1), Output => prop_q(1)); 309 310 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 311 generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) 312 port map( Input => connect(2), Output => prop_q(2)); 313 314 -- Netlist 315 U7 : AND3MAC 316 port map( I0 => prop_q(1), I1 => prop_q(2), I2 => prop_q(0), Y => 317 q); 318 319 320end FTSM; 321 322configuration CFG_a3_x2_FTSM of a3_x2 is 323 for FTSM 324 end for; 325end CFG_a3_x2_FTSM; 326 327 328----- CELL a3_x4 ----- 329library IEEE; 330use IEEE.STD_LOGIC_1164.all; 331library SYNOPSYS; 332use SYNOPSYS.attributes.REAL_NAME; 333 334-- entity declaration -- 335entity a3_x4 is 336 generic( 337 Timing_mesg: Boolean := True; 338 Timing_xgen: Boolean := False; 339 tpdi0_q_R : Time := 0.478 ns; 340 tpdi0_q_F : Time := 0.514 ns; 341 tpdi1_q_R : Time := 0.428 ns; 342 tpdi1_q_F : Time := 0.554 ns; 343 tpdi2_q_R : Time := 0.356 ns; 344 tpdi2_q_F : Time := 0.592 ns; 345 twdi0_R : Time := 0.000 ns; 346 twdi0_F : Time := 0.000 ns; 347 twdi1_R : Time := 0.000 ns; 348 twdi1_F : Time := 0.000 ns; 349 twdi2_R : Time := 0.000 ns; 350 twdi2_F : Time := 0.000 ns); 351 352 port( 353 i0 : in STD_LOGIC; 354 i1 : in STD_LOGIC; 355 i2 : in STD_LOGIC; 356 q : out STD_LOGIC); 357end a3_x4; 358 359-- architecture body -- 360library IEEE_ASIC; 361use IEEE.STD_LOGIC_MISC.all; 362use SYNOPSYS.attributes.backplane; 363use SYNOPSYS.attributes.PRIVATE; 364use SYNOPSYS.attributes.ASIC_CELL; 365use SYNOPSYS.attributes.PROPAGATE_VALUE; 366 367architecture FTSM of a3_x4 is 368 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 369 attribute PRIVATE of FTSM : architecture is TRUE; 370 attribute ASIC_CELL of FTSM : architecture is TRUE; 371 372 -- Backannotation attributes 373 attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; 374 attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; 375 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; 376 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; 377 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; 378 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; 379 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 380 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 381 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 382 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 383 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 384 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 385 386 signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 387 signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 388 389 component AND3MAC 390 generic( 391 tpdY_R : Time := 0 ns; 392 tpdY_F : Time := 0 ns; 393 strn : STRENGTH := strn_X01); 394 port( 395 I0 : in STD_LOGIC; 396 I1 : in STD_LOGIC; 397 I2 : in STD_LOGIC; 398 Y : out STD_LOGIC); 399 end component; 400 401begin 402 403 -- Extrinsic delay buffers 404 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 405 generic map( tLH => twdi0_R, tHL => twdi0_F) 406 port map( Input => i0, Output => connect(0)); 407 408 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 409 generic map( tLH => twdi1_R, tHL => twdi1_F) 410 port map( Input => i1, Output => connect(1)); 411 412 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 413 generic map( tLH => twdi2_R, tHL => twdi2_F) 414 port map( Input => i2, Output => connect(2)); 415 416 -- Intrinsic delay buffers 417 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 418 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 419 port map( Input => connect(0), Output => prop_q(0)); 420 421 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 422 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 423 port map( Input => connect(1), Output => prop_q(1)); 424 425 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 426 generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) 427 port map( Input => connect(2), Output => prop_q(2)); 428 429 -- Netlist 430 U7 : AND3MAC 431 port map( I0 => prop_q(1), I1 => prop_q(2), I2 => prop_q(0), Y => 432 q); 433 434 435end FTSM; 436 437configuration CFG_a3_x4_FTSM of a3_x4 is 438 for FTSM 439 end for; 440end CFG_a3_x4_FTSM; 441 442 443----- CELL a4_x2 ----- 444library IEEE; 445use IEEE.STD_LOGIC_1164.all; 446library SYNOPSYS; 447use SYNOPSYS.attributes.REAL_NAME; 448 449-- entity declaration -- 450entity a4_x2 is 451 generic( 452 Timing_mesg: Boolean := True; 453 Timing_xgen: Boolean := False; 454 tpdi0_q_R : Time := 0.374 ns; 455 tpdi0_q_F : Time := 0.578 ns; 456 tpdi1_q_R : Time := 0.441 ns; 457 tpdi1_q_F : Time := 0.539 ns; 458 tpdi2_q_R : Time := 0.482 ns; 459 tpdi2_q_F : Time := 0.498 ns; 460 tpdi3_q_R : Time := 0.506 ns; 461 tpdi3_q_F : Time := 0.455 ns; 462 twdi0_R : Time := 0.000 ns; 463 twdi0_F : Time := 0.000 ns; 464 twdi1_R : Time := 0.000 ns; 465 twdi1_F : Time := 0.000 ns; 466 twdi2_R : Time := 0.000 ns; 467 twdi2_F : Time := 0.000 ns; 468 twdi3_R : Time := 0.000 ns; 469 twdi3_F : Time := 0.000 ns); 470 471 port( 472 i0 : in STD_LOGIC; 473 i1 : in STD_LOGIC; 474 i2 : in STD_LOGIC; 475 i3 : in STD_LOGIC; 476 q : out STD_LOGIC); 477end a4_x2; 478 479-- architecture body -- 480library IEEE_ASIC; 481use IEEE.STD_LOGIC_MISC.all; 482use SYNOPSYS.attributes.backplane; 483use SYNOPSYS.attributes.PRIVATE; 484use SYNOPSYS.attributes.ASIC_CELL; 485use SYNOPSYS.attributes.PROPAGATE_VALUE; 486 487architecture FTSM of a4_x2 is 488 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 489 attribute PRIVATE of FTSM : architecture is TRUE; 490 attribute ASIC_CELL of FTSM : architecture is TRUE; 491 492 -- Backannotation attributes 493 attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; 494 attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; 495 attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; 496 attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; 497 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; 498 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; 499 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; 500 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; 501 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 502 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 503 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 504 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 505 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 506 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 507 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 508 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 509 510 signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 511 signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 512 513 component AND4MAC 514 generic( 515 tpdY_R : Time := 0 ns; 516 tpdY_F : Time := 0 ns; 517 strn : STRENGTH := strn_X01); 518 port( 519 I0 : in STD_LOGIC; 520 I1 : in STD_LOGIC; 521 I2 : in STD_LOGIC; 522 I3 : in STD_LOGIC; 523 Y : out STD_LOGIC); 524 end component; 525 526begin 527 528 -- Extrinsic delay buffers 529 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 530 generic map( tLH => twdi0_R, tHL => twdi0_F) 531 port map( Input => i0, Output => connect(0)); 532 533 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 534 generic map( tLH => twdi1_R, tHL => twdi1_F) 535 port map( Input => i1, Output => connect(1)); 536 537 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 538 generic map( tLH => twdi2_R, tHL => twdi2_F) 539 port map( Input => i2, Output => connect(2)); 540 541 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 542 generic map( tLH => twdi3_R, tHL => twdi3_F) 543 port map( Input => i3, Output => connect(3)); 544 545 -- Intrinsic delay buffers 546 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 547 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 548 port map( Input => connect(0), Output => prop_q(0)); 549 550 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 551 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 552 port map( Input => connect(1), Output => prop_q(1)); 553 554 U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 555 generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) 556 port map( Input => connect(2), Output => prop_q(2)); 557 558 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 559 generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) 560 port map( Input => connect(3), Output => prop_q(3)); 561 562 -- Netlist 563 U9 : AND4MAC 564 port map( I0 => prop_q(0), I1 => prop_q(1), I2 => prop_q(2), I3 => 565 prop_q(3), Y => q); 566 567 568end FTSM; 569 570configuration CFG_a4_x2_FTSM of a4_x2 is 571 for FTSM 572 end for; 573end CFG_a4_x2_FTSM; 574 575 576----- CELL a4_x4 ----- 577library IEEE; 578use IEEE.STD_LOGIC_1164.all; 579library SYNOPSYS; 580use SYNOPSYS.attributes.REAL_NAME; 581 582-- entity declaration -- 583entity a4_x4 is 584 generic( 585 Timing_mesg: Boolean := True; 586 Timing_xgen: Boolean := False; 587 tpdi0_q_R : Time := 0.505 ns; 588 tpdi0_q_F : Time := 0.650 ns; 589 tpdi1_q_R : Time := 0.578 ns; 590 tpdi1_q_F : Time := 0.614 ns; 591 tpdi2_q_R : Time := 0.627 ns; 592 tpdi2_q_F : Time := 0.576 ns; 593 tpdi3_q_R : Time := 0.661 ns; 594 tpdi3_q_F : Time := 0.538 ns; 595 twdi0_R : Time := 0.000 ns; 596 twdi0_F : Time := 0.000 ns; 597 twdi1_R : Time := 0.000 ns; 598 twdi1_F : Time := 0.000 ns; 599 twdi2_R : Time := 0.000 ns; 600 twdi2_F : Time := 0.000 ns; 601 twdi3_R : Time := 0.000 ns; 602 twdi3_F : Time := 0.000 ns); 603 604 port( 605 i0 : in STD_LOGIC; 606 i1 : in STD_LOGIC; 607 i2 : in STD_LOGIC; 608 i3 : in STD_LOGIC; 609 q : out STD_LOGIC); 610end a4_x4; 611 612-- architecture body -- 613library IEEE_ASIC; 614use IEEE.STD_LOGIC_MISC.all; 615use SYNOPSYS.attributes.backplane; 616use SYNOPSYS.attributes.PRIVATE; 617use SYNOPSYS.attributes.ASIC_CELL; 618use SYNOPSYS.attributes.PROPAGATE_VALUE; 619 620architecture FTSM of a4_x4 is 621 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 622 attribute PRIVATE of FTSM : architecture is TRUE; 623 attribute ASIC_CELL of FTSM : architecture is TRUE; 624 625 -- Backannotation attributes 626 attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; 627 attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; 628 attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; 629 attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; 630 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; 631 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; 632 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; 633 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; 634 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 635 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 636 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 637 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 638 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 639 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 640 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 641 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 642 643 signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 644 signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 645 646 component AND4MAC 647 generic( 648 tpdY_R : Time := 0 ns; 649 tpdY_F : Time := 0 ns; 650 strn : STRENGTH := strn_X01); 651 port( 652 I0 : in STD_LOGIC; 653 I1 : in STD_LOGIC; 654 I2 : in STD_LOGIC; 655 I3 : in STD_LOGIC; 656 Y : out STD_LOGIC); 657 end component; 658 659begin 660 661 -- Extrinsic delay buffers 662 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 663 generic map( tLH => twdi0_R, tHL => twdi0_F) 664 port map( Input => i0, Output => connect(0)); 665 666 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 667 generic map( tLH => twdi1_R, tHL => twdi1_F) 668 port map( Input => i1, Output => connect(1)); 669 670 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 671 generic map( tLH => twdi2_R, tHL => twdi2_F) 672 port map( Input => i2, Output => connect(2)); 673 674 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 675 generic map( tLH => twdi3_R, tHL => twdi3_F) 676 port map( Input => i3, Output => connect(3)); 677 678 -- Intrinsic delay buffers 679 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 680 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 681 port map( Input => connect(0), Output => prop_q(0)); 682 683 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 684 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 685 port map( Input => connect(1), Output => prop_q(1)); 686 687 U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 688 generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) 689 port map( Input => connect(2), Output => prop_q(2)); 690 691 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 692 generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) 693 port map( Input => connect(3), Output => prop_q(3)); 694 695 -- Netlist 696 U9 : AND4MAC 697 port map( I0 => prop_q(0), I1 => prop_q(1), I2 => prop_q(2), I3 => 698 prop_q(3), Y => q); 699 700 701end FTSM; 702 703configuration CFG_a4_x4_FTSM of a4_x4 is 704 for FTSM 705 end for; 706end CFG_a4_x4_FTSM; 707 708 709----- CELL an12_x1 ----- 710library IEEE; 711use IEEE.STD_LOGIC_1164.all; 712library SYNOPSYS; 713use SYNOPSYS.attributes.REAL_NAME; 714 715-- entity declaration -- 716entity an12_x1 is 717 generic( 718 Timing_mesg: Boolean := True; 719 Timing_xgen: Boolean := False; 720 tpdi0_q_R : Time := 0.200 ns; 721 tpdi0_q_F : Time := 0.168 ns; 722 tpdi1_q_R : Time := 0.285 ns; 723 tpdi1_q_F : Time := 0.405 ns; 724 twdi0_R : Time := 0.000 ns; 725 twdi0_F : Time := 0.000 ns; 726 twdi1_R : Time := 0.000 ns; 727 twdi1_F : Time := 0.000 ns); 728 729 port( 730 i0 : in STD_LOGIC; 731 i1 : in STD_LOGIC; 732 q : out STD_LOGIC); 733end an12_x1; 734 735-- architecture body -- 736library IEEE_ASIC; 737use IEEE.STD_LOGIC_MISC.all; 738use SYNOPSYS.attributes.backplane; 739use SYNOPSYS.attributes.PRIVATE; 740use SYNOPSYS.attributes.ASIC_CELL; 741use SYNOPSYS.attributes.PROPAGATE_VALUE; 742 743architecture FTSM of an12_x1 is 744 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 745 attribute PRIVATE of FTSM : architecture is TRUE; 746 attribute ASIC_CELL of FTSM : architecture is TRUE; 747 748 -- Backannotation attributes 749 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; 750 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; 751 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tLH"; 752 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tHL"; 753 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 754 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 755 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 756 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 757 758 signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 759 signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 760 signal n1 : STD_LOGIC; 761 762 component AND2MAC 763 generic( 764 tpdY_R : Time := 0 ns; 765 tpdY_F : Time := 0 ns; 766 strn : STRENGTH := strn_X01); 767 port( 768 I0 : in STD_LOGIC; 769 I1 : in STD_LOGIC; 770 Y : out STD_LOGIC); 771 end component; 772 773 component INVMAC 774 generic( 775 tpdY_R : Time := 0 ns; 776 tpdY_F : Time := 0 ns; 777 strn : STRENGTH := strn_X01); 778 port( 779 I0 : in STD_LOGIC; 780 Y : out STD_LOGIC); 781 end component; 782 783begin 784 785 -- Extrinsic delay buffers 786 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 787 generic map( tLH => twdi0_R, tHL => twdi0_F) 788 port map( Input => i0, Output => connect(0)); 789 790 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 791 generic map( tLH => twdi1_R, tHL => twdi1_F) 792 port map( Input => i1, Output => connect(1)); 793 794 -- Intrinsic delay buffers 795 U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 796 generic map( tLH => tpdi0_q_F, tHL => tpdi0_q_R) 797 port map( Input => connect(0), Output => prop_q(0)); 798 799 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 800 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 801 port map( Input => connect(1), Output => prop_q(1)); 802 803 -- Netlist 804 U5 : AND2MAC 805 port map( I0 => prop_q(1), I1 => n1, Y => q); 806 807 U6 : INVMAC 808 port map( I0 => prop_q(0), Y => n1); 809 810 811end FTSM; 812 813configuration CFG_an12_x1_FTSM of an12_x1 is 814 for FTSM 815 end for; 816end CFG_an12_x1_FTSM; 817 818 819----- CELL an12_x4 ----- 820library IEEE; 821use IEEE.STD_LOGIC_1164.all; 822library SYNOPSYS; 823use SYNOPSYS.attributes.REAL_NAME; 824 825-- entity declaration -- 826entity an12_x4 is 827 generic( 828 Timing_mesg: Boolean := True; 829 Timing_xgen: Boolean := False; 830 tpdi0_q_R : Time := 0.461 ns; 831 tpdi0_q_F : Time := 0.471 ns; 832 tpdi1_q_R : Time := 0.269 ns; 833 tpdi1_q_F : Time := 0.518 ns; 834 twdi0_R : Time := 0.000 ns; 835 twdi0_F : Time := 0.000 ns; 836 twdi1_R : Time := 0.000 ns; 837 twdi1_F : Time := 0.000 ns); 838 839 port( 840 i0 : in STD_LOGIC; 841 i1 : in STD_LOGIC; 842 q : out STD_LOGIC); 843end an12_x4; 844 845-- architecture body -- 846library IEEE_ASIC; 847use IEEE.STD_LOGIC_MISC.all; 848use SYNOPSYS.attributes.backplane; 849use SYNOPSYS.attributes.PRIVATE; 850use SYNOPSYS.attributes.ASIC_CELL; 851use SYNOPSYS.attributes.PROPAGATE_VALUE; 852 853architecture FTSM of an12_x4 is 854 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 855 attribute PRIVATE of FTSM : architecture is TRUE; 856 attribute ASIC_CELL of FTSM : architecture is TRUE; 857 858 -- Backannotation attributes 859 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; 860 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; 861 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tLH"; 862 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tHL"; 863 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 864 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 865 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 866 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 867 868 signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 869 signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 870 signal n1 : STD_LOGIC; 871 872 component AND2MAC 873 generic( 874 tpdY_R : Time := 0 ns; 875 tpdY_F : Time := 0 ns; 876 strn : STRENGTH := strn_X01); 877 port( 878 I0 : in STD_LOGIC; 879 I1 : in STD_LOGIC; 880 Y : out STD_LOGIC); 881 end component; 882 883 component INVMAC 884 generic( 885 tpdY_R : Time := 0 ns; 886 tpdY_F : Time := 0 ns; 887 strn : STRENGTH := strn_X01); 888 port( 889 I0 : in STD_LOGIC; 890 Y : out STD_LOGIC); 891 end component; 892 893begin 894 895 -- Extrinsic delay buffers 896 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 897 generic map( tLH => twdi0_R, tHL => twdi0_F) 898 port map( Input => i0, Output => connect(0)); 899 900 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 901 generic map( tLH => twdi1_R, tHL => twdi1_F) 902 port map( Input => i1, Output => connect(1)); 903 904 -- Intrinsic delay buffers 905 U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 906 generic map( tLH => tpdi0_q_F, tHL => tpdi0_q_R) 907 port map( Input => connect(0), Output => prop_q(0)); 908 909 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 910 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 911 port map( Input => connect(1), Output => prop_q(1)); 912 913 -- Netlist 914 U5 : AND2MAC 915 port map( I0 => prop_q(1), I1 => n1, Y => q); 916 917 U6 : INVMAC 918 port map( I0 => prop_q(0), Y => n1); 919 920 921end FTSM; 922 923configuration CFG_an12_x4_FTSM of an12_x4 is 924 for FTSM 925 end for; 926end CFG_an12_x4_FTSM; 927 928 929----- CELL ao2o22_x2 ----- 930library IEEE; 931use IEEE.STD_LOGIC_1164.all; 932library SYNOPSYS; 933use SYNOPSYS.attributes.REAL_NAME; 934 935-- entity declaration -- 936entity ao2o22_x2 is 937 generic( 938 Timing_mesg: Boolean := True; 939 Timing_xgen: Boolean := False; 940 tpdi0_q_R : Time := 0.572 ns; 941 tpdi0_q_F : Time := 0.451 ns; 942 tpdi1_q_R : Time := 0.508 ns; 943 tpdi1_q_F : Time := 0.542 ns; 944 tpdi2_q_R : Time := 0.432 ns; 945 tpdi2_q_F : Time := 0.627 ns; 946 tpdi3_q_R : Time := 0.488 ns; 947 tpdi3_q_F : Time := 0.526 ns; 948 twdi0_R : Time := 0.000 ns; 949 twdi0_F : Time := 0.000 ns; 950 twdi1_R : Time := 0.000 ns; 951 twdi1_F : Time := 0.000 ns; 952 twdi2_R : Time := 0.000 ns; 953 twdi2_F : Time := 0.000 ns; 954 twdi3_R : Time := 0.000 ns; 955 twdi3_F : Time := 0.000 ns); 956 957 port( 958 i0 : in STD_LOGIC; 959 i1 : in STD_LOGIC; 960 i2 : in STD_LOGIC; 961 i3 : in STD_LOGIC; 962 q : out STD_LOGIC); 963end ao2o22_x2; 964 965-- architecture body -- 966library IEEE_ASIC; 967use IEEE.STD_LOGIC_MISC.all; 968use SYNOPSYS.attributes.backplane; 969use SYNOPSYS.attributes.PRIVATE; 970use SYNOPSYS.attributes.ASIC_CELL; 971use SYNOPSYS.attributes.PROPAGATE_VALUE; 972 973architecture FTSM of ao2o22_x2 is 974 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 975 attribute PRIVATE of FTSM : architecture is TRUE; 976 attribute ASIC_CELL of FTSM : architecture is TRUE; 977 978 -- Backannotation attributes 979 attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; 980 attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; 981 attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; 982 attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; 983 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; 984 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; 985 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; 986 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; 987 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 988 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 989 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 990 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 991 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 992 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 993 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 994 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 995 996 signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 997 signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 998 signal n1, n2 : STD_LOGIC; 999 1000 component AND2MAC 1001 generic( 1002 tpdY_R : Time := 0 ns; 1003 tpdY_F : Time := 0 ns; 1004 strn : STRENGTH := strn_X01); 1005 port( 1006 I0 : in STD_LOGIC; 1007 I1 : in STD_LOGIC; 1008 Y : out STD_LOGIC); 1009 end component; 1010 1011 component OR2MAC 1012 generic( 1013 tpdY_R : Time := 0 ns; 1014 tpdY_F : Time := 0 ns; 1015 strn : STRENGTH := strn_X01); 1016 port( 1017 I0 : in STD_LOGIC; 1018 I1 : in STD_LOGIC; 1019 Y : out STD_LOGIC); 1020 end component; 1021 1022begin 1023 1024 -- Extrinsic delay buffers 1025 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 1026 generic map( tLH => twdi0_R, tHL => twdi0_F) 1027 port map( Input => i0, Output => connect(0)); 1028 1029 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 1030 generic map( tLH => twdi1_R, tHL => twdi1_F) 1031 port map( Input => i1, Output => connect(1)); 1032 1033 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 1034 generic map( tLH => twdi2_R, tHL => twdi2_F) 1035 port map( Input => i2, Output => connect(2)); 1036 1037 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 1038 generic map( tLH => twdi3_R, tHL => twdi3_F) 1039 port map( Input => i3, Output => connect(3)); 1040 1041 -- Intrinsic delay buffers 1042 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 1043 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 1044 port map( Input => connect(0), Output => prop_q(0)); 1045 1046 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 1047 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 1048 port map( Input => connect(1), Output => prop_q(1)); 1049 1050 U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 1051 generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) 1052 port map( Input => connect(2), Output => prop_q(2)); 1053 1054 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 1055 generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) 1056 port map( Input => connect(3), Output => prop_q(3)); 1057 1058 -- Netlist 1059 U9 : AND2MAC 1060 port map( I0 => n1, I1 => n2, Y => q); 1061 1062 U10 : OR2MAC 1063 port map( I0 => prop_q(3), I1 => prop_q(2), Y => n2); 1064 1065 U11 : OR2MAC 1066 port map( I0 => prop_q(1), I1 => prop_q(0), Y => n1); 1067 1068 1069end FTSM; 1070 1071configuration CFG_ao2o22_x2_FTSM of ao2o22_x2 is 1072 for FTSM 1073 end for; 1074end CFG_ao2o22_x2_FTSM; 1075 1076 1077----- CELL ao2o22_x4 ----- 1078library IEEE; 1079use IEEE.STD_LOGIC_1164.all; 1080library SYNOPSYS; 1081use SYNOPSYS.attributes.REAL_NAME; 1082 1083-- entity declaration -- 1084entity ao2o22_x4 is 1085 generic( 1086 Timing_mesg: Boolean := True; 1087 Timing_xgen: Boolean := False; 1088 tpdi0_q_R : Time := 0.696 ns; 1089 tpdi0_q_F : Time := 0.569 ns; 1090 tpdi1_q_R : Time := 0.637 ns; 1091 tpdi1_q_F : Time := 0.666 ns; 1092 tpdi2_q_R : Time := 0.554 ns; 1093 tpdi2_q_F : Time := 0.744 ns; 1094 tpdi3_q_R : Time := 0.606 ns; 1095 tpdi3_q_F : Time := 0.639 ns; 1096 twdi0_R : Time := 0.000 ns; 1097 twdi0_F : Time := 0.000 ns; 1098 twdi1_R : Time := 0.000 ns; 1099 twdi1_F : Time := 0.000 ns; 1100 twdi2_R : Time := 0.000 ns; 1101 twdi2_F : Time := 0.000 ns; 1102 twdi3_R : Time := 0.000 ns; 1103 twdi3_F : Time := 0.000 ns); 1104 1105 port( 1106 i0 : in STD_LOGIC; 1107 i1 : in STD_LOGIC; 1108 i2 : in STD_LOGIC; 1109 i3 : in STD_LOGIC; 1110 q : out STD_LOGIC); 1111end ao2o22_x4; 1112 1113-- architecture body -- 1114library IEEE_ASIC; 1115use IEEE.STD_LOGIC_MISC.all; 1116use SYNOPSYS.attributes.backplane; 1117use SYNOPSYS.attributes.PRIVATE; 1118use SYNOPSYS.attributes.ASIC_CELL; 1119use SYNOPSYS.attributes.PROPAGATE_VALUE; 1120 1121architecture FTSM of ao2o22_x4 is 1122 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 1123 attribute PRIVATE of FTSM : architecture is TRUE; 1124 attribute ASIC_CELL of FTSM : architecture is TRUE; 1125 1126 -- Backannotation attributes 1127 attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; 1128 attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; 1129 attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; 1130 attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; 1131 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; 1132 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; 1133 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; 1134 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; 1135 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 1136 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 1137 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 1138 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 1139 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 1140 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 1141 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 1142 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 1143 1144 signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 1145 signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 1146 signal n1, n2 : STD_LOGIC; 1147 1148 component AND2MAC 1149 generic( 1150 tpdY_R : Time := 0 ns; 1151 tpdY_F : Time := 0 ns; 1152 strn : STRENGTH := strn_X01); 1153 port( 1154 I0 : in STD_LOGIC; 1155 I1 : in STD_LOGIC; 1156 Y : out STD_LOGIC); 1157 end component; 1158 1159 component OR2MAC 1160 generic( 1161 tpdY_R : Time := 0 ns; 1162 tpdY_F : Time := 0 ns; 1163 strn : STRENGTH := strn_X01); 1164 port( 1165 I0 : in STD_LOGIC; 1166 I1 : in STD_LOGIC; 1167 Y : out STD_LOGIC); 1168 end component; 1169 1170begin 1171 1172 -- Extrinsic delay buffers 1173 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 1174 generic map( tLH => twdi0_R, tHL => twdi0_F) 1175 port map( Input => i0, Output => connect(0)); 1176 1177 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 1178 generic map( tLH => twdi1_R, tHL => twdi1_F) 1179 port map( Input => i1, Output => connect(1)); 1180 1181 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 1182 generic map( tLH => twdi2_R, tHL => twdi2_F) 1183 port map( Input => i2, Output => connect(2)); 1184 1185 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 1186 generic map( tLH => twdi3_R, tHL => twdi3_F) 1187 port map( Input => i3, Output => connect(3)); 1188 1189 -- Intrinsic delay buffers 1190 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 1191 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 1192 port map( Input => connect(0), Output => prop_q(0)); 1193 1194 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 1195 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 1196 port map( Input => connect(1), Output => prop_q(1)); 1197 1198 U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 1199 generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) 1200 port map( Input => connect(2), Output => prop_q(2)); 1201 1202 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 1203 generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) 1204 port map( Input => connect(3), Output => prop_q(3)); 1205 1206 -- Netlist 1207 U9 : AND2MAC 1208 port map( I0 => n1, I1 => n2, Y => q); 1209 1210 U10 : OR2MAC 1211 port map( I0 => prop_q(3), I1 => prop_q(2), Y => n2); 1212 1213 U11 : OR2MAC 1214 port map( I0 => prop_q(1), I1 => prop_q(0), Y => n1); 1215 1216 1217end FTSM; 1218 1219configuration CFG_ao2o22_x4_FTSM of ao2o22_x4 is 1220 for FTSM 1221 end for; 1222end CFG_ao2o22_x4_FTSM; 1223 1224 1225----- CELL ao22_x2 ----- 1226library IEEE; 1227use IEEE.STD_LOGIC_1164.all; 1228library SYNOPSYS; 1229use SYNOPSYS.attributes.REAL_NAME; 1230 1231-- entity declaration -- 1232entity ao22_x2 is 1233 generic( 1234 Timing_mesg: Boolean := True; 1235 Timing_xgen: Boolean := False; 1236 tpdi0_q_R : Time := 0.558 ns; 1237 tpdi0_q_F : Time := 0.447 ns; 1238 tpdi1_q_R : Time := 0.493 ns; 1239 tpdi1_q_F : Time := 0.526 ns; 1240 tpdi2_q_R : Time := 0.420 ns; 1241 tpdi2_q_F : Time := 0.425 ns; 1242 twdi0_R : Time := 0.000 ns; 1243 twdi0_F : Time := 0.000 ns; 1244 twdi1_R : Time := 0.000 ns; 1245 twdi1_F : Time := 0.000 ns; 1246 twdi2_R : Time := 0.000 ns; 1247 twdi2_F : Time := 0.000 ns); 1248 1249 port( 1250 i0 : in STD_LOGIC; 1251 i1 : in STD_LOGIC; 1252 i2 : in STD_LOGIC; 1253 q : out STD_LOGIC); 1254end ao22_x2; 1255 1256-- architecture body -- 1257library IEEE_ASIC; 1258use IEEE.STD_LOGIC_MISC.all; 1259use SYNOPSYS.attributes.backplane; 1260use SYNOPSYS.attributes.PRIVATE; 1261use SYNOPSYS.attributes.ASIC_CELL; 1262use SYNOPSYS.attributes.PROPAGATE_VALUE; 1263 1264architecture FTSM of ao22_x2 is 1265 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 1266 attribute PRIVATE of FTSM : architecture is TRUE; 1267 attribute ASIC_CELL of FTSM : architecture is TRUE; 1268 1269 -- Backannotation attributes 1270 attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; 1271 attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; 1272 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; 1273 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; 1274 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; 1275 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; 1276 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 1277 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 1278 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 1279 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 1280 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 1281 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 1282 1283 signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 1284 signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 1285 signal n1 : STD_LOGIC; 1286 1287 component AND2MAC 1288 generic( 1289 tpdY_R : Time := 0 ns; 1290 tpdY_F : Time := 0 ns; 1291 strn : STRENGTH := strn_X01); 1292 port( 1293 I0 : in STD_LOGIC; 1294 I1 : in STD_LOGIC; 1295 Y : out STD_LOGIC); 1296 end component; 1297 1298 component OR2MAC 1299 generic( 1300 tpdY_R : Time := 0 ns; 1301 tpdY_F : Time := 0 ns; 1302 strn : STRENGTH := strn_X01); 1303 port( 1304 I0 : in STD_LOGIC; 1305 I1 : in STD_LOGIC; 1306 Y : out STD_LOGIC); 1307 end component; 1308 1309begin 1310 1311 -- Extrinsic delay buffers 1312 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 1313 generic map( tLH => twdi0_R, tHL => twdi0_F) 1314 port map( Input => i0, Output => connect(0)); 1315 1316 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 1317 generic map( tLH => twdi1_R, tHL => twdi1_F) 1318 port map( Input => i1, Output => connect(1)); 1319 1320 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 1321 generic map( tLH => twdi2_R, tHL => twdi2_F) 1322 port map( Input => i2, Output => connect(2)); 1323 1324 -- Intrinsic delay buffers 1325 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 1326 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 1327 port map( Input => connect(0), Output => prop_q(0)); 1328 1329 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 1330 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 1331 port map( Input => connect(1), Output => prop_q(1)); 1332 1333 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 1334 generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) 1335 port map( Input => connect(2), Output => prop_q(2)); 1336 1337 -- Netlist 1338 U7 : AND2MAC 1339 port map( I0 => prop_q(2), I1 => n1, Y => q); 1340 1341 U8 : OR2MAC 1342 port map( I0 => prop_q(1), I1 => prop_q(0), Y => n1); 1343 1344 1345end FTSM; 1346 1347configuration CFG_ao22_x2_FTSM of ao22_x2 is 1348 for FTSM 1349 end for; 1350end CFG_ao22_x2_FTSM; 1351 1352 1353----- CELL ao22_x4 ----- 1354library IEEE; 1355use IEEE.STD_LOGIC_1164.all; 1356library SYNOPSYS; 1357use SYNOPSYS.attributes.REAL_NAME; 1358 1359-- entity declaration -- 1360entity ao22_x4 is 1361 generic( 1362 Timing_mesg: Boolean := True; 1363 Timing_xgen: Boolean := False; 1364 tpdi0_q_R : Time := 0.674 ns; 1365 tpdi0_q_F : Time := 0.552 ns; 1366 tpdi1_q_R : Time := 0.615 ns; 1367 tpdi1_q_F : Time := 0.647 ns; 1368 tpdi2_q_R : Time := 0.526 ns; 1369 tpdi2_q_F : Time := 0.505 ns; 1370 twdi0_R : Time := 0.000 ns; 1371 twdi0_F : Time := 0.000 ns; 1372 twdi1_R : Time := 0.000 ns; 1373 twdi1_F : Time := 0.000 ns; 1374 twdi2_R : Time := 0.000 ns; 1375 twdi2_F : Time := 0.000 ns); 1376 1377 port( 1378 i0 : in STD_LOGIC; 1379 i1 : in STD_LOGIC; 1380 i2 : in STD_LOGIC; 1381 q : out STD_LOGIC); 1382end ao22_x4; 1383 1384-- architecture body -- 1385library IEEE_ASIC; 1386use IEEE.STD_LOGIC_MISC.all; 1387use SYNOPSYS.attributes.backplane; 1388use SYNOPSYS.attributes.PRIVATE; 1389use SYNOPSYS.attributes.ASIC_CELL; 1390use SYNOPSYS.attributes.PROPAGATE_VALUE; 1391 1392architecture FTSM of ao22_x4 is 1393 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 1394 attribute PRIVATE of FTSM : architecture is TRUE; 1395 attribute ASIC_CELL of FTSM : architecture is TRUE; 1396 1397 -- Backannotation attributes 1398 attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; 1399 attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; 1400 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; 1401 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; 1402 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; 1403 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; 1404 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 1405 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 1406 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 1407 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 1408 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 1409 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 1410 1411 signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 1412 signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 1413 signal n1 : STD_LOGIC; 1414 1415 component AND2MAC 1416 generic( 1417 tpdY_R : Time := 0 ns; 1418 tpdY_F : Time := 0 ns; 1419 strn : STRENGTH := strn_X01); 1420 port( 1421 I0 : in STD_LOGIC; 1422 I1 : in STD_LOGIC; 1423 Y : out STD_LOGIC); 1424 end component; 1425 1426 component OR2MAC 1427 generic( 1428 tpdY_R : Time := 0 ns; 1429 tpdY_F : Time := 0 ns; 1430 strn : STRENGTH := strn_X01); 1431 port( 1432 I0 : in STD_LOGIC; 1433 I1 : in STD_LOGIC; 1434 Y : out STD_LOGIC); 1435 end component; 1436 1437begin 1438 1439 -- Extrinsic delay buffers 1440 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 1441 generic map( tLH => twdi0_R, tHL => twdi0_F) 1442 port map( Input => i0, Output => connect(0)); 1443 1444 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 1445 generic map( tLH => twdi1_R, tHL => twdi1_F) 1446 port map( Input => i1, Output => connect(1)); 1447 1448 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 1449 generic map( tLH => twdi2_R, tHL => twdi2_F) 1450 port map( Input => i2, Output => connect(2)); 1451 1452 -- Intrinsic delay buffers 1453 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 1454 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 1455 port map( Input => connect(0), Output => prop_q(0)); 1456 1457 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 1458 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 1459 port map( Input => connect(1), Output => prop_q(1)); 1460 1461 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 1462 generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) 1463 port map( Input => connect(2), Output => prop_q(2)); 1464 1465 -- Netlist 1466 U7 : AND2MAC 1467 port map( I0 => prop_q(2), I1 => n1, Y => q); 1468 1469 U8 : OR2MAC 1470 port map( I0 => prop_q(1), I1 => prop_q(0), Y => n1); 1471 1472 1473end FTSM; 1474 1475configuration CFG_ao22_x4_FTSM of ao22_x4 is 1476 for FTSM 1477 end for; 1478end CFG_ao22_x4_FTSM; 1479 1480 1481----- CELL buf_x2 ----- 1482library IEEE; 1483use IEEE.STD_LOGIC_1164.all; 1484library SYNOPSYS; 1485use SYNOPSYS.attributes.REAL_NAME; 1486 1487-- entity declaration -- 1488entity buf_x2 is 1489 generic( 1490 Timing_mesg: Boolean := True; 1491 Timing_xgen: Boolean := False; 1492 tpdi_q_R : Time := 0.409 ns; 1493 tpdi_q_F : Time := 0.391 ns; 1494 twdi_R : Time := 0.000 ns; 1495 twdi_F : Time := 0.000 ns); 1496 1497 port( 1498 i : in STD_LOGIC; 1499 q : out STD_LOGIC); 1500end buf_x2; 1501 1502-- architecture body -- 1503library IEEE_ASIC; 1504use IEEE.STD_LOGIC_MISC.all; 1505use SYNOPSYS.attributes.backplane; 1506use SYNOPSYS.attributes.PRIVATE; 1507use SYNOPSYS.attributes.ASIC_CELL; 1508use SYNOPSYS.attributes.PROPAGATE_VALUE; 1509 1510architecture FTSM of buf_x2 is 1511 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 1512 attribute PRIVATE of FTSM : architecture is TRUE; 1513 attribute ASIC_CELL of FTSM : architecture is TRUE; 1514 1515 -- Backannotation attributes 1516 attribute PROPAGATE_VALUE of tpdi_q_F: constant is "U2/tHL"; 1517 attribute PROPAGATE_VALUE of tpdi_q_R: constant is "U2/tLH"; 1518 attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; 1519 attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; 1520 1521 signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); 1522 1523begin 1524 1525 -- Extrinsic delay buffers 1526 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 1527 generic map( tLH => twdi_R, tHL => twdi_F) 1528 port map( Input => i, Output => connect(0)); 1529 1530 -- Concurrent assignments 1531 U2 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 1532 generic map( tLH => tpdi_q_R, tHL => tpdi_q_F) 1533 port map( Input => connect(0), Output => q); 1534 1535 1536end FTSM; 1537 1538configuration CFG_buf_x2_FTSM of buf_x2 is 1539 for FTSM 1540 end for; 1541end CFG_buf_x2_FTSM; 1542 1543 1544----- CELL buf_x4 ----- 1545library IEEE; 1546use IEEE.STD_LOGIC_1164.all; 1547library SYNOPSYS; 1548use SYNOPSYS.attributes.REAL_NAME; 1549 1550-- entity declaration -- 1551entity buf_x4 is 1552 generic( 1553 Timing_mesg: Boolean := True; 1554 Timing_xgen: Boolean := False; 1555 tpdi_q_R : Time := 0.379 ns; 1556 tpdi_q_F : Time := 0.409 ns; 1557 twdi_R : Time := 0.000 ns; 1558 twdi_F : Time := 0.000 ns); 1559 1560 port( 1561 i : in STD_LOGIC; 1562 q : out STD_LOGIC); 1563end buf_x4; 1564 1565-- architecture body -- 1566library IEEE_ASIC; 1567use IEEE.STD_LOGIC_MISC.all; 1568use SYNOPSYS.attributes.backplane; 1569use SYNOPSYS.attributes.PRIVATE; 1570use SYNOPSYS.attributes.ASIC_CELL; 1571use SYNOPSYS.attributes.PROPAGATE_VALUE; 1572 1573architecture FTSM of buf_x4 is 1574 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 1575 attribute PRIVATE of FTSM : architecture is TRUE; 1576 attribute ASIC_CELL of FTSM : architecture is TRUE; 1577 1578 -- Backannotation attributes 1579 attribute PROPAGATE_VALUE of tpdi_q_F: constant is "U2/tHL"; 1580 attribute PROPAGATE_VALUE of tpdi_q_R: constant is "U2/tLH"; 1581 attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; 1582 attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; 1583 1584 signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); 1585 1586begin 1587 1588 -- Extrinsic delay buffers 1589 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 1590 generic map( tLH => twdi_R, tHL => twdi_F) 1591 port map( Input => i, Output => connect(0)); 1592 1593 -- Concurrent assignments 1594 U2 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 1595 generic map( tLH => tpdi_q_R, tHL => tpdi_q_F) 1596 port map( Input => connect(0), Output => q); 1597 1598 1599end FTSM; 1600 1601configuration CFG_buf_x4_FTSM of buf_x4 is 1602 for FTSM 1603 end for; 1604end CFG_buf_x4_FTSM; 1605 1606 1607----- CELL buf_x8 ----- 1608library IEEE; 1609use IEEE.STD_LOGIC_1164.all; 1610library SYNOPSYS; 1611use SYNOPSYS.attributes.REAL_NAME; 1612 1613-- entity declaration -- 1614entity buf_x8 is 1615 generic( 1616 Timing_mesg: Boolean := True; 1617 Timing_xgen: Boolean := False; 1618 tpdi_q_R : Time := 0.343 ns; 1619 tpdi_q_F : Time := 0.396 ns; 1620 twdi_R : Time := 0.000 ns; 1621 twdi_F : Time := 0.000 ns); 1622 1623 port( 1624 i : in STD_LOGIC; 1625 q : out STD_LOGIC); 1626end buf_x8; 1627 1628-- architecture body -- 1629library IEEE_ASIC; 1630use IEEE.STD_LOGIC_MISC.all; 1631use SYNOPSYS.attributes.backplane; 1632use SYNOPSYS.attributes.PRIVATE; 1633use SYNOPSYS.attributes.ASIC_CELL; 1634use SYNOPSYS.attributes.PROPAGATE_VALUE; 1635 1636architecture FTSM of buf_x8 is 1637 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 1638 attribute PRIVATE of FTSM : architecture is TRUE; 1639 attribute ASIC_CELL of FTSM : architecture is TRUE; 1640 1641 -- Backannotation attributes 1642 attribute PROPAGATE_VALUE of tpdi_q_F: constant is "U2/tHL"; 1643 attribute PROPAGATE_VALUE of tpdi_q_R: constant is "U2/tLH"; 1644 attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; 1645 attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; 1646 1647 signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); 1648 1649begin 1650 1651 -- Extrinsic delay buffers 1652 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 1653 generic map( tLH => twdi_R, tHL => twdi_F) 1654 port map( Input => i, Output => connect(0)); 1655 1656 -- Concurrent assignments 1657 U2 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 1658 generic map( tLH => tpdi_q_R, tHL => tpdi_q_F) 1659 port map( Input => connect(0), Output => q); 1660 1661 1662end FTSM; 1663 1664configuration CFG_buf_x8_FTSM of buf_x8 is 1665 for FTSM 1666 end for; 1667end CFG_buf_x8_FTSM; 1668 1669 1670----- CELL inv_x1 ----- 1671library IEEE; 1672use IEEE.STD_LOGIC_1164.all; 1673library SYNOPSYS; 1674use SYNOPSYS.attributes.REAL_NAME; 1675 1676-- entity declaration -- 1677entity inv_x1 is 1678 generic( 1679 Timing_mesg: Boolean := True; 1680 Timing_xgen: Boolean := False; 1681 tpdi_nq_R : Time := 0.101 ns; 1682 tpdi_nq_F : Time := 0.139 ns; 1683 twdi_R : Time := 0.000 ns; 1684 twdi_F : Time := 0.000 ns); 1685 1686 port( 1687 i : in STD_LOGIC; 1688 nq : out STD_LOGIC); 1689end inv_x1; 1690 1691-- architecture body -- 1692library IEEE_ASIC; 1693use IEEE.STD_LOGIC_MISC.all; 1694use SYNOPSYS.attributes.backplane; 1695use SYNOPSYS.attributes.PRIVATE; 1696use SYNOPSYS.attributes.ASIC_CELL; 1697use SYNOPSYS.attributes.PROPAGATE_VALUE; 1698 1699architecture FTSM of inv_x1 is 1700 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 1701 attribute PRIVATE of FTSM : architecture is TRUE; 1702 attribute ASIC_CELL of FTSM : architecture is TRUE; 1703 1704 -- Backannotation attributes 1705 attribute PROPAGATE_VALUE of tpdi_nq_F: constant is "U2/U1/tHL"; 1706 attribute PROPAGATE_VALUE of tpdi_nq_R: constant is "U2/U1/tLH"; 1707 attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; 1708 attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; 1709 1710 signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); 1711 1712 component INVMAC 1713 generic( 1714 tpdY_R : Time := 0 ns; 1715 tpdY_F : Time := 0 ns; 1716 strn : STRENGTH := strn_X01); 1717 port( 1718 I0 : in STD_LOGIC; 1719 Y : out STD_LOGIC); 1720 end component; 1721 1722begin 1723 1724 -- Extrinsic delay buffers 1725 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 1726 generic map( tLH => twdi_R, tHL => twdi_F) 1727 port map( Input => i, Output => connect(0)); 1728 1729 -- Netlist 1730 U2 : INVMAC 1731 generic map( tpdY_R => tpdi_nq_R, tpdY_F => tpdi_nq_F ) 1732 port map( I0 => connect(0), Y => nq); 1733 1734 1735end FTSM; 1736 1737configuration CFG_inv_x1_FTSM of inv_x1 is 1738 for FTSM 1739 end for; 1740end CFG_inv_x1_FTSM; 1741 1742 1743----- CELL inv_x2 ----- 1744library IEEE; 1745use IEEE.STD_LOGIC_1164.all; 1746library SYNOPSYS; 1747use SYNOPSYS.attributes.REAL_NAME; 1748 1749-- entity declaration -- 1750entity inv_x2 is 1751 generic( 1752 Timing_mesg: Boolean := True; 1753 Timing_xgen: Boolean := False; 1754 tpdi_nq_R : Time := 0.069 ns; 1755 tpdi_nq_F : Time := 0.163 ns; 1756 twdi_R : Time := 0.000 ns; 1757 twdi_F : Time := 0.000 ns); 1758 1759 port( 1760 i : in STD_LOGIC; 1761 nq : out STD_LOGIC); 1762end inv_x2; 1763 1764-- architecture body -- 1765library IEEE_ASIC; 1766use IEEE.STD_LOGIC_MISC.all; 1767use SYNOPSYS.attributes.backplane; 1768use SYNOPSYS.attributes.PRIVATE; 1769use SYNOPSYS.attributes.ASIC_CELL; 1770use SYNOPSYS.attributes.PROPAGATE_VALUE; 1771 1772architecture FTSM of inv_x2 is 1773 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 1774 attribute PRIVATE of FTSM : architecture is TRUE; 1775 attribute ASIC_CELL of FTSM : architecture is TRUE; 1776 1777 -- Backannotation attributes 1778 attribute PROPAGATE_VALUE of tpdi_nq_F: constant is "U2/U1/tHL"; 1779 attribute PROPAGATE_VALUE of tpdi_nq_R: constant is "U2/U1/tLH"; 1780 attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; 1781 attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; 1782 1783 signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); 1784 1785 component INVMAC 1786 generic( 1787 tpdY_R : Time := 0 ns; 1788 tpdY_F : Time := 0 ns; 1789 strn : STRENGTH := strn_X01); 1790 port( 1791 I0 : in STD_LOGIC; 1792 Y : out STD_LOGIC); 1793 end component; 1794 1795begin 1796 1797 -- Extrinsic delay buffers 1798 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 1799 generic map( tLH => twdi_R, tHL => twdi_F) 1800 port map( Input => i, Output => connect(0)); 1801 1802 -- Netlist 1803 U2 : INVMAC 1804 generic map( tpdY_R => tpdi_nq_R, tpdY_F => tpdi_nq_F ) 1805 port map( I0 => connect(0), Y => nq); 1806 1807 1808end FTSM; 1809 1810configuration CFG_inv_x2_FTSM of inv_x2 is 1811 for FTSM 1812 end for; 1813end CFG_inv_x2_FTSM; 1814 1815 1816----- CELL inv_x4 ----- 1817library IEEE; 1818use IEEE.STD_LOGIC_1164.all; 1819library SYNOPSYS; 1820use SYNOPSYS.attributes.REAL_NAME; 1821 1822-- entity declaration -- 1823entity inv_x4 is 1824 generic( 1825 Timing_mesg: Boolean := True; 1826 Timing_xgen: Boolean := False; 1827 tpdi_nq_R : Time := 0.071 ns; 1828 tpdi_nq_F : Time := 0.143 ns; 1829 twdi_R : Time := 0.000 ns; 1830 twdi_F : Time := 0.000 ns); 1831 1832 port( 1833 i : in STD_LOGIC; 1834 nq : out STD_LOGIC); 1835end inv_x4; 1836 1837-- architecture body -- 1838library IEEE_ASIC; 1839use IEEE.STD_LOGIC_MISC.all; 1840use SYNOPSYS.attributes.backplane; 1841use SYNOPSYS.attributes.PRIVATE; 1842use SYNOPSYS.attributes.ASIC_CELL; 1843use SYNOPSYS.attributes.PROPAGATE_VALUE; 1844 1845architecture FTSM of inv_x4 is 1846 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 1847 attribute PRIVATE of FTSM : architecture is TRUE; 1848 attribute ASIC_CELL of FTSM : architecture is TRUE; 1849 1850 -- Backannotation attributes 1851 attribute PROPAGATE_VALUE of tpdi_nq_F: constant is "U2/U1/tHL"; 1852 attribute PROPAGATE_VALUE of tpdi_nq_R: constant is "U2/U1/tLH"; 1853 attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; 1854 attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; 1855 1856 signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); 1857 1858 component INVMAC 1859 generic( 1860 tpdY_R : Time := 0 ns; 1861 tpdY_F : Time := 0 ns; 1862 strn : STRENGTH := strn_X01); 1863 port( 1864 I0 : in STD_LOGIC; 1865 Y : out STD_LOGIC); 1866 end component; 1867 1868begin 1869 1870 -- Extrinsic delay buffers 1871 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 1872 generic map( tLH => twdi_R, tHL => twdi_F) 1873 port map( Input => i, Output => connect(0)); 1874 1875 -- Netlist 1876 U2 : INVMAC 1877 generic map( tpdY_R => tpdi_nq_R, tpdY_F => tpdi_nq_F ) 1878 port map( I0 => connect(0), Y => nq); 1879 1880 1881end FTSM; 1882 1883configuration CFG_inv_x4_FTSM of inv_x4 is 1884 for FTSM 1885 end for; 1886end CFG_inv_x4_FTSM; 1887 1888 1889----- CELL inv_x8 ----- 1890library IEEE; 1891use IEEE.STD_LOGIC_1164.all; 1892library SYNOPSYS; 1893use SYNOPSYS.attributes.REAL_NAME; 1894 1895-- entity declaration -- 1896entity inv_x8 is 1897 generic( 1898 Timing_mesg: Boolean := True; 1899 Timing_xgen: Boolean := False; 1900 tpdi_nq_R : Time := 0.086 ns; 1901 tpdi_nq_F : Time := 0.133 ns; 1902 twdi_R : Time := 0.000 ns; 1903 twdi_F : Time := 0.000 ns); 1904 1905 port( 1906 i : in STD_LOGIC; 1907 nq : out STD_LOGIC); 1908end inv_x8; 1909 1910-- architecture body -- 1911library IEEE_ASIC; 1912use IEEE.STD_LOGIC_MISC.all; 1913use SYNOPSYS.attributes.backplane; 1914use SYNOPSYS.attributes.PRIVATE; 1915use SYNOPSYS.attributes.ASIC_CELL; 1916use SYNOPSYS.attributes.PROPAGATE_VALUE; 1917 1918architecture FTSM of inv_x8 is 1919 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 1920 attribute PRIVATE of FTSM : architecture is TRUE; 1921 attribute ASIC_CELL of FTSM : architecture is TRUE; 1922 1923 -- Backannotation attributes 1924 attribute PROPAGATE_VALUE of tpdi_nq_F: constant is "U2/U1/tHL"; 1925 attribute PROPAGATE_VALUE of tpdi_nq_R: constant is "U2/U1/tLH"; 1926 attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; 1927 attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; 1928 1929 signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); 1930 1931 component INVMAC 1932 generic( 1933 tpdY_R : Time := 0 ns; 1934 tpdY_F : Time := 0 ns; 1935 strn : STRENGTH := strn_X01); 1936 port( 1937 I0 : in STD_LOGIC; 1938 Y : out STD_LOGIC); 1939 end component; 1940 1941begin 1942 1943 -- Extrinsic delay buffers 1944 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 1945 generic map( tLH => twdi_R, tHL => twdi_F) 1946 port map( Input => i, Output => connect(0)); 1947 1948 -- Netlist 1949 U2 : INVMAC 1950 generic map( tpdY_R => tpdi_nq_R, tpdY_F => tpdi_nq_F ) 1951 port map( I0 => connect(0), Y => nq); 1952 1953 1954end FTSM; 1955 1956configuration CFG_inv_x8_FTSM of inv_x8 is 1957 for FTSM 1958 end for; 1959end CFG_inv_x8_FTSM; 1960 1961 1962----- CELL mx2_x2 ----- 1963library IEEE; 1964use IEEE.STD_LOGIC_1164.all; 1965library SYNOPSYS; 1966use SYNOPSYS.attributes.REAL_NAME; 1967 1968-- entity declaration -- 1969entity mx2_x2 is 1970 generic( 1971 Timing_mesg: Boolean := True; 1972 Timing_xgen: Boolean := False; 1973 tpdcmd_q_R : Time := 0.484 ns; 1974 tpdcmd_q_F : Time := 0.522 ns; 1975 tpdi0_q_R : Time := 0.451 ns; 1976 tpdi0_q_F : Time := 0.469 ns; 1977 tpdi1_q_R : Time := 0.451 ns; 1978 tpdi1_q_F : Time := 0.469 ns; 1979 twdcmd_R : Time := 0.000 ns; 1980 twdcmd_F : Time := 0.000 ns; 1981 twdi0_R : Time := 0.000 ns; 1982 twdi0_F : Time := 0.000 ns; 1983 twdi1_R : Time := 0.000 ns; 1984 twdi1_F : Time := 0.000 ns); 1985 1986 port( 1987 cmd : in STD_LOGIC; 1988 i0 : in STD_LOGIC; 1989 i1 : in STD_LOGIC; 1990 q : out STD_LOGIC); 1991end mx2_x2; 1992 1993-- architecture body -- 1994library IEEE_ASIC; 1995use IEEE.STD_LOGIC_MISC.all; 1996use SYNOPSYS.attributes.backplane; 1997use SYNOPSYS.attributes.PRIVATE; 1998use SYNOPSYS.attributes.ASIC_CELL; 1999use SYNOPSYS.attributes.PROPAGATE_VALUE; 2000 2001architecture FTSM of mx2_x2 is 2002 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 2003 attribute PRIVATE of FTSM : architecture is TRUE; 2004 attribute ASIC_CELL of FTSM : architecture is TRUE; 2005 2006 -- Backannotation attributes 2007 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; 2008 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; 2009 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; 2010 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; 2011 attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is "U4/tLH"; 2012 attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is "U4/tHL"; 2013 attribute PROPAGATE_VALUE of twdi1_F: constant is "U3/tHL"; 2014 attribute PROPAGATE_VALUE of twdi1_R: constant is "U3/tLH"; 2015 attribute PROPAGATE_VALUE of twdi0_F: constant is "U2/tHL"; 2016 attribute PROPAGATE_VALUE of twdi0_R: constant is "U2/tLH"; 2017 attribute PROPAGATE_VALUE of twdcmd_F: constant is "U1/tHL"; 2018 attribute PROPAGATE_VALUE of twdcmd_R: constant is "U1/tLH"; 2019 2020 signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 2021 signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 2022 2023 component MUX2MAC 2024 generic( 2025 tpdY_R : Time := 0 ns; 2026 tpdY_F : Time := 0 ns; 2027 strn : STRENGTH := strn_X01); 2028 port( 2029 I0 : in STD_LOGIC; 2030 I1 : in STD_LOGIC; 2031 S0 : in STD_LOGIC; 2032 Y : out STD_LOGIC); 2033 end component; 2034 2035begin 2036 2037 -- Extrinsic delay buffers 2038 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 2039 generic map( tLH => twdcmd_R, tHL => twdcmd_F) 2040 port map( Input => cmd, Output => connect(0)); 2041 2042 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 2043 generic map( tLH => twdi0_R, tHL => twdi0_F) 2044 port map( Input => i0, Output => connect(1)); 2045 2046 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 2047 generic map( tLH => twdi1_R, tHL => twdi1_F) 2048 port map( Input => i1, Output => connect(2)); 2049 2050 -- Intrinsic delay buffers 2051 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 2052 generic map( tLH => tpdcmd_q_R, tHL => tpdcmd_q_F) 2053 port map( Input => connect(0), Output => prop_q(0)); 2054 2055 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 2056 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 2057 port map( Input => connect(1), Output => prop_q(1)); 2058 2059 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 2060 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 2061 port map( Input => connect(2), Output => prop_q(2)); 2062 2063 -- Netlist 2064 U7 : MUX2MAC 2065 port map( I0 => prop_q(1), I1 => prop_q(2), S0 => prop_q(0), Y => 2066 q); 2067 2068 2069end FTSM; 2070 2071configuration CFG_mx2_x2_FTSM of mx2_x2 is 2072 for FTSM 2073 end for; 2074end CFG_mx2_x2_FTSM; 2075 2076 2077----- CELL mx2_x4 ----- 2078library IEEE; 2079use IEEE.STD_LOGIC_1164.all; 2080library SYNOPSYS; 2081use SYNOPSYS.attributes.REAL_NAME; 2082 2083-- entity declaration -- 2084entity mx2_x4 is 2085 generic( 2086 Timing_mesg: Boolean := True; 2087 Timing_xgen: Boolean := False; 2088 tpdcmd_q_R : Time := 0.615 ns; 2089 tpdcmd_q_F : Time := 0.647 ns; 2090 tpdi0_q_R : Time := 0.564 ns; 2091 tpdi0_q_F : Time := 0.576 ns; 2092 tpdi1_q_R : Time := 0.564 ns; 2093 tpdi1_q_F : Time := 0.576 ns; 2094 twdcmd_R : Time := 0.000 ns; 2095 twdcmd_F : Time := 0.000 ns; 2096 twdi0_R : Time := 0.000 ns; 2097 twdi0_F : Time := 0.000 ns; 2098 twdi1_R : Time := 0.000 ns; 2099 twdi1_F : Time := 0.000 ns); 2100 2101 port( 2102 cmd : in STD_LOGIC; 2103 i0 : in STD_LOGIC; 2104 i1 : in STD_LOGIC; 2105 q : out STD_LOGIC); 2106end mx2_x4; 2107 2108-- architecture body -- 2109library IEEE_ASIC; 2110use IEEE.STD_LOGIC_MISC.all; 2111use SYNOPSYS.attributes.backplane; 2112use SYNOPSYS.attributes.PRIVATE; 2113use SYNOPSYS.attributes.ASIC_CELL; 2114use SYNOPSYS.attributes.PROPAGATE_VALUE; 2115 2116architecture FTSM of mx2_x4 is 2117 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 2118 attribute PRIVATE of FTSM : architecture is TRUE; 2119 attribute ASIC_CELL of FTSM : architecture is TRUE; 2120 2121 -- Backannotation attributes 2122 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; 2123 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; 2124 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; 2125 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; 2126 attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is "U4/tLH"; 2127 attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is "U4/tHL"; 2128 attribute PROPAGATE_VALUE of twdi1_F: constant is "U3/tHL"; 2129 attribute PROPAGATE_VALUE of twdi1_R: constant is "U3/tLH"; 2130 attribute PROPAGATE_VALUE of twdi0_F: constant is "U2/tHL"; 2131 attribute PROPAGATE_VALUE of twdi0_R: constant is "U2/tLH"; 2132 attribute PROPAGATE_VALUE of twdcmd_F: constant is "U1/tHL"; 2133 attribute PROPAGATE_VALUE of twdcmd_R: constant is "U1/tLH"; 2134 2135 signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 2136 signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 2137 2138 component MUX2MAC 2139 generic( 2140 tpdY_R : Time := 0 ns; 2141 tpdY_F : Time := 0 ns; 2142 strn : STRENGTH := strn_X01); 2143 port( 2144 I0 : in STD_LOGIC; 2145 I1 : in STD_LOGIC; 2146 S0 : in STD_LOGIC; 2147 Y : out STD_LOGIC); 2148 end component; 2149 2150begin 2151 2152 -- Extrinsic delay buffers 2153 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 2154 generic map( tLH => twdcmd_R, tHL => twdcmd_F) 2155 port map( Input => cmd, Output => connect(0)); 2156 2157 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 2158 generic map( tLH => twdi0_R, tHL => twdi0_F) 2159 port map( Input => i0, Output => connect(1)); 2160 2161 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 2162 generic map( tLH => twdi1_R, tHL => twdi1_F) 2163 port map( Input => i1, Output => connect(2)); 2164 2165 -- Intrinsic delay buffers 2166 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 2167 generic map( tLH => tpdcmd_q_R, tHL => tpdcmd_q_F) 2168 port map( Input => connect(0), Output => prop_q(0)); 2169 2170 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 2171 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 2172 port map( Input => connect(1), Output => prop_q(1)); 2173 2174 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 2175 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 2176 port map( Input => connect(2), Output => prop_q(2)); 2177 2178 -- Netlist 2179 U7 : MUX2MAC 2180 port map( I0 => prop_q(1), I1 => prop_q(2), S0 => prop_q(0), Y => 2181 q); 2182 2183 2184end FTSM; 2185 2186configuration CFG_mx2_x4_FTSM of mx2_x4 is 2187 for FTSM 2188 end for; 2189end CFG_mx2_x4_FTSM; 2190 2191 2192----- CELL mx3_x2 ----- 2193library IEEE; 2194use IEEE.STD_LOGIC_1164.all; 2195library SYNOPSYS; 2196use SYNOPSYS.attributes.REAL_NAME; 2197 2198-- entity declaration -- 2199entity mx3_x2 is 2200 generic( 2201 Timing_mesg: Boolean := True; 2202 Timing_xgen: Boolean := False; 2203 tpdcmd0_q_R : Time := 0.573 ns; 2204 tpdcmd0_q_F : Time := 0.680 ns; 2205 tpdcmd1_q_R : Time := 0.664 ns; 2206 tpdcmd1_q_F : Time := 0.817 ns; 2207 tpdi0_q_R : Time := 0.538 ns; 2208 tpdi0_q_F : Time := 0.658 ns; 2209 tpdi1_q_R : Time := 0.654 ns; 2210 tpdi1_q_F : Time := 0.808 ns; 2211 tpdi2_q_R : Time := 0.654 ns; 2212 tpdi2_q_F : Time := 0.808 ns; 2213 twdcmd0_R : Time := 0.000 ns; 2214 twdcmd0_F : Time := 0.000 ns; 2215 twdcmd1_R : Time := 0.000 ns; 2216 twdcmd1_F : Time := 0.000 ns; 2217 twdi0_R : Time := 0.000 ns; 2218 twdi0_F : Time := 0.000 ns; 2219 twdi1_R : Time := 0.000 ns; 2220 twdi1_F : Time := 0.000 ns; 2221 twdi2_R : Time := 0.000 ns; 2222 twdi2_F : Time := 0.000 ns); 2223 2224 port( 2225 cmd0 : in STD_LOGIC; 2226 cmd1 : in STD_LOGIC; 2227 i0 : in STD_LOGIC; 2228 i1 : in STD_LOGIC; 2229 i2 : in STD_LOGIC; 2230 q : out STD_LOGIC); 2231end mx3_x2; 2232 2233-- architecture body -- 2234library IEEE_ASIC; 2235use IEEE.STD_LOGIC_MISC.all; 2236use SYNOPSYS.attributes.backplane; 2237use SYNOPSYS.attributes.PRIVATE; 2238use SYNOPSYS.attributes.ASIC_CELL; 2239use SYNOPSYS.attributes.PROPAGATE_VALUE; 2240 2241architecture FTSM of mx3_x2 is 2242 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 2243 attribute PRIVATE of FTSM : architecture is TRUE; 2244 attribute ASIC_CELL of FTSM : architecture is TRUE; 2245 2246 -- Backannotation attributes 2247 attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U10/tLH"; 2248 attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U10/tHL"; 2249 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U9/tLH"; 2250 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U9/tHL"; 2251 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U8/tLH"; 2252 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U8/tHL"; 2253 attribute PROPAGATE_VALUE of tpdcmd1_q_R: constant is "U7/tLH"; 2254 attribute PROPAGATE_VALUE of tpdcmd1_q_F: constant is "U7/tHL"; 2255 attribute PROPAGATE_VALUE of tpdcmd0_q_R: constant is "U6/tLH"; 2256 attribute PROPAGATE_VALUE of tpdcmd0_q_F: constant is "U6/tHL"; 2257 attribute PROPAGATE_VALUE of twdi2_F: constant is "U5/tHL"; 2258 attribute PROPAGATE_VALUE of twdi2_R: constant is "U5/tLH"; 2259 attribute PROPAGATE_VALUE of twdi1_F: constant is "U4/tHL"; 2260 attribute PROPAGATE_VALUE of twdi1_R: constant is "U4/tLH"; 2261 attribute PROPAGATE_VALUE of twdi0_F: constant is "U3/tHL"; 2262 attribute PROPAGATE_VALUE of twdi0_R: constant is "U3/tLH"; 2263 attribute PROPAGATE_VALUE of twdcmd1_F: constant is "U2/tHL"; 2264 attribute PROPAGATE_VALUE of twdcmd1_R: constant is "U2/tLH"; 2265 attribute PROPAGATE_VALUE of twdcmd0_F: constant is "U1/tHL"; 2266 attribute PROPAGATE_VALUE of twdcmd0_R: constant is "U1/tLH"; 2267 2268 signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); 2269 signal prop_q : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); 2270 signal n1 : STD_LOGIC; 2271 2272 component MUX2MAC 2273 generic( 2274 tpdY_R : Time := 0 ns; 2275 tpdY_F : Time := 0 ns; 2276 strn : STRENGTH := strn_X01); 2277 port( 2278 I0 : in STD_LOGIC; 2279 I1 : in STD_LOGIC; 2280 S0 : in STD_LOGIC; 2281 Y : out STD_LOGIC); 2282 end component; 2283 2284begin 2285 2286 -- Extrinsic delay buffers 2287 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 2288 generic map( tLH => twdcmd0_R, tHL => twdcmd0_F) 2289 port map( Input => cmd0, Output => connect(0)); 2290 2291 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 2292 generic map( tLH => twdcmd1_R, tHL => twdcmd1_F) 2293 port map( Input => cmd1, Output => connect(1)); 2294 2295 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 2296 generic map( tLH => twdi0_R, tHL => twdi0_F) 2297 port map( Input => i0, Output => connect(2)); 2298 2299 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 2300 generic map( tLH => twdi1_R, tHL => twdi1_F) 2301 port map( Input => i1, Output => connect(3)); 2302 2303 U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 2304 generic map( tLH => twdi2_R, tHL => twdi2_F) 2305 port map( Input => i2, Output => connect(4)); 2306 2307 -- Intrinsic delay buffers 2308 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 2309 generic map( tLH => tpdcmd0_q_R, tHL => tpdcmd0_q_F) 2310 port map( Input => connect(0), Output => prop_q(0)); 2311 2312 U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 2313 generic map( tLH => tpdcmd1_q_R, tHL => tpdcmd1_q_F) 2314 port map( Input => connect(1), Output => prop_q(1)); 2315 2316 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 2317 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 2318 port map( Input => connect(2), Output => prop_q(2)); 2319 2320 U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 2321 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 2322 port map( Input => connect(3), Output => prop_q(3)); 2323 2324 U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 2325 generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) 2326 port map( Input => connect(4), Output => prop_q(4)); 2327 2328 -- Netlist 2329 U11 : MUX2MAC 2330 port map( I0 => prop_q(4), I1 => prop_q(3), S0 => prop_q(1), Y => 2331 n1); 2332 2333 U12 : MUX2MAC 2334 port map( I0 => prop_q(2), I1 => n1, S0 => prop_q(0), Y => q); 2335 2336 2337end FTSM; 2338 2339configuration CFG_mx3_x2_FTSM of mx3_x2 is 2340 for FTSM 2341 end for; 2342end CFG_mx3_x2_FTSM; 2343 2344 2345----- CELL mx3_x4 ----- 2346library IEEE; 2347use IEEE.STD_LOGIC_1164.all; 2348library SYNOPSYS; 2349use SYNOPSYS.attributes.REAL_NAME; 2350 2351-- entity declaration -- 2352entity mx3_x4 is 2353 generic( 2354 Timing_mesg: Boolean := True; 2355 Timing_xgen: Boolean := False; 2356 tpdcmd0_q_R : Time := 0.683 ns; 2357 tpdcmd0_q_F : Time := 0.779 ns; 2358 tpdcmd1_q_R : Time := 0.792 ns; 2359 tpdcmd1_q_F : Time := 0.967 ns; 2360 tpdi0_q_R : Time := 0.640 ns; 2361 tpdi0_q_F : Time := 0.774 ns; 2362 tpdi1_q_R : Time := 0.770 ns; 2363 tpdi1_q_F : Time := 0.948 ns; 2364 tpdi2_q_R : Time := 0.770 ns; 2365 tpdi2_q_F : Time := 0.948 ns; 2366 twdcmd0_R : Time := 0.000 ns; 2367 twdcmd0_F : Time := 0.000 ns; 2368 twdcmd1_R : Time := 0.000 ns; 2369 twdcmd1_F : Time := 0.000 ns; 2370 twdi0_R : Time := 0.000 ns; 2371 twdi0_F : Time := 0.000 ns; 2372 twdi1_R : Time := 0.000 ns; 2373 twdi1_F : Time := 0.000 ns; 2374 twdi2_R : Time := 0.000 ns; 2375 twdi2_F : Time := 0.000 ns); 2376 2377 port( 2378 cmd0 : in STD_LOGIC; 2379 cmd1 : in STD_LOGIC; 2380 i0 : in STD_LOGIC; 2381 i1 : in STD_LOGIC; 2382 i2 : in STD_LOGIC; 2383 q : out STD_LOGIC); 2384end mx3_x4; 2385 2386-- architecture body -- 2387library IEEE_ASIC; 2388use IEEE.STD_LOGIC_MISC.all; 2389use SYNOPSYS.attributes.backplane; 2390use SYNOPSYS.attributes.PRIVATE; 2391use SYNOPSYS.attributes.ASIC_CELL; 2392use SYNOPSYS.attributes.PROPAGATE_VALUE; 2393 2394architecture FTSM of mx3_x4 is 2395 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 2396 attribute PRIVATE of FTSM : architecture is TRUE; 2397 attribute ASIC_CELL of FTSM : architecture is TRUE; 2398 2399 -- Backannotation attributes 2400 attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U10/tLH"; 2401 attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U10/tHL"; 2402 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U9/tLH"; 2403 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U9/tHL"; 2404 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U8/tLH"; 2405 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U8/tHL"; 2406 attribute PROPAGATE_VALUE of tpdcmd1_q_R: constant is "U7/tLH"; 2407 attribute PROPAGATE_VALUE of tpdcmd1_q_F: constant is "U7/tHL"; 2408 attribute PROPAGATE_VALUE of tpdcmd0_q_R: constant is "U6/tLH"; 2409 attribute PROPAGATE_VALUE of tpdcmd0_q_F: constant is "U6/tHL"; 2410 attribute PROPAGATE_VALUE of twdi2_F: constant is "U5/tHL"; 2411 attribute PROPAGATE_VALUE of twdi2_R: constant is "U5/tLH"; 2412 attribute PROPAGATE_VALUE of twdi1_F: constant is "U4/tHL"; 2413 attribute PROPAGATE_VALUE of twdi1_R: constant is "U4/tLH"; 2414 attribute PROPAGATE_VALUE of twdi0_F: constant is "U3/tHL"; 2415 attribute PROPAGATE_VALUE of twdi0_R: constant is "U3/tLH"; 2416 attribute PROPAGATE_VALUE of twdcmd1_F: constant is "U2/tHL"; 2417 attribute PROPAGATE_VALUE of twdcmd1_R: constant is "U2/tLH"; 2418 attribute PROPAGATE_VALUE of twdcmd0_F: constant is "U1/tHL"; 2419 attribute PROPAGATE_VALUE of twdcmd0_R: constant is "U1/tLH"; 2420 2421 signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); 2422 signal prop_q : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); 2423 signal n1 : STD_LOGIC; 2424 2425 component MUX2MAC 2426 generic( 2427 tpdY_R : Time := 0 ns; 2428 tpdY_F : Time := 0 ns; 2429 strn : STRENGTH := strn_X01); 2430 port( 2431 I0 : in STD_LOGIC; 2432 I1 : in STD_LOGIC; 2433 S0 : in STD_LOGIC; 2434 Y : out STD_LOGIC); 2435 end component; 2436 2437begin 2438 2439 -- Extrinsic delay buffers 2440 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 2441 generic map( tLH => twdcmd0_R, tHL => twdcmd0_F) 2442 port map( Input => cmd0, Output => connect(0)); 2443 2444 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 2445 generic map( tLH => twdcmd1_R, tHL => twdcmd1_F) 2446 port map( Input => cmd1, Output => connect(1)); 2447 2448 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 2449 generic map( tLH => twdi0_R, tHL => twdi0_F) 2450 port map( Input => i0, Output => connect(2)); 2451 2452 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 2453 generic map( tLH => twdi1_R, tHL => twdi1_F) 2454 port map( Input => i1, Output => connect(3)); 2455 2456 U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 2457 generic map( tLH => twdi2_R, tHL => twdi2_F) 2458 port map( Input => i2, Output => connect(4)); 2459 2460 -- Intrinsic delay buffers 2461 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 2462 generic map( tLH => tpdcmd0_q_R, tHL => tpdcmd0_q_F) 2463 port map( Input => connect(0), Output => prop_q(0)); 2464 2465 U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 2466 generic map( tLH => tpdcmd1_q_R, tHL => tpdcmd1_q_F) 2467 port map( Input => connect(1), Output => prop_q(1)); 2468 2469 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 2470 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 2471 port map( Input => connect(2), Output => prop_q(2)); 2472 2473 U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 2474 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 2475 port map( Input => connect(3), Output => prop_q(3)); 2476 2477 U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 2478 generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) 2479 port map( Input => connect(4), Output => prop_q(4)); 2480 2481 -- Netlist 2482 U11 : MUX2MAC 2483 port map( I0 => prop_q(4), I1 => prop_q(3), S0 => prop_q(1), Y => 2484 n1); 2485 2486 U12 : MUX2MAC 2487 port map( I0 => prop_q(2), I1 => n1, S0 => prop_q(0), Y => q); 2488 2489 2490end FTSM; 2491 2492configuration CFG_mx3_x4_FTSM of mx3_x4 is 2493 for FTSM 2494 end for; 2495end CFG_mx3_x4_FTSM; 2496 2497 2498----- CELL na2_x1 ----- 2499library IEEE; 2500use IEEE.STD_LOGIC_1164.all; 2501library SYNOPSYS; 2502use SYNOPSYS.attributes.REAL_NAME; 2503 2504-- entity declaration -- 2505entity na2_x1 is 2506 generic( 2507 Timing_mesg: Boolean := True; 2508 Timing_xgen: Boolean := False; 2509 tpdi0_nq_R : Time := 0.059 ns; 2510 tpdi0_nq_F : Time := 0.288 ns; 2511 tpdi1_nq_R : Time := 0.111 ns; 2512 tpdi1_nq_F : Time := 0.234 ns; 2513 twdi0_R : Time := 0.000 ns; 2514 twdi0_F : Time := 0.000 ns; 2515 twdi1_R : Time := 0.000 ns; 2516 twdi1_F : Time := 0.000 ns); 2517 2518 port( 2519 i0 : in STD_LOGIC; 2520 i1 : in STD_LOGIC; 2521 nq : out STD_LOGIC); 2522end na2_x1; 2523 2524-- architecture body -- 2525library IEEE_ASIC; 2526use IEEE.STD_LOGIC_MISC.all; 2527use SYNOPSYS.attributes.backplane; 2528use SYNOPSYS.attributes.PRIVATE; 2529use SYNOPSYS.attributes.ASIC_CELL; 2530use SYNOPSYS.attributes.PROPAGATE_VALUE; 2531 2532architecture FTSM of na2_x1 is 2533 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 2534 attribute PRIVATE of FTSM : architecture is TRUE; 2535 attribute ASIC_CELL of FTSM : architecture is TRUE; 2536 2537 -- Backannotation attributes 2538 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U4/tLH"; 2539 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U4/tHL"; 2540 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U3/tLH"; 2541 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U3/tHL"; 2542 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 2543 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 2544 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 2545 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 2546 2547 signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 2548 signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 2549 2550 component NAND2MAC 2551 generic( 2552 tpdY_R : Time := 0 ns; 2553 tpdY_F : Time := 0 ns; 2554 strn : STRENGTH := strn_X01); 2555 port( 2556 I0 : in STD_LOGIC; 2557 I1 : in STD_LOGIC; 2558 Y : out STD_LOGIC); 2559 end component; 2560 2561begin 2562 2563 -- Extrinsic delay buffers 2564 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 2565 generic map( tLH => twdi0_R, tHL => twdi0_F) 2566 port map( Input => i0, Output => connect(0)); 2567 2568 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 2569 generic map( tLH => twdi1_R, tHL => twdi1_F) 2570 port map( Input => i1, Output => connect(1)); 2571 2572 -- Intrinsic delay buffers 2573 U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 2574 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 2575 port map( Input => connect(0), Output => prop_nq(0)); 2576 2577 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 2578 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 2579 port map( Input => connect(1), Output => prop_nq(1)); 2580 2581 -- Netlist 2582 U5 : NAND2MAC 2583 port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => nq); 2584 2585 2586end FTSM; 2587 2588configuration CFG_na2_x1_FTSM of na2_x1 is 2589 for FTSM 2590 end for; 2591end CFG_na2_x1_FTSM; 2592 2593 2594----- CELL na2_x4 ----- 2595library IEEE; 2596use IEEE.STD_LOGIC_1164.all; 2597library SYNOPSYS; 2598use SYNOPSYS.attributes.REAL_NAME; 2599 2600-- entity declaration -- 2601entity na2_x4 is 2602 generic( 2603 Timing_mesg: Boolean := True; 2604 Timing_xgen: Boolean := False; 2605 tpdi0_nq_R : Time := 0.412 ns; 2606 tpdi0_nq_F : Time := 0.552 ns; 2607 tpdi1_nq_R : Time := 0.353 ns; 2608 tpdi1_nq_F : Time := 0.601 ns; 2609 twdi0_R : Time := 0.000 ns; 2610 twdi0_F : Time := 0.000 ns; 2611 twdi1_R : Time := 0.000 ns; 2612 twdi1_F : Time := 0.000 ns); 2613 2614 port( 2615 i0 : in STD_LOGIC; 2616 i1 : in STD_LOGIC; 2617 nq : out STD_LOGIC); 2618end na2_x4; 2619 2620-- architecture body -- 2621library IEEE_ASIC; 2622use IEEE.STD_LOGIC_MISC.all; 2623use SYNOPSYS.attributes.backplane; 2624use SYNOPSYS.attributes.PRIVATE; 2625use SYNOPSYS.attributes.ASIC_CELL; 2626use SYNOPSYS.attributes.PROPAGATE_VALUE; 2627 2628architecture FTSM of na2_x4 is 2629 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 2630 attribute PRIVATE of FTSM : architecture is TRUE; 2631 attribute ASIC_CELL of FTSM : architecture is TRUE; 2632 2633 -- Backannotation attributes 2634 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U4/tLH"; 2635 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U4/tHL"; 2636 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U3/tLH"; 2637 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U3/tHL"; 2638 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 2639 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 2640 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 2641 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 2642 2643 signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 2644 signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 2645 2646 component NAND2MAC 2647 generic( 2648 tpdY_R : Time := 0 ns; 2649 tpdY_F : Time := 0 ns; 2650 strn : STRENGTH := strn_X01); 2651 port( 2652 I0 : in STD_LOGIC; 2653 I1 : in STD_LOGIC; 2654 Y : out STD_LOGIC); 2655 end component; 2656 2657begin 2658 2659 -- Extrinsic delay buffers 2660 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 2661 generic map( tLH => twdi0_R, tHL => twdi0_F) 2662 port map( Input => i0, Output => connect(0)); 2663 2664 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 2665 generic map( tLH => twdi1_R, tHL => twdi1_F) 2666 port map( Input => i1, Output => connect(1)); 2667 2668 -- Intrinsic delay buffers 2669 U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 2670 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 2671 port map( Input => connect(0), Output => prop_nq(0)); 2672 2673 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 2674 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 2675 port map( Input => connect(1), Output => prop_nq(1)); 2676 2677 -- Netlist 2678 U5 : NAND2MAC 2679 port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => nq); 2680 2681 2682end FTSM; 2683 2684configuration CFG_na2_x4_FTSM of na2_x4 is 2685 for FTSM 2686 end for; 2687end CFG_na2_x4_FTSM; 2688 2689 2690----- CELL na3_x1 ----- 2691library IEEE; 2692use IEEE.STD_LOGIC_1164.all; 2693library SYNOPSYS; 2694use SYNOPSYS.attributes.REAL_NAME; 2695 2696-- entity declaration -- 2697entity na3_x1 is 2698 generic( 2699 Timing_mesg: Boolean := True; 2700 Timing_xgen: Boolean := False; 2701 tpdi0_nq_R : Time := 0.119 ns; 2702 tpdi0_nq_F : Time := 0.363 ns; 2703 tpdi1_nq_R : Time := 0.171 ns; 2704 tpdi1_nq_F : Time := 0.316 ns; 2705 tpdi2_nq_R : Time := 0.193 ns; 2706 tpdi2_nq_F : Time := 0.265 ns; 2707 twdi0_R : Time := 0.000 ns; 2708 twdi0_F : Time := 0.000 ns; 2709 twdi1_R : Time := 0.000 ns; 2710 twdi1_F : Time := 0.000 ns; 2711 twdi2_R : Time := 0.000 ns; 2712 twdi2_F : Time := 0.000 ns); 2713 2714 port( 2715 i0 : in STD_LOGIC; 2716 i1 : in STD_LOGIC; 2717 i2 : in STD_LOGIC; 2718 nq : out STD_LOGIC); 2719end na3_x1; 2720 2721-- architecture body -- 2722library IEEE_ASIC; 2723use IEEE.STD_LOGIC_MISC.all; 2724use SYNOPSYS.attributes.backplane; 2725use SYNOPSYS.attributes.PRIVATE; 2726use SYNOPSYS.attributes.ASIC_CELL; 2727use SYNOPSYS.attributes.PROPAGATE_VALUE; 2728 2729architecture FTSM of na3_x1 is 2730 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 2731 attribute PRIVATE of FTSM : architecture is TRUE; 2732 attribute ASIC_CELL of FTSM : architecture is TRUE; 2733 2734 -- Backannotation attributes 2735 attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; 2736 attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; 2737 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; 2738 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; 2739 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; 2740 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; 2741 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 2742 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 2743 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 2744 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 2745 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 2746 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 2747 2748 signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 2749 signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 2750 2751 component NAND3MAC 2752 generic( 2753 tpdY_R : Time := 0 ns; 2754 tpdY_F : Time := 0 ns; 2755 strn : STRENGTH := strn_X01); 2756 port( 2757 I0 : in STD_LOGIC; 2758 I1 : in STD_LOGIC; 2759 I2 : in STD_LOGIC; 2760 Y : out STD_LOGIC); 2761 end component; 2762 2763begin 2764 2765 -- Extrinsic delay buffers 2766 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 2767 generic map( tLH => twdi0_R, tHL => twdi0_F) 2768 port map( Input => i0, Output => connect(0)); 2769 2770 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 2771 generic map( tLH => twdi1_R, tHL => twdi1_F) 2772 port map( Input => i1, Output => connect(1)); 2773 2774 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 2775 generic map( tLH => twdi2_R, tHL => twdi2_F) 2776 port map( Input => i2, Output => connect(2)); 2777 2778 -- Intrinsic delay buffers 2779 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 2780 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 2781 port map( Input => connect(0), Output => prop_nq(0)); 2782 2783 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 2784 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 2785 port map( Input => connect(1), Output => prop_nq(1)); 2786 2787 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 2788 generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) 2789 port map( Input => connect(2), Output => prop_nq(2)); 2790 2791 -- Netlist 2792 U7 : NAND3MAC 2793 port map( I0 => prop_nq(1), I1 => prop_nq(2), I2 => prop_nq(0), Y => 2794 nq); 2795 2796 2797end FTSM; 2798 2799configuration CFG_na3_x1_FTSM of na3_x1 is 2800 for FTSM 2801 end for; 2802end CFG_na3_x1_FTSM; 2803 2804 2805----- CELL na3_x4 ----- 2806library IEEE; 2807use IEEE.STD_LOGIC_1164.all; 2808library SYNOPSYS; 2809use SYNOPSYS.attributes.REAL_NAME; 2810 2811-- entity declaration -- 2812entity na3_x4 is 2813 generic( 2814 Timing_mesg: Boolean := True; 2815 Timing_xgen: Boolean := False; 2816 tpdi0_nq_R : Time := 0.556 ns; 2817 tpdi0_nq_F : Time := 0.601 ns; 2818 tpdi1_nq_R : Time := 0.460 ns; 2819 tpdi1_nq_F : Time := 0.691 ns; 2820 tpdi2_nq_R : Time := 0.519 ns; 2821 tpdi2_nq_F : Time := 0.647 ns; 2822 twdi0_R : Time := 0.000 ns; 2823 twdi0_F : Time := 0.000 ns; 2824 twdi1_R : Time := 0.000 ns; 2825 twdi1_F : Time := 0.000 ns; 2826 twdi2_R : Time := 0.000 ns; 2827 twdi2_F : Time := 0.000 ns); 2828 2829 port( 2830 i0 : in STD_LOGIC; 2831 i1 : in STD_LOGIC; 2832 i2 : in STD_LOGIC; 2833 nq : out STD_LOGIC); 2834end na3_x4; 2835 2836-- architecture body -- 2837library IEEE_ASIC; 2838use IEEE.STD_LOGIC_MISC.all; 2839use SYNOPSYS.attributes.backplane; 2840use SYNOPSYS.attributes.PRIVATE; 2841use SYNOPSYS.attributes.ASIC_CELL; 2842use SYNOPSYS.attributes.PROPAGATE_VALUE; 2843 2844architecture FTSM of na3_x4 is 2845 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 2846 attribute PRIVATE of FTSM : architecture is TRUE; 2847 attribute ASIC_CELL of FTSM : architecture is TRUE; 2848 2849 -- Backannotation attributes 2850 attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; 2851 attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; 2852 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; 2853 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; 2854 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; 2855 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; 2856 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 2857 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 2858 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 2859 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 2860 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 2861 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 2862 2863 signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 2864 signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 2865 2866 component NAND3MAC 2867 generic( 2868 tpdY_R : Time := 0 ns; 2869 tpdY_F : Time := 0 ns; 2870 strn : STRENGTH := strn_X01); 2871 port( 2872 I0 : in STD_LOGIC; 2873 I1 : in STD_LOGIC; 2874 I2 : in STD_LOGIC; 2875 Y : out STD_LOGIC); 2876 end component; 2877 2878begin 2879 2880 -- Extrinsic delay buffers 2881 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 2882 generic map( tLH => twdi0_R, tHL => twdi0_F) 2883 port map( Input => i0, Output => connect(0)); 2884 2885 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 2886 generic map( tLH => twdi1_R, tHL => twdi1_F) 2887 port map( Input => i1, Output => connect(1)); 2888 2889 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 2890 generic map( tLH => twdi2_R, tHL => twdi2_F) 2891 port map( Input => i2, Output => connect(2)); 2892 2893 -- Intrinsic delay buffers 2894 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 2895 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 2896 port map( Input => connect(0), Output => prop_nq(0)); 2897 2898 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 2899 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 2900 port map( Input => connect(1), Output => prop_nq(1)); 2901 2902 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 2903 generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) 2904 port map( Input => connect(2), Output => prop_nq(2)); 2905 2906 -- Netlist 2907 U7 : NAND3MAC 2908 port map( I0 => prop_nq(1), I1 => prop_nq(2), I2 => prop_nq(0), Y => 2909 nq); 2910 2911 2912end FTSM; 2913 2914configuration CFG_na3_x4_FTSM of na3_x4 is 2915 for FTSM 2916 end for; 2917end CFG_na3_x4_FTSM; 2918 2919 2920----- CELL na4_x1 ----- 2921library IEEE; 2922use IEEE.STD_LOGIC_1164.all; 2923library SYNOPSYS; 2924use SYNOPSYS.attributes.REAL_NAME; 2925 2926-- entity declaration -- 2927entity na4_x1 is 2928 generic( 2929 Timing_mesg: Boolean := True; 2930 Timing_xgen: Boolean := False; 2931 tpdi0_nq_R : Time := 0.179 ns; 2932 tpdi0_nq_F : Time := 0.438 ns; 2933 tpdi1_nq_R : Time := 0.237 ns; 2934 tpdi1_nq_F : Time := 0.395 ns; 2935 tpdi2_nq_R : Time := 0.269 ns; 2936 tpdi2_nq_F : Time := 0.350 ns; 2937 tpdi3_nq_R : Time := 0.282 ns; 2938 tpdi3_nq_F : Time := 0.302 ns; 2939 twdi0_R : Time := 0.000 ns; 2940 twdi0_F : Time := 0.000 ns; 2941 twdi1_R : Time := 0.000 ns; 2942 twdi1_F : Time := 0.000 ns; 2943 twdi2_R : Time := 0.000 ns; 2944 twdi2_F : Time := 0.000 ns; 2945 twdi3_R : Time := 0.000 ns; 2946 twdi3_F : Time := 0.000 ns); 2947 2948 port( 2949 i0 : in STD_LOGIC; 2950 i1 : in STD_LOGIC; 2951 i2 : in STD_LOGIC; 2952 i3 : in STD_LOGIC; 2953 nq : out STD_LOGIC); 2954end na4_x1; 2955 2956-- architecture body -- 2957library IEEE_ASIC; 2958use IEEE.STD_LOGIC_MISC.all; 2959use SYNOPSYS.attributes.backplane; 2960use SYNOPSYS.attributes.PRIVATE; 2961use SYNOPSYS.attributes.ASIC_CELL; 2962use SYNOPSYS.attributes.PROPAGATE_VALUE; 2963 2964architecture FTSM of na4_x1 is 2965 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 2966 attribute PRIVATE of FTSM : architecture is TRUE; 2967 attribute ASIC_CELL of FTSM : architecture is TRUE; 2968 2969 -- Backannotation attributes 2970 attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; 2971 attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; 2972 attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; 2973 attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; 2974 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; 2975 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; 2976 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; 2977 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; 2978 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 2979 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 2980 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 2981 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 2982 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 2983 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 2984 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 2985 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 2986 2987 signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 2988 signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 2989 2990 component NAND4MAC 2991 generic( 2992 tpdY_R : Time := 0 ns; 2993 tpdY_F : Time := 0 ns; 2994 strn : STRENGTH := strn_X01); 2995 port( 2996 I0 : in STD_LOGIC; 2997 I1 : in STD_LOGIC; 2998 I2 : in STD_LOGIC; 2999 I3 : in STD_LOGIC; 3000 Y : out STD_LOGIC); 3001 end component; 3002 3003begin 3004 3005 -- Extrinsic delay buffers 3006 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 3007 generic map( tLH => twdi0_R, tHL => twdi0_F) 3008 port map( Input => i0, Output => connect(0)); 3009 3010 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 3011 generic map( tLH => twdi1_R, tHL => twdi1_F) 3012 port map( Input => i1, Output => connect(1)); 3013 3014 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 3015 generic map( tLH => twdi2_R, tHL => twdi2_F) 3016 port map( Input => i2, Output => connect(2)); 3017 3018 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 3019 generic map( tLH => twdi3_R, tHL => twdi3_F) 3020 port map( Input => i3, Output => connect(3)); 3021 3022 -- Intrinsic delay buffers 3023 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 3024 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 3025 port map( Input => connect(0), Output => prop_nq(0)); 3026 3027 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 3028 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 3029 port map( Input => connect(1), Output => prop_nq(1)); 3030 3031 U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 3032 generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) 3033 port map( Input => connect(2), Output => prop_nq(2)); 3034 3035 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 3036 generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) 3037 port map( Input => connect(3), Output => prop_nq(3)); 3038 3039 -- Netlist 3040 U9 : NAND4MAC 3041 port map( I0 => prop_nq(0), I1 => prop_nq(1), I2 => prop_nq(2), I3 => 3042 prop_nq(3), Y => nq); 3043 3044 3045end FTSM; 3046 3047configuration CFG_na4_x1_FTSM of na4_x1 is 3048 for FTSM 3049 end for; 3050end CFG_na4_x1_FTSM; 3051 3052 3053----- CELL na4_x4 ----- 3054library IEEE; 3055use IEEE.STD_LOGIC_1164.all; 3056library SYNOPSYS; 3057use SYNOPSYS.attributes.REAL_NAME; 3058 3059-- entity declaration -- 3060entity na4_x4 is 3061 generic( 3062 Timing_mesg: Boolean := True; 3063 Timing_xgen: Boolean := False; 3064 tpdi0_nq_R : Time := 0.578 ns; 3065 tpdi0_nq_F : Time := 0.771 ns; 3066 tpdi1_nq_R : Time := 0.643 ns; 3067 tpdi1_nq_F : Time := 0.731 ns; 3068 tpdi2_nq_R : Time := 0.681 ns; 3069 tpdi2_nq_F : Time := 0.689 ns; 3070 tpdi3_nq_R : Time := 0.703 ns; 3071 tpdi3_nq_F : Time := 0.644 ns; 3072 twdi0_R : Time := 0.000 ns; 3073 twdi0_F : Time := 0.000 ns; 3074 twdi1_R : Time := 0.000 ns; 3075 twdi1_F : Time := 0.000 ns; 3076 twdi2_R : Time := 0.000 ns; 3077 twdi2_F : Time := 0.000 ns; 3078 twdi3_R : Time := 0.000 ns; 3079 twdi3_F : Time := 0.000 ns); 3080 3081 port( 3082 i0 : in STD_LOGIC; 3083 i1 : in STD_LOGIC; 3084 i2 : in STD_LOGIC; 3085 i3 : in STD_LOGIC; 3086 nq : out STD_LOGIC); 3087end na4_x4; 3088 3089-- architecture body -- 3090library IEEE_ASIC; 3091use IEEE.STD_LOGIC_MISC.all; 3092use SYNOPSYS.attributes.backplane; 3093use SYNOPSYS.attributes.PRIVATE; 3094use SYNOPSYS.attributes.ASIC_CELL; 3095use SYNOPSYS.attributes.PROPAGATE_VALUE; 3096 3097architecture FTSM of na4_x4 is 3098 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 3099 attribute PRIVATE of FTSM : architecture is TRUE; 3100 attribute ASIC_CELL of FTSM : architecture is TRUE; 3101 3102 -- Backannotation attributes 3103 attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; 3104 attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; 3105 attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; 3106 attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; 3107 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; 3108 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; 3109 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; 3110 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; 3111 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 3112 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 3113 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 3114 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 3115 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 3116 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 3117 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 3118 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 3119 3120 signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 3121 signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 3122 3123 component NAND4MAC 3124 generic( 3125 tpdY_R : Time := 0 ns; 3126 tpdY_F : Time := 0 ns; 3127 strn : STRENGTH := strn_X01); 3128 port( 3129 I0 : in STD_LOGIC; 3130 I1 : in STD_LOGIC; 3131 I2 : in STD_LOGIC; 3132 I3 : in STD_LOGIC; 3133 Y : out STD_LOGIC); 3134 end component; 3135 3136begin 3137 3138 -- Extrinsic delay buffers 3139 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 3140 generic map( tLH => twdi0_R, tHL => twdi0_F) 3141 port map( Input => i0, Output => connect(0)); 3142 3143 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 3144 generic map( tLH => twdi1_R, tHL => twdi1_F) 3145 port map( Input => i1, Output => connect(1)); 3146 3147 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 3148 generic map( tLH => twdi2_R, tHL => twdi2_F) 3149 port map( Input => i2, Output => connect(2)); 3150 3151 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 3152 generic map( tLH => twdi3_R, tHL => twdi3_F) 3153 port map( Input => i3, Output => connect(3)); 3154 3155 -- Intrinsic delay buffers 3156 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 3157 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 3158 port map( Input => connect(0), Output => prop_nq(0)); 3159 3160 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 3161 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 3162 port map( Input => connect(1), Output => prop_nq(1)); 3163 3164 U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 3165 generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) 3166 port map( Input => connect(2), Output => prop_nq(2)); 3167 3168 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 3169 generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) 3170 port map( Input => connect(3), Output => prop_nq(3)); 3171 3172 -- Netlist 3173 U9 : NAND4MAC 3174 port map( I0 => prop_nq(0), I1 => prop_nq(1), I2 => prop_nq(2), I3 => 3175 prop_nq(3), Y => nq); 3176 3177 3178end FTSM; 3179 3180configuration CFG_na4_x4_FTSM of na4_x4 is 3181 for FTSM 3182 end for; 3183end CFG_na4_x4_FTSM; 3184 3185 3186----- CELL nao2o22_x1 ----- 3187library IEEE; 3188use IEEE.STD_LOGIC_1164.all; 3189library SYNOPSYS; 3190use SYNOPSYS.attributes.REAL_NAME; 3191 3192-- entity declaration -- 3193entity nao2o22_x1 is 3194 generic( 3195 Timing_mesg: Boolean := True; 3196 Timing_xgen: Boolean := False; 3197 tpdi0_nq_R : Time := 0.294 ns; 3198 tpdi0_nq_F : Time := 0.226 ns; 3199 tpdi1_nq_R : Time := 0.218 ns; 3200 tpdi1_nq_F : Time := 0.287 ns; 3201 tpdi2_nq_R : Time := 0.237 ns; 3202 tpdi2_nq_F : Time := 0.307 ns; 3203 tpdi3_nq_R : Time := 0.174 ns; 3204 tpdi3_nq_F : Time := 0.382 ns; 3205 twdi0_R : Time := 0.000 ns; 3206 twdi0_F : Time := 0.000 ns; 3207 twdi1_R : Time := 0.000 ns; 3208 twdi1_F : Time := 0.000 ns; 3209 twdi2_R : Time := 0.000 ns; 3210 twdi2_F : Time := 0.000 ns; 3211 twdi3_R : Time := 0.000 ns; 3212 twdi3_F : Time := 0.000 ns); 3213 3214 port( 3215 i0 : in STD_LOGIC; 3216 i1 : in STD_LOGIC; 3217 i2 : in STD_LOGIC; 3218 i3 : in STD_LOGIC; 3219 nq : out STD_LOGIC); 3220end nao2o22_x1; 3221 3222-- architecture body -- 3223library IEEE_ASIC; 3224use IEEE.STD_LOGIC_MISC.all; 3225use SYNOPSYS.attributes.backplane; 3226use SYNOPSYS.attributes.PRIVATE; 3227use SYNOPSYS.attributes.ASIC_CELL; 3228use SYNOPSYS.attributes.PROPAGATE_VALUE; 3229 3230architecture FTSM of nao2o22_x1 is 3231 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 3232 attribute PRIVATE of FTSM : architecture is TRUE; 3233 attribute ASIC_CELL of FTSM : architecture is TRUE; 3234 3235 -- Backannotation attributes 3236 attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; 3237 attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; 3238 attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; 3239 attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; 3240 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; 3241 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; 3242 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; 3243 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; 3244 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 3245 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 3246 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 3247 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 3248 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 3249 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 3250 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 3251 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 3252 3253 signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 3254 signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 3255 signal n1, n2 : STD_LOGIC; 3256 3257 component NAND2MAC 3258 generic( 3259 tpdY_R : Time := 0 ns; 3260 tpdY_F : Time := 0 ns; 3261 strn : STRENGTH := strn_X01); 3262 port( 3263 I0 : in STD_LOGIC; 3264 I1 : in STD_LOGIC; 3265 Y : out STD_LOGIC); 3266 end component; 3267 3268 component OR2MAC 3269 generic( 3270 tpdY_R : Time := 0 ns; 3271 tpdY_F : Time := 0 ns; 3272 strn : STRENGTH := strn_X01); 3273 port( 3274 I0 : in STD_LOGIC; 3275 I1 : in STD_LOGIC; 3276 Y : out STD_LOGIC); 3277 end component; 3278 3279begin 3280 3281 -- Extrinsic delay buffers 3282 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 3283 generic map( tLH => twdi0_R, tHL => twdi0_F) 3284 port map( Input => i0, Output => connect(0)); 3285 3286 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 3287 generic map( tLH => twdi1_R, tHL => twdi1_F) 3288 port map( Input => i1, Output => connect(1)); 3289 3290 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 3291 generic map( tLH => twdi2_R, tHL => twdi2_F) 3292 port map( Input => i2, Output => connect(2)); 3293 3294 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 3295 generic map( tLH => twdi3_R, tHL => twdi3_F) 3296 port map( Input => i3, Output => connect(3)); 3297 3298 -- Intrinsic delay buffers 3299 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 3300 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 3301 port map( Input => connect(0), Output => prop_nq(0)); 3302 3303 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 3304 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 3305 port map( Input => connect(1), Output => prop_nq(1)); 3306 3307 U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 3308 generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) 3309 port map( Input => connect(2), Output => prop_nq(2)); 3310 3311 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 3312 generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) 3313 port map( Input => connect(3), Output => prop_nq(3)); 3314 3315 -- Netlist 3316 U9 : NAND2MAC 3317 port map( I0 => n1, I1 => n2, Y => nq); 3318 3319 U10 : OR2MAC 3320 port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n2); 3321 3322 U11 : OR2MAC 3323 port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); 3324 3325 3326end FTSM; 3327 3328configuration CFG_nao2o22_x1_FTSM of nao2o22_x1 is 3329 for FTSM 3330 end for; 3331end CFG_nao2o22_x1_FTSM; 3332 3333 3334----- CELL nao2o22_x4 ----- 3335library IEEE; 3336use IEEE.STD_LOGIC_1164.all; 3337library SYNOPSYS; 3338use SYNOPSYS.attributes.REAL_NAME; 3339 3340-- entity declaration -- 3341entity nao2o22_x4 is 3342 generic( 3343 Timing_mesg: Boolean := True; 3344 Timing_xgen: Boolean := False; 3345 tpdi0_nq_R : Time := 0.734 ns; 3346 tpdi0_nq_F : Time := 0.644 ns; 3347 tpdi1_nq_R : Time := 0.666 ns; 3348 tpdi1_nq_F : Time := 0.717 ns; 3349 tpdi2_nq_R : Time := 0.664 ns; 3350 tpdi2_nq_F : Time := 0.721 ns; 3351 tpdi3_nq_R : Time := 0.607 ns; 3352 tpdi3_nq_F : Time := 0.807 ns; 3353 twdi0_R : Time := 0.000 ns; 3354 twdi0_F : Time := 0.000 ns; 3355 twdi1_R : Time := 0.000 ns; 3356 twdi1_F : Time := 0.000 ns; 3357 twdi2_R : Time := 0.000 ns; 3358 twdi2_F : Time := 0.000 ns; 3359 twdi3_R : Time := 0.000 ns; 3360 twdi3_F : Time := 0.000 ns); 3361 3362 port( 3363 i0 : in STD_LOGIC; 3364 i1 : in STD_LOGIC; 3365 i2 : in STD_LOGIC; 3366 i3 : in STD_LOGIC; 3367 nq : out STD_LOGIC); 3368end nao2o22_x4; 3369 3370-- architecture body -- 3371library IEEE_ASIC; 3372use IEEE.STD_LOGIC_MISC.all; 3373use SYNOPSYS.attributes.backplane; 3374use SYNOPSYS.attributes.PRIVATE; 3375use SYNOPSYS.attributes.ASIC_CELL; 3376use SYNOPSYS.attributes.PROPAGATE_VALUE; 3377 3378architecture FTSM of nao2o22_x4 is 3379 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 3380 attribute PRIVATE of FTSM : architecture is TRUE; 3381 attribute ASIC_CELL of FTSM : architecture is TRUE; 3382 3383 -- Backannotation attributes 3384 attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; 3385 attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; 3386 attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; 3387 attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; 3388 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; 3389 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; 3390 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; 3391 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; 3392 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 3393 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 3394 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 3395 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 3396 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 3397 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 3398 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 3399 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 3400 3401 signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 3402 signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 3403 signal n1, n2 : STD_LOGIC; 3404 3405 component NAND2MAC 3406 generic( 3407 tpdY_R : Time := 0 ns; 3408 tpdY_F : Time := 0 ns; 3409 strn : STRENGTH := strn_X01); 3410 port( 3411 I0 : in STD_LOGIC; 3412 I1 : in STD_LOGIC; 3413 Y : out STD_LOGIC); 3414 end component; 3415 3416 component OR2MAC 3417 generic( 3418 tpdY_R : Time := 0 ns; 3419 tpdY_F : Time := 0 ns; 3420 strn : STRENGTH := strn_X01); 3421 port( 3422 I0 : in STD_LOGIC; 3423 I1 : in STD_LOGIC; 3424 Y : out STD_LOGIC); 3425 end component; 3426 3427begin 3428 3429 -- Extrinsic delay buffers 3430 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 3431 generic map( tLH => twdi0_R, tHL => twdi0_F) 3432 port map( Input => i0, Output => connect(0)); 3433 3434 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 3435 generic map( tLH => twdi1_R, tHL => twdi1_F) 3436 port map( Input => i1, Output => connect(1)); 3437 3438 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 3439 generic map( tLH => twdi2_R, tHL => twdi2_F) 3440 port map( Input => i2, Output => connect(2)); 3441 3442 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 3443 generic map( tLH => twdi3_R, tHL => twdi3_F) 3444 port map( Input => i3, Output => connect(3)); 3445 3446 -- Intrinsic delay buffers 3447 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 3448 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 3449 port map( Input => connect(0), Output => prop_nq(0)); 3450 3451 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 3452 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 3453 port map( Input => connect(1), Output => prop_nq(1)); 3454 3455 U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 3456 generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) 3457 port map( Input => connect(2), Output => prop_nq(2)); 3458 3459 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 3460 generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) 3461 port map( Input => connect(3), Output => prop_nq(3)); 3462 3463 -- Netlist 3464 U9 : NAND2MAC 3465 port map( I0 => n1, I1 => n2, Y => nq); 3466 3467 U10 : OR2MAC 3468 port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n2); 3469 3470 U11 : OR2MAC 3471 port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); 3472 3473 3474end FTSM; 3475 3476configuration CFG_nao2o22_x4_FTSM of nao2o22_x4 is 3477 for FTSM 3478 end for; 3479end CFG_nao2o22_x4_FTSM; 3480 3481 3482----- CELL nao22_x1 ----- 3483library IEEE; 3484use IEEE.STD_LOGIC_1164.all; 3485library SYNOPSYS; 3486use SYNOPSYS.attributes.REAL_NAME; 3487 3488-- entity declaration -- 3489entity nao22_x1 is 3490 generic( 3491 Timing_mesg: Boolean := True; 3492 Timing_xgen: Boolean := False; 3493 tpdi0_nq_R : Time := 0.294 ns; 3494 tpdi0_nq_F : Time := 0.226 ns; 3495 tpdi1_nq_R : Time := 0.218 ns; 3496 tpdi1_nq_F : Time := 0.287 ns; 3497 tpdi2_nq_R : Time := 0.165 ns; 3498 tpdi2_nq_F : Time := 0.238 ns; 3499 twdi0_R : Time := 0.000 ns; 3500 twdi0_F : Time := 0.000 ns; 3501 twdi1_R : Time := 0.000 ns; 3502 twdi1_F : Time := 0.000 ns; 3503 twdi2_R : Time := 0.000 ns; 3504 twdi2_F : Time := 0.000 ns); 3505 3506 port( 3507 i0 : in STD_LOGIC; 3508 i1 : in STD_LOGIC; 3509 i2 : in STD_LOGIC; 3510 nq : out STD_LOGIC); 3511end nao22_x1; 3512 3513-- architecture body -- 3514library IEEE_ASIC; 3515use IEEE.STD_LOGIC_MISC.all; 3516use SYNOPSYS.attributes.backplane; 3517use SYNOPSYS.attributes.PRIVATE; 3518use SYNOPSYS.attributes.ASIC_CELL; 3519use SYNOPSYS.attributes.PROPAGATE_VALUE; 3520 3521architecture FTSM of nao22_x1 is 3522 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 3523 attribute PRIVATE of FTSM : architecture is TRUE; 3524 attribute ASIC_CELL of FTSM : architecture is TRUE; 3525 3526 -- Backannotation attributes 3527 attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; 3528 attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; 3529 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; 3530 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; 3531 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; 3532 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; 3533 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 3534 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 3535 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 3536 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 3537 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 3538 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 3539 3540 signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 3541 signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 3542 signal n1 : STD_LOGIC; 3543 3544 component NAND2MAC 3545 generic( 3546 tpdY_R : Time := 0 ns; 3547 tpdY_F : Time := 0 ns; 3548 strn : STRENGTH := strn_X01); 3549 port( 3550 I0 : in STD_LOGIC; 3551 I1 : in STD_LOGIC; 3552 Y : out STD_LOGIC); 3553 end component; 3554 3555 component OR2MAC 3556 generic( 3557 tpdY_R : Time := 0 ns; 3558 tpdY_F : Time := 0 ns; 3559 strn : STRENGTH := strn_X01); 3560 port( 3561 I0 : in STD_LOGIC; 3562 I1 : in STD_LOGIC; 3563 Y : out STD_LOGIC); 3564 end component; 3565 3566begin 3567 3568 -- Extrinsic delay buffers 3569 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 3570 generic map( tLH => twdi0_R, tHL => twdi0_F) 3571 port map( Input => i0, Output => connect(0)); 3572 3573 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 3574 generic map( tLH => twdi1_R, tHL => twdi1_F) 3575 port map( Input => i1, Output => connect(1)); 3576 3577 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 3578 generic map( tLH => twdi2_R, tHL => twdi2_F) 3579 port map( Input => i2, Output => connect(2)); 3580 3581 -- Intrinsic delay buffers 3582 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 3583 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 3584 port map( Input => connect(0), Output => prop_nq(0)); 3585 3586 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 3587 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 3588 port map( Input => connect(1), Output => prop_nq(1)); 3589 3590 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 3591 generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) 3592 port map( Input => connect(2), Output => prop_nq(2)); 3593 3594 -- Netlist 3595 U7 : NAND2MAC 3596 port map( I0 => prop_nq(2), I1 => n1, Y => nq); 3597 3598 U8 : OR2MAC 3599 port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); 3600 3601 3602end FTSM; 3603 3604configuration CFG_nao22_x1_FTSM of nao22_x1 is 3605 for FTSM 3606 end for; 3607end CFG_nao22_x1_FTSM; 3608 3609 3610----- CELL nao22_x4 ----- 3611library IEEE; 3612use IEEE.STD_LOGIC_1164.all; 3613library SYNOPSYS; 3614use SYNOPSYS.attributes.REAL_NAME; 3615 3616-- entity declaration -- 3617entity nao22_x4 is 3618 generic( 3619 Timing_mesg: Boolean := True; 3620 Timing_xgen: Boolean := False; 3621 tpdi0_nq_R : Time := 0.732 ns; 3622 tpdi0_nq_F : Time := 0.650 ns; 3623 tpdi1_nq_R : Time := 0.664 ns; 3624 tpdi1_nq_F : Time := 0.723 ns; 3625 tpdi2_nq_R : Time := 0.596 ns; 3626 tpdi2_nq_F : Time := 0.636 ns; 3627 twdi0_R : Time := 0.000 ns; 3628 twdi0_F : Time := 0.000 ns; 3629 twdi1_R : Time := 0.000 ns; 3630 twdi1_F : Time := 0.000 ns; 3631 twdi2_R : Time := 0.000 ns; 3632 twdi2_F : Time := 0.000 ns); 3633 3634 port( 3635 i0 : in STD_LOGIC; 3636 i1 : in STD_LOGIC; 3637 i2 : in STD_LOGIC; 3638 nq : out STD_LOGIC); 3639end nao22_x4; 3640 3641-- architecture body -- 3642library IEEE_ASIC; 3643use IEEE.STD_LOGIC_MISC.all; 3644use SYNOPSYS.attributes.backplane; 3645use SYNOPSYS.attributes.PRIVATE; 3646use SYNOPSYS.attributes.ASIC_CELL; 3647use SYNOPSYS.attributes.PROPAGATE_VALUE; 3648 3649architecture FTSM of nao22_x4 is 3650 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 3651 attribute PRIVATE of FTSM : architecture is TRUE; 3652 attribute ASIC_CELL of FTSM : architecture is TRUE; 3653 3654 -- Backannotation attributes 3655 attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; 3656 attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; 3657 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; 3658 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; 3659 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; 3660 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; 3661 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 3662 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 3663 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 3664 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 3665 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 3666 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 3667 3668 signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 3669 signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 3670 signal n1 : STD_LOGIC; 3671 3672 component NAND2MAC 3673 generic( 3674 tpdY_R : Time := 0 ns; 3675 tpdY_F : Time := 0 ns; 3676 strn : STRENGTH := strn_X01); 3677 port( 3678 I0 : in STD_LOGIC; 3679 I1 : in STD_LOGIC; 3680 Y : out STD_LOGIC); 3681 end component; 3682 3683 component OR2MAC 3684 generic( 3685 tpdY_R : Time := 0 ns; 3686 tpdY_F : Time := 0 ns; 3687 strn : STRENGTH := strn_X01); 3688 port( 3689 I0 : in STD_LOGIC; 3690 I1 : in STD_LOGIC; 3691 Y : out STD_LOGIC); 3692 end component; 3693 3694begin 3695 3696 -- Extrinsic delay buffers 3697 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 3698 generic map( tLH => twdi0_R, tHL => twdi0_F) 3699 port map( Input => i0, Output => connect(0)); 3700 3701 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 3702 generic map( tLH => twdi1_R, tHL => twdi1_F) 3703 port map( Input => i1, Output => connect(1)); 3704 3705 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 3706 generic map( tLH => twdi2_R, tHL => twdi2_F) 3707 port map( Input => i2, Output => connect(2)); 3708 3709 -- Intrinsic delay buffers 3710 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 3711 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 3712 port map( Input => connect(0), Output => prop_nq(0)); 3713 3714 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 3715 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 3716 port map( Input => connect(1), Output => prop_nq(1)); 3717 3718 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 3719 generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) 3720 port map( Input => connect(2), Output => prop_nq(2)); 3721 3722 -- Netlist 3723 U7 : NAND2MAC 3724 port map( I0 => prop_nq(2), I1 => n1, Y => nq); 3725 3726 U8 : OR2MAC 3727 port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); 3728 3729 3730end FTSM; 3731 3732configuration CFG_nao22_x4_FTSM of nao22_x4 is 3733 for FTSM 3734 end for; 3735end CFG_nao22_x4_FTSM; 3736 3737 3738----- CELL nmx2_x1 ----- 3739library IEEE; 3740use IEEE.STD_LOGIC_1164.all; 3741library SYNOPSYS; 3742use SYNOPSYS.attributes.REAL_NAME; 3743 3744-- entity declaration -- 3745entity nmx2_x1 is 3746 generic( 3747 Timing_mesg: Boolean := True; 3748 Timing_xgen: Boolean := False; 3749 tpdcmd_nq_R : Time := 0.218 ns; 3750 tpdcmd_nq_F : Time := 0.287 ns; 3751 tpdi0_nq_R : Time := 0.217 ns; 3752 tpdi0_nq_F : Time := 0.256 ns; 3753 tpdi1_nq_R : Time := 0.217 ns; 3754 tpdi1_nq_F : Time := 0.256 ns; 3755 twdcmd_R : Time := 0.000 ns; 3756 twdcmd_F : Time := 0.000 ns; 3757 twdi0_R : Time := 0.000 ns; 3758 twdi0_F : Time := 0.000 ns; 3759 twdi1_R : Time := 0.000 ns; 3760 twdi1_F : Time := 0.000 ns); 3761 3762 port( 3763 cmd : in STD_LOGIC; 3764 i0 : in STD_LOGIC; 3765 i1 : in STD_LOGIC; 3766 nq : out STD_LOGIC); 3767end nmx2_x1; 3768 3769-- architecture body -- 3770library IEEE_ASIC; 3771use IEEE.STD_LOGIC_MISC.all; 3772use SYNOPSYS.attributes.backplane; 3773use SYNOPSYS.attributes.PRIVATE; 3774use SYNOPSYS.attributes.ASIC_CELL; 3775use SYNOPSYS.attributes.PROPAGATE_VALUE; 3776 3777architecture FTSM of nmx2_x1 is 3778 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 3779 attribute PRIVATE of FTSM : architecture is TRUE; 3780 attribute ASIC_CELL of FTSM : architecture is TRUE; 3781 3782 -- Backannotation attributes 3783 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; 3784 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; 3785 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; 3786 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; 3787 attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is "U4/tLH"; 3788 attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is "U4/tHL"; 3789 attribute PROPAGATE_VALUE of twdi1_F: constant is "U3/tHL"; 3790 attribute PROPAGATE_VALUE of twdi1_R: constant is "U3/tLH"; 3791 attribute PROPAGATE_VALUE of twdi0_F: constant is "U2/tHL"; 3792 attribute PROPAGATE_VALUE of twdi0_R: constant is "U2/tLH"; 3793 attribute PROPAGATE_VALUE of twdcmd_F: constant is "U1/tHL"; 3794 attribute PROPAGATE_VALUE of twdcmd_R: constant is "U1/tLH"; 3795 3796 signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 3797 signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 3798 signal n1 : STD_LOGIC; 3799 3800 component MUX2MAC 3801 generic( 3802 tpdY_R : Time := 0 ns; 3803 tpdY_F : Time := 0 ns; 3804 strn : STRENGTH := strn_X01); 3805 port( 3806 I0 : in STD_LOGIC; 3807 I1 : in STD_LOGIC; 3808 S0 : in STD_LOGIC; 3809 Y : out STD_LOGIC); 3810 end component; 3811 3812 component INVMAC 3813 generic( 3814 tpdY_R : Time := 0 ns; 3815 tpdY_F : Time := 0 ns; 3816 strn : STRENGTH := strn_X01); 3817 port( 3818 I0 : in STD_LOGIC; 3819 Y : out STD_LOGIC); 3820 end component; 3821 3822begin 3823 3824 -- Extrinsic delay buffers 3825 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 3826 generic map( tLH => twdcmd_R, tHL => twdcmd_F) 3827 port map( Input => cmd, Output => connect(0)); 3828 3829 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 3830 generic map( tLH => twdi0_R, tHL => twdi0_F) 3831 port map( Input => i0, Output => connect(1)); 3832 3833 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 3834 generic map( tLH => twdi1_R, tHL => twdi1_F) 3835 port map( Input => i1, Output => connect(2)); 3836 3837 -- Intrinsic delay buffers 3838 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 3839 generic map( tLH => tpdcmd_nq_F, tHL => tpdcmd_nq_R) 3840 port map( Input => connect(0), Output => prop_nq(0)); 3841 3842 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 3843 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 3844 port map( Input => connect(1), Output => prop_nq(1)); 3845 3846 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 3847 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 3848 port map( Input => connect(2), Output => prop_nq(2)); 3849 3850 -- Netlist 3851 U7 : MUX2MAC 3852 port map( I0 => prop_nq(1), I1 => prop_nq(2), S0 => prop_nq(0), Y => 3853 n1); 3854 3855 U8 : INVMAC 3856 port map( I0 => n1, Y => nq); 3857 3858 3859end FTSM; 3860 3861configuration CFG_nmx2_x1_FTSM of nmx2_x1 is 3862 for FTSM 3863 end for; 3864end CFG_nmx2_x1_FTSM; 3865 3866 3867----- CELL nmx2_x4 ----- 3868library IEEE; 3869use IEEE.STD_LOGIC_1164.all; 3870library SYNOPSYS; 3871use SYNOPSYS.attributes.REAL_NAME; 3872 3873-- entity declaration -- 3874entity nmx2_x4 is 3875 generic( 3876 Timing_mesg: Boolean := True; 3877 Timing_xgen: Boolean := False; 3878 tpdcmd_nq_R : Time := 0.632 ns; 3879 tpdcmd_nq_F : Time := 0.708 ns; 3880 tpdi0_nq_R : Time := 0.610 ns; 3881 tpdi0_nq_F : Time := 0.653 ns; 3882 tpdi1_nq_R : Time := 0.610 ns; 3883 tpdi1_nq_F : Time := 0.653 ns; 3884 twdcmd_R : Time := 0.000 ns; 3885 twdcmd_F : Time := 0.000 ns; 3886 twdi0_R : Time := 0.000 ns; 3887 twdi0_F : Time := 0.000 ns; 3888 twdi1_R : Time := 0.000 ns; 3889 twdi1_F : Time := 0.000 ns); 3890 3891 port( 3892 cmd : in STD_LOGIC; 3893 i0 : in STD_LOGIC; 3894 i1 : in STD_LOGIC; 3895 nq : out STD_LOGIC); 3896end nmx2_x4; 3897 3898-- architecture body -- 3899library IEEE_ASIC; 3900use IEEE.STD_LOGIC_MISC.all; 3901use SYNOPSYS.attributes.backplane; 3902use SYNOPSYS.attributes.PRIVATE; 3903use SYNOPSYS.attributes.ASIC_CELL; 3904use SYNOPSYS.attributes.PROPAGATE_VALUE; 3905 3906architecture FTSM of nmx2_x4 is 3907 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 3908 attribute PRIVATE of FTSM : architecture is TRUE; 3909 attribute ASIC_CELL of FTSM : architecture is TRUE; 3910 3911 -- Backannotation attributes 3912 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; 3913 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; 3914 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; 3915 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; 3916 attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is "U4/tLH"; 3917 attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is "U4/tHL"; 3918 attribute PROPAGATE_VALUE of twdi1_F: constant is "U3/tHL"; 3919 attribute PROPAGATE_VALUE of twdi1_R: constant is "U3/tLH"; 3920 attribute PROPAGATE_VALUE of twdi0_F: constant is "U2/tHL"; 3921 attribute PROPAGATE_VALUE of twdi0_R: constant is "U2/tLH"; 3922 attribute PROPAGATE_VALUE of twdcmd_F: constant is "U1/tHL"; 3923 attribute PROPAGATE_VALUE of twdcmd_R: constant is "U1/tLH"; 3924 3925 signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 3926 signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 3927 signal n1 : STD_LOGIC; 3928 3929 component MUX2MAC 3930 generic( 3931 tpdY_R : Time := 0 ns; 3932 tpdY_F : Time := 0 ns; 3933 strn : STRENGTH := strn_X01); 3934 port( 3935 I0 : in STD_LOGIC; 3936 I1 : in STD_LOGIC; 3937 S0 : in STD_LOGIC; 3938 Y : out STD_LOGIC); 3939 end component; 3940 3941 component INVMAC 3942 generic( 3943 tpdY_R : Time := 0 ns; 3944 tpdY_F : Time := 0 ns; 3945 strn : STRENGTH := strn_X01); 3946 port( 3947 I0 : in STD_LOGIC; 3948 Y : out STD_LOGIC); 3949 end component; 3950 3951begin 3952 3953 -- Extrinsic delay buffers 3954 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 3955 generic map( tLH => twdcmd_R, tHL => twdcmd_F) 3956 port map( Input => cmd, Output => connect(0)); 3957 3958 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 3959 generic map( tLH => twdi0_R, tHL => twdi0_F) 3960 port map( Input => i0, Output => connect(1)); 3961 3962 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 3963 generic map( tLH => twdi1_R, tHL => twdi1_F) 3964 port map( Input => i1, Output => connect(2)); 3965 3966 -- Intrinsic delay buffers 3967 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 3968 generic map( tLH => tpdcmd_nq_F, tHL => tpdcmd_nq_R) 3969 port map( Input => connect(0), Output => prop_nq(0)); 3970 3971 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 3972 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 3973 port map( Input => connect(1), Output => prop_nq(1)); 3974 3975 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 3976 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 3977 port map( Input => connect(2), Output => prop_nq(2)); 3978 3979 -- Netlist 3980 U7 : MUX2MAC 3981 port map( I0 => prop_nq(1), I1 => prop_nq(2), S0 => prop_nq(0), Y => 3982 n1); 3983 3984 U8 : INVMAC 3985 port map( I0 => n1, Y => nq); 3986 3987 3988end FTSM; 3989 3990configuration CFG_nmx2_x4_FTSM of nmx2_x4 is 3991 for FTSM 3992 end for; 3993end CFG_nmx2_x4_FTSM; 3994 3995 3996----- CELL nmx3_x1 ----- 3997library IEEE; 3998use IEEE.STD_LOGIC_1164.all; 3999library SYNOPSYS; 4000use SYNOPSYS.attributes.REAL_NAME; 4001 4002-- entity declaration -- 4003entity nmx3_x1 is 4004 generic( 4005 Timing_mesg: Boolean := True; 4006 Timing_xgen: Boolean := False; 4007 tpdcmd0_nq_R : Time := 0.356 ns; 4008 tpdcmd0_nq_F : Time := 0.495 ns; 4009 tpdcmd1_nq_R : Time := 0.414 ns; 4010 tpdcmd1_nq_F : Time := 0.566 ns; 4011 tpdi0_nq_R : Time := 0.315 ns; 4012 tpdi0_nq_F : Time := 0.441 ns; 4013 tpdi1_nq_R : Time := 0.429 ns; 4014 tpdi1_nq_F : Time := 0.582 ns; 4015 tpdi2_nq_R : Time := 0.429 ns; 4016 tpdi2_nq_F : Time := 0.582 ns; 4017 twdcmd0_R : Time := 0.000 ns; 4018 twdcmd0_F : Time := 0.000 ns; 4019 twdcmd1_R : Time := 0.000 ns; 4020 twdcmd1_F : Time := 0.000 ns; 4021 twdi0_R : Time := 0.000 ns; 4022 twdi0_F : Time := 0.000 ns; 4023 twdi1_R : Time := 0.000 ns; 4024 twdi1_F : Time := 0.000 ns; 4025 twdi2_R : Time := 0.000 ns; 4026 twdi2_F : Time := 0.000 ns); 4027 4028 port( 4029 cmd0 : in STD_LOGIC; 4030 cmd1 : in STD_LOGIC; 4031 i0 : in STD_LOGIC; 4032 i1 : in STD_LOGIC; 4033 i2 : in STD_LOGIC; 4034 nq : out STD_LOGIC); 4035end nmx3_x1; 4036 4037-- architecture body -- 4038library IEEE_ASIC; 4039use IEEE.STD_LOGIC_MISC.all; 4040use SYNOPSYS.attributes.backplane; 4041use SYNOPSYS.attributes.PRIVATE; 4042use SYNOPSYS.attributes.ASIC_CELL; 4043use SYNOPSYS.attributes.PROPAGATE_VALUE; 4044 4045architecture FTSM of nmx3_x1 is 4046 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 4047 attribute PRIVATE of FTSM : architecture is TRUE; 4048 attribute ASIC_CELL of FTSM : architecture is TRUE; 4049 4050 -- Backannotation attributes 4051 attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U10/tLH"; 4052 attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U10/tHL"; 4053 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U9/tLH"; 4054 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U9/tHL"; 4055 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U8/tLH"; 4056 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U8/tHL"; 4057 attribute PROPAGATE_VALUE of tpdcmd1_nq_F: constant is "U7/tLH"; 4058 attribute PROPAGATE_VALUE of tpdcmd1_nq_R: constant is "U7/tHL"; 4059 attribute PROPAGATE_VALUE of tpdcmd0_nq_F: constant is "U6/tLH"; 4060 attribute PROPAGATE_VALUE of tpdcmd0_nq_R: constant is "U6/tHL"; 4061 attribute PROPAGATE_VALUE of twdi2_F: constant is "U5/tHL"; 4062 attribute PROPAGATE_VALUE of twdi2_R: constant is "U5/tLH"; 4063 attribute PROPAGATE_VALUE of twdi1_F: constant is "U4/tHL"; 4064 attribute PROPAGATE_VALUE of twdi1_R: constant is "U4/tLH"; 4065 attribute PROPAGATE_VALUE of twdi0_F: constant is "U3/tHL"; 4066 attribute PROPAGATE_VALUE of twdi0_R: constant is "U3/tLH"; 4067 attribute PROPAGATE_VALUE of twdcmd1_F: constant is "U2/tHL"; 4068 attribute PROPAGATE_VALUE of twdcmd1_R: constant is "U2/tLH"; 4069 attribute PROPAGATE_VALUE of twdcmd0_F: constant is "U1/tHL"; 4070 attribute PROPAGATE_VALUE of twdcmd0_R: constant is "U1/tLH"; 4071 4072 signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); 4073 signal prop_nq : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); 4074 signal n1, n2 : STD_LOGIC; 4075 4076 component MUX2MAC 4077 generic( 4078 tpdY_R : Time := 0 ns; 4079 tpdY_F : Time := 0 ns; 4080 strn : STRENGTH := strn_X01); 4081 port( 4082 I0 : in STD_LOGIC; 4083 I1 : in STD_LOGIC; 4084 S0 : in STD_LOGIC; 4085 Y : out STD_LOGIC); 4086 end component; 4087 4088 component INVMAC 4089 generic( 4090 tpdY_R : Time := 0 ns; 4091 tpdY_F : Time := 0 ns; 4092 strn : STRENGTH := strn_X01); 4093 port( 4094 I0 : in STD_LOGIC; 4095 Y : out STD_LOGIC); 4096 end component; 4097 4098begin 4099 4100 -- Extrinsic delay buffers 4101 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 4102 generic map( tLH => twdcmd0_R, tHL => twdcmd0_F) 4103 port map( Input => cmd0, Output => connect(0)); 4104 4105 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 4106 generic map( tLH => twdcmd1_R, tHL => twdcmd1_F) 4107 port map( Input => cmd1, Output => connect(1)); 4108 4109 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 4110 generic map( tLH => twdi0_R, tHL => twdi0_F) 4111 port map( Input => i0, Output => connect(2)); 4112 4113 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 4114 generic map( tLH => twdi1_R, tHL => twdi1_F) 4115 port map( Input => i1, Output => connect(3)); 4116 4117 U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 4118 generic map( tLH => twdi2_R, tHL => twdi2_F) 4119 port map( Input => i2, Output => connect(4)); 4120 4121 -- Intrinsic delay buffers 4122 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 4123 generic map( tLH => tpdcmd0_nq_F, tHL => tpdcmd0_nq_R) 4124 port map( Input => connect(0), Output => prop_nq(0)); 4125 4126 U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 4127 generic map( tLH => tpdcmd1_nq_F, tHL => tpdcmd1_nq_R) 4128 port map( Input => connect(1), Output => prop_nq(1)); 4129 4130 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 4131 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 4132 port map( Input => connect(2), Output => prop_nq(2)); 4133 4134 U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 4135 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 4136 port map( Input => connect(3), Output => prop_nq(3)); 4137 4138 U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 4139 generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) 4140 port map( Input => connect(4), Output => prop_nq(4)); 4141 4142 -- Netlist 4143 U11 : MUX2MAC 4144 port map( I0 => prop_nq(4), I1 => prop_nq(3), S0 => prop_nq(1), Y => 4145 n1); 4146 4147 U12 : MUX2MAC 4148 port map( I0 => prop_nq(2), I1 => n1, S0 => prop_nq(0), Y => n2); 4149 4150 U13 : INVMAC 4151 port map( I0 => n2, Y => nq); 4152 4153 4154end FTSM; 4155 4156configuration CFG_nmx3_x1_FTSM of nmx3_x1 is 4157 for FTSM 4158 end for; 4159end CFG_nmx3_x1_FTSM; 4160 4161 4162----- CELL nmx3_x4 ----- 4163library IEEE; 4164use IEEE.STD_LOGIC_1164.all; 4165library SYNOPSYS; 4166use SYNOPSYS.attributes.REAL_NAME; 4167 4168-- entity declaration -- 4169entity nmx3_x4 is 4170 generic( 4171 Timing_mesg: Boolean := True; 4172 Timing_xgen: Boolean := False; 4173 tpdcmd0_nq_R : Time := 0.790 ns; 4174 tpdcmd0_nq_F : Time := 0.936 ns; 4175 tpdcmd1_nq_R : Time := 0.866 ns; 4176 tpdcmd1_nq_F : Time := 1.048 ns; 4177 tpdi0_nq_R : Time := 0.748 ns; 4178 tpdi0_nq_F : Time := 0.900 ns; 4179 tpdi1_nq_R : Time := 0.869 ns; 4180 tpdi1_nq_F : Time := 1.053 ns; 4181 tpdi2_nq_R : Time := 0.869 ns; 4182 tpdi2_nq_F : Time := 1.053 ns; 4183 twdcmd0_R : Time := 0.000 ns; 4184 twdcmd0_F : Time := 0.000 ns; 4185 twdcmd1_R : Time := 0.000 ns; 4186 twdcmd1_F : Time := 0.000 ns; 4187 twdi0_R : Time := 0.000 ns; 4188 twdi0_F : Time := 0.000 ns; 4189 twdi1_R : Time := 0.000 ns; 4190 twdi1_F : Time := 0.000 ns; 4191 twdi2_R : Time := 0.000 ns; 4192 twdi2_F : Time := 0.000 ns); 4193 4194 port( 4195 cmd0 : in STD_LOGIC; 4196 cmd1 : in STD_LOGIC; 4197 i0 : in STD_LOGIC; 4198 i1 : in STD_LOGIC; 4199 i2 : in STD_LOGIC; 4200 nq : out STD_LOGIC); 4201end nmx3_x4; 4202 4203-- architecture body -- 4204library IEEE_ASIC; 4205use IEEE.STD_LOGIC_MISC.all; 4206use SYNOPSYS.attributes.backplane; 4207use SYNOPSYS.attributes.PRIVATE; 4208use SYNOPSYS.attributes.ASIC_CELL; 4209use SYNOPSYS.attributes.PROPAGATE_VALUE; 4210 4211architecture FTSM of nmx3_x4 is 4212 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 4213 attribute PRIVATE of FTSM : architecture is TRUE; 4214 attribute ASIC_CELL of FTSM : architecture is TRUE; 4215 4216 -- Backannotation attributes 4217 attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U10/tLH"; 4218 attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U10/tHL"; 4219 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U9/tLH"; 4220 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U9/tHL"; 4221 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U8/tLH"; 4222 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U8/tHL"; 4223 attribute PROPAGATE_VALUE of tpdcmd1_nq_F: constant is "U7/tLH"; 4224 attribute PROPAGATE_VALUE of tpdcmd1_nq_R: constant is "U7/tHL"; 4225 attribute PROPAGATE_VALUE of tpdcmd0_nq_F: constant is "U6/tLH"; 4226 attribute PROPAGATE_VALUE of tpdcmd0_nq_R: constant is "U6/tHL"; 4227 attribute PROPAGATE_VALUE of twdi2_F: constant is "U5/tHL"; 4228 attribute PROPAGATE_VALUE of twdi2_R: constant is "U5/tLH"; 4229 attribute PROPAGATE_VALUE of twdi1_F: constant is "U4/tHL"; 4230 attribute PROPAGATE_VALUE of twdi1_R: constant is "U4/tLH"; 4231 attribute PROPAGATE_VALUE of twdi0_F: constant is "U3/tHL"; 4232 attribute PROPAGATE_VALUE of twdi0_R: constant is "U3/tLH"; 4233 attribute PROPAGATE_VALUE of twdcmd1_F: constant is "U2/tHL"; 4234 attribute PROPAGATE_VALUE of twdcmd1_R: constant is "U2/tLH"; 4235 attribute PROPAGATE_VALUE of twdcmd0_F: constant is "U1/tHL"; 4236 attribute PROPAGATE_VALUE of twdcmd0_R: constant is "U1/tLH"; 4237 4238 signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); 4239 signal prop_nq : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); 4240 signal n1, n2 : STD_LOGIC; 4241 4242 component MUX2MAC 4243 generic( 4244 tpdY_R : Time := 0 ns; 4245 tpdY_F : Time := 0 ns; 4246 strn : STRENGTH := strn_X01); 4247 port( 4248 I0 : in STD_LOGIC; 4249 I1 : in STD_LOGIC; 4250 S0 : in STD_LOGIC; 4251 Y : out STD_LOGIC); 4252 end component; 4253 4254 component INVMAC 4255 generic( 4256 tpdY_R : Time := 0 ns; 4257 tpdY_F : Time := 0 ns; 4258 strn : STRENGTH := strn_X01); 4259 port( 4260 I0 : in STD_LOGIC; 4261 Y : out STD_LOGIC); 4262 end component; 4263 4264begin 4265 4266 -- Extrinsic delay buffers 4267 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 4268 generic map( tLH => twdcmd0_R, tHL => twdcmd0_F) 4269 port map( Input => cmd0, Output => connect(0)); 4270 4271 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 4272 generic map( tLH => twdcmd1_R, tHL => twdcmd1_F) 4273 port map( Input => cmd1, Output => connect(1)); 4274 4275 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 4276 generic map( tLH => twdi0_R, tHL => twdi0_F) 4277 port map( Input => i0, Output => connect(2)); 4278 4279 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 4280 generic map( tLH => twdi1_R, tHL => twdi1_F) 4281 port map( Input => i1, Output => connect(3)); 4282 4283 U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 4284 generic map( tLH => twdi2_R, tHL => twdi2_F) 4285 port map( Input => i2, Output => connect(4)); 4286 4287 -- Intrinsic delay buffers 4288 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 4289 generic map( tLH => tpdcmd0_nq_F, tHL => tpdcmd0_nq_R) 4290 port map( Input => connect(0), Output => prop_nq(0)); 4291 4292 U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 4293 generic map( tLH => tpdcmd1_nq_F, tHL => tpdcmd1_nq_R) 4294 port map( Input => connect(1), Output => prop_nq(1)); 4295 4296 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 4297 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 4298 port map( Input => connect(2), Output => prop_nq(2)); 4299 4300 U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 4301 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 4302 port map( Input => connect(3), Output => prop_nq(3)); 4303 4304 U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 4305 generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) 4306 port map( Input => connect(4), Output => prop_nq(4)); 4307 4308 -- Netlist 4309 U11 : MUX2MAC 4310 port map( I0 => prop_nq(4), I1 => prop_nq(3), S0 => prop_nq(1), Y => 4311 n1); 4312 4313 U12 : MUX2MAC 4314 port map( I0 => prop_nq(2), I1 => n1, S0 => prop_nq(0), Y => n2); 4315 4316 U13 : INVMAC 4317 port map( I0 => n2, Y => nq); 4318 4319 4320end FTSM; 4321 4322configuration CFG_nmx3_x4_FTSM of nmx3_x4 is 4323 for FTSM 4324 end for; 4325end CFG_nmx3_x4_FTSM; 4326 4327 4328----- CELL no2_x1 ----- 4329library IEEE; 4330use IEEE.STD_LOGIC_1164.all; 4331library SYNOPSYS; 4332use SYNOPSYS.attributes.REAL_NAME; 4333 4334-- entity declaration -- 4335entity no2_x1 is 4336 generic( 4337 Timing_mesg: Boolean := True; 4338 Timing_xgen: Boolean := False; 4339 tpdi0_nq_R : Time := 0.298 ns; 4340 tpdi0_nq_F : Time := 0.121 ns; 4341 tpdi1_nq_R : Time := 0.193 ns; 4342 tpdi1_nq_F : Time := 0.161 ns; 4343 twdi0_R : Time := 0.000 ns; 4344 twdi0_F : Time := 0.000 ns; 4345 twdi1_R : Time := 0.000 ns; 4346 twdi1_F : Time := 0.000 ns); 4347 4348 port( 4349 i0 : in STD_LOGIC; 4350 i1 : in STD_LOGIC; 4351 nq : out STD_LOGIC); 4352end no2_x1; 4353 4354-- architecture body -- 4355library IEEE_ASIC; 4356use IEEE.STD_LOGIC_MISC.all; 4357use SYNOPSYS.attributes.backplane; 4358use SYNOPSYS.attributes.PRIVATE; 4359use SYNOPSYS.attributes.ASIC_CELL; 4360use SYNOPSYS.attributes.PROPAGATE_VALUE; 4361 4362architecture FTSM of no2_x1 is 4363 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 4364 attribute PRIVATE of FTSM : architecture is TRUE; 4365 attribute ASIC_CELL of FTSM : architecture is TRUE; 4366 4367 -- Backannotation attributes 4368 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U4/tLH"; 4369 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U4/tHL"; 4370 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U3/tLH"; 4371 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U3/tHL"; 4372 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 4373 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 4374 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 4375 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 4376 4377 signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 4378 signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 4379 4380 component NOR2MAC 4381 generic( 4382 tpdY_R : Time := 0 ns; 4383 tpdY_F : Time := 0 ns; 4384 strn : STRENGTH := strn_X01); 4385 port( 4386 I0 : in STD_LOGIC; 4387 I1 : in STD_LOGIC; 4388 Y : out STD_LOGIC); 4389 end component; 4390 4391begin 4392 4393 -- Extrinsic delay buffers 4394 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 4395 generic map( tLH => twdi0_R, tHL => twdi0_F) 4396 port map( Input => i0, Output => connect(0)); 4397 4398 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 4399 generic map( tLH => twdi1_R, tHL => twdi1_F) 4400 port map( Input => i1, Output => connect(1)); 4401 4402 -- Intrinsic delay buffers 4403 U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 4404 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 4405 port map( Input => connect(0), Output => prop_nq(0)); 4406 4407 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 4408 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 4409 port map( Input => connect(1), Output => prop_nq(1)); 4410 4411 -- Netlist 4412 U5 : NOR2MAC 4413 port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => nq); 4414 4415 4416end FTSM; 4417 4418configuration CFG_no2_x1_FTSM of no2_x1 is 4419 for FTSM 4420 end for; 4421end CFG_no2_x1_FTSM; 4422 4423 4424----- CELL no2_x4 ----- 4425library IEEE; 4426use IEEE.STD_LOGIC_1164.all; 4427library SYNOPSYS; 4428use SYNOPSYS.attributes.REAL_NAME; 4429 4430-- entity declaration -- 4431entity no2_x4 is 4432 generic( 4433 Timing_mesg: Boolean := True; 4434 Timing_xgen: Boolean := False; 4435 tpdi0_nq_R : Time := 0.618 ns; 4436 tpdi0_nq_F : Time := 0.447 ns; 4437 tpdi1_nq_R : Time := 0.522 ns; 4438 tpdi1_nq_F : Time := 0.504 ns; 4439 twdi0_R : Time := 0.000 ns; 4440 twdi0_F : Time := 0.000 ns; 4441 twdi1_R : Time := 0.000 ns; 4442 twdi1_F : Time := 0.000 ns); 4443 4444 port( 4445 i0 : in STD_LOGIC; 4446 i1 : in STD_LOGIC; 4447 nq : out STD_LOGIC); 4448end no2_x4; 4449 4450-- architecture body -- 4451library IEEE_ASIC; 4452use IEEE.STD_LOGIC_MISC.all; 4453use SYNOPSYS.attributes.backplane; 4454use SYNOPSYS.attributes.PRIVATE; 4455use SYNOPSYS.attributes.ASIC_CELL; 4456use SYNOPSYS.attributes.PROPAGATE_VALUE; 4457 4458architecture FTSM of no2_x4 is 4459 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 4460 attribute PRIVATE of FTSM : architecture is TRUE; 4461 attribute ASIC_CELL of FTSM : architecture is TRUE; 4462 4463 -- Backannotation attributes 4464 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U4/tLH"; 4465 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U4/tHL"; 4466 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U3/tLH"; 4467 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U3/tHL"; 4468 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 4469 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 4470 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 4471 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 4472 4473 signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 4474 signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 4475 4476 component NOR2MAC 4477 generic( 4478 tpdY_R : Time := 0 ns; 4479 tpdY_F : Time := 0 ns; 4480 strn : STRENGTH := strn_X01); 4481 port( 4482 I0 : in STD_LOGIC; 4483 I1 : in STD_LOGIC; 4484 Y : out STD_LOGIC); 4485 end component; 4486 4487begin 4488 4489 -- Extrinsic delay buffers 4490 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 4491 generic map( tLH => twdi0_R, tHL => twdi0_F) 4492 port map( Input => i0, Output => connect(0)); 4493 4494 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 4495 generic map( tLH => twdi1_R, tHL => twdi1_F) 4496 port map( Input => i1, Output => connect(1)); 4497 4498 -- Intrinsic delay buffers 4499 U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 4500 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 4501 port map( Input => connect(0), Output => prop_nq(0)); 4502 4503 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 4504 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 4505 port map( Input => connect(1), Output => prop_nq(1)); 4506 4507 -- Netlist 4508 U5 : NOR2MAC 4509 port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => nq); 4510 4511 4512end FTSM; 4513 4514configuration CFG_no2_x4_FTSM of no2_x4 is 4515 for FTSM 4516 end for; 4517end CFG_no2_x4_FTSM; 4518 4519 4520----- CELL no3_x1 ----- 4521library IEEE; 4522use IEEE.STD_LOGIC_1164.all; 4523library SYNOPSYS; 4524use SYNOPSYS.attributes.REAL_NAME; 4525 4526-- entity declaration -- 4527entity no3_x1 is 4528 generic( 4529 Timing_mesg: Boolean := True; 4530 Timing_xgen: Boolean := False; 4531 tpdi0_nq_R : Time := 0.318 ns; 4532 tpdi0_nq_F : Time := 0.246 ns; 4533 tpdi1_nq_R : Time := 0.215 ns; 4534 tpdi1_nq_F : Time := 0.243 ns; 4535 tpdi2_nq_R : Time := 0.407 ns; 4536 tpdi2_nq_F : Time := 0.192 ns; 4537 twdi0_R : Time := 0.000 ns; 4538 twdi0_F : Time := 0.000 ns; 4539 twdi1_R : Time := 0.000 ns; 4540 twdi1_F : Time := 0.000 ns; 4541 twdi2_R : Time := 0.000 ns; 4542 twdi2_F : Time := 0.000 ns); 4543 4544 port( 4545 i0 : in STD_LOGIC; 4546 i1 : in STD_LOGIC; 4547 i2 : in STD_LOGIC; 4548 nq : out STD_LOGIC); 4549end no3_x1; 4550 4551-- architecture body -- 4552library IEEE_ASIC; 4553use IEEE.STD_LOGIC_MISC.all; 4554use SYNOPSYS.attributes.backplane; 4555use SYNOPSYS.attributes.PRIVATE; 4556use SYNOPSYS.attributes.ASIC_CELL; 4557use SYNOPSYS.attributes.PROPAGATE_VALUE; 4558 4559architecture FTSM of no3_x1 is 4560 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 4561 attribute PRIVATE of FTSM : architecture is TRUE; 4562 attribute ASIC_CELL of FTSM : architecture is TRUE; 4563 4564 -- Backannotation attributes 4565 attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; 4566 attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; 4567 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; 4568 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; 4569 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; 4570 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; 4571 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 4572 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 4573 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 4574 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 4575 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 4576 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 4577 4578 signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 4579 signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 4580 4581 component NOR3MAC 4582 generic( 4583 tpdY_R : Time := 0 ns; 4584 tpdY_F : Time := 0 ns; 4585 strn : STRENGTH := strn_X01); 4586 port( 4587 I0 : in STD_LOGIC; 4588 I1 : in STD_LOGIC; 4589 I2 : in STD_LOGIC; 4590 Y : out STD_LOGIC); 4591 end component; 4592 4593begin 4594 4595 -- Extrinsic delay buffers 4596 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 4597 generic map( tLH => twdi0_R, tHL => twdi0_F) 4598 port map( Input => i0, Output => connect(0)); 4599 4600 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 4601 generic map( tLH => twdi1_R, tHL => twdi1_F) 4602 port map( Input => i1, Output => connect(1)); 4603 4604 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 4605 generic map( tLH => twdi2_R, tHL => twdi2_F) 4606 port map( Input => i2, Output => connect(2)); 4607 4608 -- Intrinsic delay buffers 4609 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 4610 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 4611 port map( Input => connect(0), Output => prop_nq(0)); 4612 4613 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 4614 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 4615 port map( Input => connect(1), Output => prop_nq(1)); 4616 4617 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 4618 generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) 4619 port map( Input => connect(2), Output => prop_nq(2)); 4620 4621 -- Netlist 4622 U7 : NOR3MAC 4623 port map( I0 => prop_nq(2), I1 => prop_nq(0), I2 => prop_nq(1), Y => 4624 nq); 4625 4626 4627end FTSM; 4628 4629configuration CFG_no3_x1_FTSM of no3_x1 is 4630 for FTSM 4631 end for; 4632end CFG_no3_x1_FTSM; 4633 4634 4635----- CELL no3_x4 ----- 4636library IEEE; 4637use IEEE.STD_LOGIC_1164.all; 4638library SYNOPSYS; 4639use SYNOPSYS.attributes.REAL_NAME; 4640 4641-- entity declaration -- 4642entity no3_x4 is 4643 generic( 4644 Timing_mesg: Boolean := True; 4645 Timing_xgen: Boolean := False; 4646 tpdi0_nq_R : Time := 0.722 ns; 4647 tpdi0_nq_F : Time := 0.561 ns; 4648 tpdi1_nq_R : Time := 0.638 ns; 4649 tpdi1_nq_F : Time := 0.623 ns; 4650 tpdi2_nq_R : Time := 0.545 ns; 4651 tpdi2_nq_F : Time := 0.640 ns; 4652 twdi0_R : Time := 0.000 ns; 4653 twdi0_F : Time := 0.000 ns; 4654 twdi1_R : Time := 0.000 ns; 4655 twdi1_F : Time := 0.000 ns; 4656 twdi2_R : Time := 0.000 ns; 4657 twdi2_F : Time := 0.000 ns); 4658 4659 port( 4660 i0 : in STD_LOGIC; 4661 i1 : in STD_LOGIC; 4662 i2 : in STD_LOGIC; 4663 nq : out STD_LOGIC); 4664end no3_x4; 4665 4666-- architecture body -- 4667library IEEE_ASIC; 4668use IEEE.STD_LOGIC_MISC.all; 4669use SYNOPSYS.attributes.backplane; 4670use SYNOPSYS.attributes.PRIVATE; 4671use SYNOPSYS.attributes.ASIC_CELL; 4672use SYNOPSYS.attributes.PROPAGATE_VALUE; 4673 4674architecture FTSM of no3_x4 is 4675 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 4676 attribute PRIVATE of FTSM : architecture is TRUE; 4677 attribute ASIC_CELL of FTSM : architecture is TRUE; 4678 4679 -- Backannotation attributes 4680 attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; 4681 attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; 4682 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; 4683 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; 4684 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; 4685 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; 4686 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 4687 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 4688 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 4689 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 4690 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 4691 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 4692 4693 signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 4694 signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 4695 4696 component NOR3MAC 4697 generic( 4698 tpdY_R : Time := 0 ns; 4699 tpdY_F : Time := 0 ns; 4700 strn : STRENGTH := strn_X01); 4701 port( 4702 I0 : in STD_LOGIC; 4703 I1 : in STD_LOGIC; 4704 I2 : in STD_LOGIC; 4705 Y : out STD_LOGIC); 4706 end component; 4707 4708begin 4709 4710 -- Extrinsic delay buffers 4711 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 4712 generic map( tLH => twdi0_R, tHL => twdi0_F) 4713 port map( Input => i0, Output => connect(0)); 4714 4715 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 4716 generic map( tLH => twdi1_R, tHL => twdi1_F) 4717 port map( Input => i1, Output => connect(1)); 4718 4719 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 4720 generic map( tLH => twdi2_R, tHL => twdi2_F) 4721 port map( Input => i2, Output => connect(2)); 4722 4723 -- Intrinsic delay buffers 4724 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 4725 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 4726 port map( Input => connect(0), Output => prop_nq(0)); 4727 4728 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 4729 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 4730 port map( Input => connect(1), Output => prop_nq(1)); 4731 4732 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 4733 generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) 4734 port map( Input => connect(2), Output => prop_nq(2)); 4735 4736 -- Netlist 4737 U7 : NOR3MAC 4738 port map( I0 => prop_nq(2), I1 => prop_nq(0), I2 => prop_nq(1), Y => 4739 nq); 4740 4741 4742end FTSM; 4743 4744configuration CFG_no3_x4_FTSM of no3_x4 is 4745 for FTSM 4746 end for; 4747end CFG_no3_x4_FTSM; 4748 4749 4750----- CELL no4_x1 ----- 4751library IEEE; 4752use IEEE.STD_LOGIC_1164.all; 4753library SYNOPSYS; 4754use SYNOPSYS.attributes.REAL_NAME; 4755 4756-- entity declaration -- 4757entity no4_x1 is 4758 generic( 4759 Timing_mesg: Boolean := True; 4760 Timing_xgen: Boolean := False; 4761 tpdi0_nq_R : Time := 0.330 ns; 4762 tpdi0_nq_F : Time := 0.340 ns; 4763 tpdi1_nq_R : Time := 0.230 ns; 4764 tpdi1_nq_F : Time := 0.320 ns; 4765 tpdi2_nq_R : Time := 0.419 ns; 4766 tpdi2_nq_F : Time := 0.333 ns; 4767 tpdi3_nq_R : Time := 0.499 ns; 4768 tpdi3_nq_F : Time := 0.271 ns; 4769 twdi0_R : Time := 0.000 ns; 4770 twdi0_F : Time := 0.000 ns; 4771 twdi1_R : Time := 0.000 ns; 4772 twdi1_F : Time := 0.000 ns; 4773 twdi2_R : Time := 0.000 ns; 4774 twdi2_F : Time := 0.000 ns; 4775 twdi3_R : Time := 0.000 ns; 4776 twdi3_F : Time := 0.000 ns); 4777 4778 port( 4779 i0 : in STD_LOGIC; 4780 i1 : in STD_LOGIC; 4781 i2 : in STD_LOGIC; 4782 i3 : in STD_LOGIC; 4783 nq : out STD_LOGIC); 4784end no4_x1; 4785 4786-- architecture body -- 4787library IEEE_ASIC; 4788use IEEE.STD_LOGIC_MISC.all; 4789use SYNOPSYS.attributes.backplane; 4790use SYNOPSYS.attributes.PRIVATE; 4791use SYNOPSYS.attributes.ASIC_CELL; 4792use SYNOPSYS.attributes.PROPAGATE_VALUE; 4793 4794architecture FTSM of no4_x1 is 4795 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 4796 attribute PRIVATE of FTSM : architecture is TRUE; 4797 attribute ASIC_CELL of FTSM : architecture is TRUE; 4798 4799 -- Backannotation attributes 4800 attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; 4801 attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; 4802 attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; 4803 attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; 4804 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; 4805 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; 4806 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; 4807 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; 4808 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 4809 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 4810 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 4811 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 4812 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 4813 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 4814 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 4815 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 4816 4817 signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 4818 signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 4819 4820 component NOR4MAC 4821 generic( 4822 tpdY_R : Time := 0 ns; 4823 tpdY_F : Time := 0 ns; 4824 strn : STRENGTH := strn_X01); 4825 port( 4826 I0 : in STD_LOGIC; 4827 I1 : in STD_LOGIC; 4828 I2 : in STD_LOGIC; 4829 I3 : in STD_LOGIC; 4830 Y : out STD_LOGIC); 4831 end component; 4832 4833begin 4834 4835 -- Extrinsic delay buffers 4836 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 4837 generic map( tLH => twdi0_R, tHL => twdi0_F) 4838 port map( Input => i0, Output => connect(0)); 4839 4840 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 4841 generic map( tLH => twdi1_R, tHL => twdi1_F) 4842 port map( Input => i1, Output => connect(1)); 4843 4844 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 4845 generic map( tLH => twdi2_R, tHL => twdi2_F) 4846 port map( Input => i2, Output => connect(2)); 4847 4848 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 4849 generic map( tLH => twdi3_R, tHL => twdi3_F) 4850 port map( Input => i3, Output => connect(3)); 4851 4852 -- Intrinsic delay buffers 4853 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 4854 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 4855 port map( Input => connect(0), Output => prop_nq(0)); 4856 4857 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 4858 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 4859 port map( Input => connect(1), Output => prop_nq(1)); 4860 4861 U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 4862 generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) 4863 port map( Input => connect(2), Output => prop_nq(2)); 4864 4865 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 4866 generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) 4867 port map( Input => connect(3), Output => prop_nq(3)); 4868 4869 -- Netlist 4870 U9 : NOR4MAC 4871 port map( I0 => prop_nq(0), I1 => prop_nq(1), I2 => prop_nq(2), I3 => 4872 prop_nq(3), Y => nq); 4873 4874 4875end FTSM; 4876 4877configuration CFG_no4_x1_FTSM of no4_x1 is 4878 for FTSM 4879 end for; 4880end CFG_no4_x1_FTSM; 4881 4882 4883----- CELL no4_x4 ----- 4884library IEEE; 4885use IEEE.STD_LOGIC_1164.all; 4886library SYNOPSYS; 4887use SYNOPSYS.attributes.REAL_NAME; 4888 4889-- entity declaration -- 4890entity no4_x4 is 4891 generic( 4892 Timing_mesg: Boolean := True; 4893 Timing_xgen: Boolean := False; 4894 tpdi0_nq_R : Time := 0.656 ns; 4895 tpdi0_nq_F : Time := 0.777 ns; 4896 tpdi1_nq_R : Time := 0.564 ns; 4897 tpdi1_nq_F : Time := 0.768 ns; 4898 tpdi2_nq_R : Time := 0.739 ns; 4899 tpdi2_nq_F : Time := 0.761 ns; 4900 tpdi3_nq_R : Time := 0.816 ns; 4901 tpdi3_nq_F : Time := 0.693 ns; 4902 twdi0_R : Time := 0.000 ns; 4903 twdi0_F : Time := 0.000 ns; 4904 twdi1_R : Time := 0.000 ns; 4905 twdi1_F : Time := 0.000 ns; 4906 twdi2_R : Time := 0.000 ns; 4907 twdi2_F : Time := 0.000 ns; 4908 twdi3_R : Time := 0.000 ns; 4909 twdi3_F : Time := 0.000 ns); 4910 4911 port( 4912 i0 : in STD_LOGIC; 4913 i1 : in STD_LOGIC; 4914 i2 : in STD_LOGIC; 4915 i3 : in STD_LOGIC; 4916 nq : out STD_LOGIC); 4917end no4_x4; 4918 4919-- architecture body -- 4920library IEEE_ASIC; 4921use IEEE.STD_LOGIC_MISC.all; 4922use SYNOPSYS.attributes.backplane; 4923use SYNOPSYS.attributes.PRIVATE; 4924use SYNOPSYS.attributes.ASIC_CELL; 4925use SYNOPSYS.attributes.PROPAGATE_VALUE; 4926 4927architecture FTSM of no4_x4 is 4928 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 4929 attribute PRIVATE of FTSM : architecture is TRUE; 4930 attribute ASIC_CELL of FTSM : architecture is TRUE; 4931 4932 -- Backannotation attributes 4933 attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; 4934 attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; 4935 attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; 4936 attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; 4937 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; 4938 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; 4939 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; 4940 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; 4941 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 4942 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 4943 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 4944 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 4945 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 4946 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 4947 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 4948 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 4949 4950 signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 4951 signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 4952 4953 component NOR4MAC 4954 generic( 4955 tpdY_R : Time := 0 ns; 4956 tpdY_F : Time := 0 ns; 4957 strn : STRENGTH := strn_X01); 4958 port( 4959 I0 : in STD_LOGIC; 4960 I1 : in STD_LOGIC; 4961 I2 : in STD_LOGIC; 4962 I3 : in STD_LOGIC; 4963 Y : out STD_LOGIC); 4964 end component; 4965 4966begin 4967 4968 -- Extrinsic delay buffers 4969 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 4970 generic map( tLH => twdi0_R, tHL => twdi0_F) 4971 port map( Input => i0, Output => connect(0)); 4972 4973 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 4974 generic map( tLH => twdi1_R, tHL => twdi1_F) 4975 port map( Input => i1, Output => connect(1)); 4976 4977 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 4978 generic map( tLH => twdi2_R, tHL => twdi2_F) 4979 port map( Input => i2, Output => connect(2)); 4980 4981 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 4982 generic map( tLH => twdi3_R, tHL => twdi3_F) 4983 port map( Input => i3, Output => connect(3)); 4984 4985 -- Intrinsic delay buffers 4986 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 4987 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 4988 port map( Input => connect(0), Output => prop_nq(0)); 4989 4990 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 4991 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 4992 port map( Input => connect(1), Output => prop_nq(1)); 4993 4994 U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 4995 generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) 4996 port map( Input => connect(2), Output => prop_nq(2)); 4997 4998 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 4999 generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) 5000 port map( Input => connect(3), Output => prop_nq(3)); 5001 5002 -- Netlist 5003 U9 : NOR4MAC 5004 port map( I0 => prop_nq(0), I1 => prop_nq(1), I2 => prop_nq(2), I3 => 5005 prop_nq(3), Y => nq); 5006 5007 5008end FTSM; 5009 5010configuration CFG_no4_x4_FTSM of no4_x4 is 5011 for FTSM 5012 end for; 5013end CFG_no4_x4_FTSM; 5014 5015 5016----- CELL noa2a2a2a24_x1 ----- 5017library IEEE; 5018use IEEE.STD_LOGIC_1164.all; 5019library SYNOPSYS; 5020use SYNOPSYS.attributes.REAL_NAME; 5021 5022-- entity declaration -- 5023entity noa2a2a2a24_x1 is 5024 generic( 5025 Timing_mesg: Boolean := True; 5026 Timing_xgen: Boolean := False; 5027 tpdi0_nq_R : Time := 0.649 ns; 5028 tpdi0_nq_F : Time := 0.606 ns; 5029 tpdi1_nq_R : Time := 0.775 ns; 5030 tpdi1_nq_F : Time := 0.562 ns; 5031 tpdi2_nq_R : Time := 0.550 ns; 5032 tpdi2_nq_F : Time := 0.662 ns; 5033 tpdi3_nq_R : Time := 0.667 ns; 5034 tpdi3_nq_F : Time := 0.616 ns; 5035 tpdi4_nq_R : Time := 0.419 ns; 5036 tpdi4_nq_F : Time := 0.613 ns; 5037 tpdi5_nq_R : Time := 0.329 ns; 5038 tpdi5_nq_F : Time := 0.662 ns; 5039 tpdi6_nq_R : Time := 0.270 ns; 5040 tpdi6_nq_F : Time := 0.535 ns; 5041 tpdi7_nq_R : Time := 0.200 ns; 5042 tpdi7_nq_F : Time := 0.591 ns; 5043 twdi0_R : Time := 0.000 ns; 5044 twdi0_F : Time := 0.000 ns; 5045 twdi1_R : Time := 0.000 ns; 5046 twdi1_F : Time := 0.000 ns; 5047 twdi2_R : Time := 0.000 ns; 5048 twdi2_F : Time := 0.000 ns; 5049 twdi3_R : Time := 0.000 ns; 5050 twdi3_F : Time := 0.000 ns; 5051 twdi4_R : Time := 0.000 ns; 5052 twdi4_F : Time := 0.000 ns; 5053 twdi5_R : Time := 0.000 ns; 5054 twdi5_F : Time := 0.000 ns; 5055 twdi6_R : Time := 0.000 ns; 5056 twdi6_F : Time := 0.000 ns; 5057 twdi7_R : Time := 0.000 ns; 5058 twdi7_F : Time := 0.000 ns); 5059 5060 port( 5061 i0 : in STD_LOGIC; 5062 i1 : in STD_LOGIC; 5063 i2 : in STD_LOGIC; 5064 i3 : in STD_LOGIC; 5065 i4 : in STD_LOGIC; 5066 i5 : in STD_LOGIC; 5067 i6 : in STD_LOGIC; 5068 i7 : in STD_LOGIC; 5069 nq : out STD_LOGIC); 5070end noa2a2a2a24_x1; 5071 5072-- architecture body -- 5073library IEEE_ASIC; 5074use IEEE.STD_LOGIC_MISC.all; 5075use SYNOPSYS.attributes.backplane; 5076use SYNOPSYS.attributes.PRIVATE; 5077use SYNOPSYS.attributes.ASIC_CELL; 5078use SYNOPSYS.attributes.PROPAGATE_VALUE; 5079 5080architecture FTSM of noa2a2a2a24_x1 is 5081 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 5082 attribute PRIVATE of FTSM : architecture is TRUE; 5083 attribute ASIC_CELL of FTSM : architecture is TRUE; 5084 5085 -- Backannotation attributes 5086 attribute PROPAGATE_VALUE of tpdi7_nq_F: constant is "U16/tLH"; 5087 attribute PROPAGATE_VALUE of tpdi7_nq_R: constant is "U16/tHL"; 5088 attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is "U15/tLH"; 5089 attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is "U15/tHL"; 5090 attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is "U14/tLH"; 5091 attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is "U14/tHL"; 5092 attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U13/tLH"; 5093 attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U13/tHL"; 5094 attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U12/tLH"; 5095 attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U12/tHL"; 5096 attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U11/tLH"; 5097 attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U11/tHL"; 5098 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U10/tLH"; 5099 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U10/tHL"; 5100 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U9/tLH"; 5101 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U9/tHL"; 5102 attribute PROPAGATE_VALUE of twdi7_F: constant is "U8/tHL"; 5103 attribute PROPAGATE_VALUE of twdi7_R: constant is "U8/tLH"; 5104 attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; 5105 attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; 5106 attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; 5107 attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; 5108 attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; 5109 attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; 5110 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 5111 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 5112 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 5113 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 5114 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 5115 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 5116 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 5117 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 5118 5119 signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); 5120 signal prop_nq : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); 5121 signal n1, n2, n3, n4 : STD_LOGIC; 5122 5123 component AND4MAC 5124 generic( 5125 tpdY_R : Time := 0 ns; 5126 tpdY_F : Time := 0 ns; 5127 strn : STRENGTH := strn_X01); 5128 port( 5129 I0 : in STD_LOGIC; 5130 I1 : in STD_LOGIC; 5131 I2 : in STD_LOGIC; 5132 I3 : in STD_LOGIC; 5133 Y : out STD_LOGIC); 5134 end component; 5135 5136 component NAND2MAC 5137 generic( 5138 tpdY_R : Time := 0 ns; 5139 tpdY_F : Time := 0 ns; 5140 strn : STRENGTH := strn_X01); 5141 port( 5142 I0 : in STD_LOGIC; 5143 I1 : in STD_LOGIC; 5144 Y : out STD_LOGIC); 5145 end component; 5146 5147begin 5148 5149 -- Extrinsic delay buffers 5150 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5151 generic map( tLH => twdi0_R, tHL => twdi0_F) 5152 port map( Input => i0, Output => connect(0)); 5153 5154 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5155 generic map( tLH => twdi1_R, tHL => twdi1_F) 5156 port map( Input => i1, Output => connect(1)); 5157 5158 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5159 generic map( tLH => twdi2_R, tHL => twdi2_F) 5160 port map( Input => i2, Output => connect(2)); 5161 5162 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5163 generic map( tLH => twdi3_R, tHL => twdi3_F) 5164 port map( Input => i3, Output => connect(3)); 5165 5166 U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5167 generic map( tLH => twdi4_R, tHL => twdi4_F) 5168 port map( Input => i4, Output => connect(4)); 5169 5170 U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5171 generic map( tLH => twdi5_R, tHL => twdi5_F) 5172 port map( Input => i5, Output => connect(5)); 5173 5174 U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5175 generic map( tLH => twdi6_R, tHL => twdi6_F) 5176 port map( Input => i6, Output => connect(6)); 5177 5178 U8 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5179 generic map( tLH => twdi7_R, tHL => twdi7_F) 5180 port map( Input => i7, Output => connect(7)); 5181 5182 -- Intrinsic delay buffers 5183 U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5184 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 5185 port map( Input => connect(0), Output => prop_nq(0)); 5186 5187 U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5188 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 5189 port map( Input => connect(1), Output => prop_nq(1)); 5190 5191 U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5192 generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) 5193 port map( Input => connect(2), Output => prop_nq(2)); 5194 5195 U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5196 generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) 5197 port map( Input => connect(3), Output => prop_nq(3)); 5198 5199 U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5200 generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) 5201 port map( Input => connect(4), Output => prop_nq(4)); 5202 5203 U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5204 generic map( tLH => tpdi5_nq_F, tHL => tpdi5_nq_R) 5205 port map( Input => connect(5), Output => prop_nq(5)); 5206 5207 U15 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5208 generic map( tLH => tpdi6_nq_F, tHL => tpdi6_nq_R) 5209 port map( Input => connect(6), Output => prop_nq(6)); 5210 5211 U16 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5212 generic map( tLH => tpdi7_nq_F, tHL => tpdi7_nq_R) 5213 port map( Input => connect(7), Output => prop_nq(7)); 5214 5215 -- Netlist 5216 U17 : AND4MAC 5217 port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => nq); 5218 5219 U18 : NAND2MAC 5220 port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n4); 5221 5222 U19 : NAND2MAC 5223 port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n3); 5224 5225 U20 : NAND2MAC 5226 port map( I0 => prop_nq(4), I1 => prop_nq(5), Y => n2); 5227 5228 U21 : NAND2MAC 5229 port map( I0 => prop_nq(6), I1 => prop_nq(7), Y => n1); 5230 5231 5232end FTSM; 5233 5234configuration CFG_noa2a2a2a24_x1_FTSM of noa2a2a2a24_x1 is 5235 for FTSM 5236 end for; 5237end CFG_noa2a2a2a24_x1_FTSM; 5238 5239 5240----- CELL noa2a2a2a24_x4 ----- 5241library IEEE; 5242use IEEE.STD_LOGIC_1164.all; 5243library SYNOPSYS; 5244use SYNOPSYS.attributes.REAL_NAME; 5245 5246-- entity declaration -- 5247entity noa2a2a2a24_x4 is 5248 generic( 5249 Timing_mesg: Boolean := True; 5250 Timing_xgen: Boolean := False; 5251 tpdi0_nq_R : Time := 0.966 ns; 5252 tpdi0_nq_F : Time := 1.049 ns; 5253 tpdi1_nq_R : Time := 1.097 ns; 5254 tpdi1_nq_F : Time := 1.005 ns; 5255 tpdi2_nq_R : Time := 0.867 ns; 5256 tpdi2_nq_F : Time := 1.106 ns; 5257 tpdi3_nq_R : Time := 0.990 ns; 5258 tpdi3_nq_F : Time := 1.061 ns; 5259 tpdi4_nq_R : Time := 0.748 ns; 5260 tpdi4_nq_F : Time := 1.061 ns; 5261 tpdi5_nq_R : Time := 0.649 ns; 5262 tpdi5_nq_F : Time := 1.109 ns; 5263 tpdi6_nq_R : Time := 0.606 ns; 5264 tpdi6_nq_F : Time := 0.999 ns; 5265 tpdi7_nq_R : Time := 0.525 ns; 5266 tpdi7_nq_F : Time := 1.052 ns; 5267 twdi0_R : Time := 0.000 ns; 5268 twdi0_F : Time := 0.000 ns; 5269 twdi1_R : Time := 0.000 ns; 5270 twdi1_F : Time := 0.000 ns; 5271 twdi2_R : Time := 0.000 ns; 5272 twdi2_F : Time := 0.000 ns; 5273 twdi3_R : Time := 0.000 ns; 5274 twdi3_F : Time := 0.000 ns; 5275 twdi4_R : Time := 0.000 ns; 5276 twdi4_F : Time := 0.000 ns; 5277 twdi5_R : Time := 0.000 ns; 5278 twdi5_F : Time := 0.000 ns; 5279 twdi6_R : Time := 0.000 ns; 5280 twdi6_F : Time := 0.000 ns; 5281 twdi7_R : Time := 0.000 ns; 5282 twdi7_F : Time := 0.000 ns); 5283 5284 port( 5285 i0 : in STD_LOGIC; 5286 i1 : in STD_LOGIC; 5287 i2 : in STD_LOGIC; 5288 i3 : in STD_LOGIC; 5289 i4 : in STD_LOGIC; 5290 i5 : in STD_LOGIC; 5291 i6 : in STD_LOGIC; 5292 i7 : in STD_LOGIC; 5293 nq : out STD_LOGIC); 5294end noa2a2a2a24_x4; 5295 5296-- architecture body -- 5297library IEEE_ASIC; 5298use IEEE.STD_LOGIC_MISC.all; 5299use SYNOPSYS.attributes.backplane; 5300use SYNOPSYS.attributes.PRIVATE; 5301use SYNOPSYS.attributes.ASIC_CELL; 5302use SYNOPSYS.attributes.PROPAGATE_VALUE; 5303 5304architecture FTSM of noa2a2a2a24_x4 is 5305 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 5306 attribute PRIVATE of FTSM : architecture is TRUE; 5307 attribute ASIC_CELL of FTSM : architecture is TRUE; 5308 5309 -- Backannotation attributes 5310 attribute PROPAGATE_VALUE of tpdi7_nq_F: constant is "U16/tLH"; 5311 attribute PROPAGATE_VALUE of tpdi7_nq_R: constant is "U16/tHL"; 5312 attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is "U15/tLH"; 5313 attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is "U15/tHL"; 5314 attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is "U14/tLH"; 5315 attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is "U14/tHL"; 5316 attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U13/tLH"; 5317 attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U13/tHL"; 5318 attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U12/tLH"; 5319 attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U12/tHL"; 5320 attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U11/tLH"; 5321 attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U11/tHL"; 5322 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U10/tLH"; 5323 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U10/tHL"; 5324 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U9/tLH"; 5325 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U9/tHL"; 5326 attribute PROPAGATE_VALUE of twdi7_F: constant is "U8/tHL"; 5327 attribute PROPAGATE_VALUE of twdi7_R: constant is "U8/tLH"; 5328 attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; 5329 attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; 5330 attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; 5331 attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; 5332 attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; 5333 attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; 5334 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 5335 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 5336 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 5337 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 5338 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 5339 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 5340 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 5341 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 5342 5343 signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); 5344 signal prop_nq : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); 5345 signal n1, n2, n3, n4 : STD_LOGIC; 5346 5347 component AND4MAC 5348 generic( 5349 tpdY_R : Time := 0 ns; 5350 tpdY_F : Time := 0 ns; 5351 strn : STRENGTH := strn_X01); 5352 port( 5353 I0 : in STD_LOGIC; 5354 I1 : in STD_LOGIC; 5355 I2 : in STD_LOGIC; 5356 I3 : in STD_LOGIC; 5357 Y : out STD_LOGIC); 5358 end component; 5359 5360 component NAND2MAC 5361 generic( 5362 tpdY_R : Time := 0 ns; 5363 tpdY_F : Time := 0 ns; 5364 strn : STRENGTH := strn_X01); 5365 port( 5366 I0 : in STD_LOGIC; 5367 I1 : in STD_LOGIC; 5368 Y : out STD_LOGIC); 5369 end component; 5370 5371begin 5372 5373 -- Extrinsic delay buffers 5374 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5375 generic map( tLH => twdi0_R, tHL => twdi0_F) 5376 port map( Input => i0, Output => connect(0)); 5377 5378 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5379 generic map( tLH => twdi1_R, tHL => twdi1_F) 5380 port map( Input => i1, Output => connect(1)); 5381 5382 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5383 generic map( tLH => twdi2_R, tHL => twdi2_F) 5384 port map( Input => i2, Output => connect(2)); 5385 5386 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5387 generic map( tLH => twdi3_R, tHL => twdi3_F) 5388 port map( Input => i3, Output => connect(3)); 5389 5390 U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5391 generic map( tLH => twdi4_R, tHL => twdi4_F) 5392 port map( Input => i4, Output => connect(4)); 5393 5394 U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5395 generic map( tLH => twdi5_R, tHL => twdi5_F) 5396 port map( Input => i5, Output => connect(5)); 5397 5398 U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5399 generic map( tLH => twdi6_R, tHL => twdi6_F) 5400 port map( Input => i6, Output => connect(6)); 5401 5402 U8 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5403 generic map( tLH => twdi7_R, tHL => twdi7_F) 5404 port map( Input => i7, Output => connect(7)); 5405 5406 -- Intrinsic delay buffers 5407 U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5408 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 5409 port map( Input => connect(0), Output => prop_nq(0)); 5410 5411 U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5412 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 5413 port map( Input => connect(1), Output => prop_nq(1)); 5414 5415 U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5416 generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) 5417 port map( Input => connect(2), Output => prop_nq(2)); 5418 5419 U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5420 generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) 5421 port map( Input => connect(3), Output => prop_nq(3)); 5422 5423 U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5424 generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) 5425 port map( Input => connect(4), Output => prop_nq(4)); 5426 5427 U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5428 generic map( tLH => tpdi5_nq_F, tHL => tpdi5_nq_R) 5429 port map( Input => connect(5), Output => prop_nq(5)); 5430 5431 U15 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5432 generic map( tLH => tpdi6_nq_F, tHL => tpdi6_nq_R) 5433 port map( Input => connect(6), Output => prop_nq(6)); 5434 5435 U16 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5436 generic map( tLH => tpdi7_nq_F, tHL => tpdi7_nq_R) 5437 port map( Input => connect(7), Output => prop_nq(7)); 5438 5439 -- Netlist 5440 U17 : AND4MAC 5441 port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => nq); 5442 5443 U18 : NAND2MAC 5444 port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n4); 5445 5446 U19 : NAND2MAC 5447 port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n3); 5448 5449 U20 : NAND2MAC 5450 port map( I0 => prop_nq(4), I1 => prop_nq(5), Y => n2); 5451 5452 U21 : NAND2MAC 5453 port map( I0 => prop_nq(6), I1 => prop_nq(7), Y => n1); 5454 5455 5456end FTSM; 5457 5458configuration CFG_noa2a2a2a24_x4_FTSM of noa2a2a2a24_x4 is 5459 for FTSM 5460 end for; 5461end CFG_noa2a2a2a24_x4_FTSM; 5462 5463 5464----- CELL noa2a2a23_x1 ----- 5465library IEEE; 5466use IEEE.STD_LOGIC_1164.all; 5467library SYNOPSYS; 5468use SYNOPSYS.attributes.REAL_NAME; 5469 5470-- entity declaration -- 5471entity noa2a2a23_x1 is 5472 generic( 5473 Timing_mesg: Boolean := True; 5474 Timing_xgen: Boolean := False; 5475 tpdi0_nq_R : Time := 0.525 ns; 5476 tpdi0_nq_F : Time := 0.425 ns; 5477 tpdi1_nq_R : Time := 0.643 ns; 5478 tpdi1_nq_F : Time := 0.388 ns; 5479 tpdi2_nq_R : Time := 0.307 ns; 5480 tpdi2_nq_F : Time := 0.479 ns; 5481 tpdi3_nq_R : Time := 0.398 ns; 5482 tpdi3_nq_F : Time := 0.438 ns; 5483 tpdi4_nq_R : Time := 0.250 ns; 5484 tpdi4_nq_F : Time := 0.416 ns; 5485 tpdi5_nq_R : Time := 0.178 ns; 5486 tpdi5_nq_F : Time := 0.464 ns; 5487 twdi0_R : Time := 0.000 ns; 5488 twdi0_F : Time := 0.000 ns; 5489 twdi1_R : Time := 0.000 ns; 5490 twdi1_F : Time := 0.000 ns; 5491 twdi2_R : Time := 0.000 ns; 5492 twdi2_F : Time := 0.000 ns; 5493 twdi3_R : Time := 0.000 ns; 5494 twdi3_F : Time := 0.000 ns; 5495 twdi4_R : Time := 0.000 ns; 5496 twdi4_F : Time := 0.000 ns; 5497 twdi5_R : Time := 0.000 ns; 5498 twdi5_F : Time := 0.000 ns); 5499 5500 port( 5501 i0 : in STD_LOGIC; 5502 i1 : in STD_LOGIC; 5503 i2 : in STD_LOGIC; 5504 i3 : in STD_LOGIC; 5505 i4 : in STD_LOGIC; 5506 i5 : in STD_LOGIC; 5507 nq : out STD_LOGIC); 5508end noa2a2a23_x1; 5509 5510-- architecture body -- 5511library IEEE_ASIC; 5512use IEEE.STD_LOGIC_MISC.all; 5513use SYNOPSYS.attributes.backplane; 5514use SYNOPSYS.attributes.PRIVATE; 5515use SYNOPSYS.attributes.ASIC_CELL; 5516use SYNOPSYS.attributes.PROPAGATE_VALUE; 5517 5518architecture FTSM of noa2a2a23_x1 is 5519 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 5520 attribute PRIVATE of FTSM : architecture is TRUE; 5521 attribute ASIC_CELL of FTSM : architecture is TRUE; 5522 5523 -- Backannotation attributes 5524 attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is "U12/tLH"; 5525 attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is "U12/tHL"; 5526 attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U11/tLH"; 5527 attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U11/tHL"; 5528 attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U10/tLH"; 5529 attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U10/tHL"; 5530 attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U9/tLH"; 5531 attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U9/tHL"; 5532 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U8/tLH"; 5533 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U8/tHL"; 5534 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U7/tLH"; 5535 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U7/tHL"; 5536 attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; 5537 attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; 5538 attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; 5539 attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; 5540 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 5541 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 5542 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 5543 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 5544 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 5545 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 5546 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 5547 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 5548 5549 signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); 5550 signal prop_nq : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); 5551 signal n1, n2, n3 : STD_LOGIC; 5552 5553 component AND3MAC 5554 generic( 5555 tpdY_R : Time := 0 ns; 5556 tpdY_F : Time := 0 ns; 5557 strn : STRENGTH := strn_X01); 5558 port( 5559 I0 : in STD_LOGIC; 5560 I1 : in STD_LOGIC; 5561 I2 : in STD_LOGIC; 5562 Y : out STD_LOGIC); 5563 end component; 5564 5565 component NAND2MAC 5566 generic( 5567 tpdY_R : Time := 0 ns; 5568 tpdY_F : Time := 0 ns; 5569 strn : STRENGTH := strn_X01); 5570 port( 5571 I0 : in STD_LOGIC; 5572 I1 : in STD_LOGIC; 5573 Y : out STD_LOGIC); 5574 end component; 5575 5576begin 5577 5578 -- Extrinsic delay buffers 5579 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5580 generic map( tLH => twdi0_R, tHL => twdi0_F) 5581 port map( Input => i0, Output => connect(0)); 5582 5583 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5584 generic map( tLH => twdi1_R, tHL => twdi1_F) 5585 port map( Input => i1, Output => connect(1)); 5586 5587 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5588 generic map( tLH => twdi2_R, tHL => twdi2_F) 5589 port map( Input => i2, Output => connect(2)); 5590 5591 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5592 generic map( tLH => twdi3_R, tHL => twdi3_F) 5593 port map( Input => i3, Output => connect(3)); 5594 5595 U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5596 generic map( tLH => twdi4_R, tHL => twdi4_F) 5597 port map( Input => i4, Output => connect(4)); 5598 5599 U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5600 generic map( tLH => twdi5_R, tHL => twdi5_F) 5601 port map( Input => i5, Output => connect(5)); 5602 5603 -- Intrinsic delay buffers 5604 U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5605 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 5606 port map( Input => connect(0), Output => prop_nq(0)); 5607 5608 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5609 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 5610 port map( Input => connect(1), Output => prop_nq(1)); 5611 5612 U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5613 generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) 5614 port map( Input => connect(2), Output => prop_nq(2)); 5615 5616 U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5617 generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) 5618 port map( Input => connect(3), Output => prop_nq(3)); 5619 5620 U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5621 generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) 5622 port map( Input => connect(4), Output => prop_nq(4)); 5623 5624 U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5625 generic map( tLH => tpdi5_nq_F, tHL => tpdi5_nq_R) 5626 port map( Input => connect(5), Output => prop_nq(5)); 5627 5628 -- Netlist 5629 U13 : AND3MAC 5630 port map( I0 => n1, I1 => n2, I2 => n3, Y => nq); 5631 5632 U14 : NAND2MAC 5633 port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n2); 5634 5635 U15 : NAND2MAC 5636 port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); 5637 5638 U16 : NAND2MAC 5639 port map( I0 => prop_nq(4), I1 => prop_nq(5), Y => n3); 5640 5641 5642end FTSM; 5643 5644configuration CFG_noa2a2a23_x1_FTSM of noa2a2a23_x1 is 5645 for FTSM 5646 end for; 5647end CFG_noa2a2a23_x1_FTSM; 5648 5649 5650----- CELL noa2a2a23_x4 ----- 5651library IEEE; 5652use IEEE.STD_LOGIC_1164.all; 5653library SYNOPSYS; 5654use SYNOPSYS.attributes.REAL_NAME; 5655 5656-- entity declaration -- 5657entity noa2a2a23_x4 is 5658 generic( 5659 Timing_mesg: Boolean := True; 5660 Timing_xgen: Boolean := False; 5661 tpdi0_nq_R : Time := 0.834 ns; 5662 tpdi0_nq_F : Time := 0.814 ns; 5663 tpdi1_nq_R : Time := 0.955 ns; 5664 tpdi1_nq_F : Time := 0.778 ns; 5665 tpdi2_nq_R : Time := 0.620 ns; 5666 tpdi2_nq_F : Time := 0.873 ns; 5667 tpdi3_nq_R : Time := 0.716 ns; 5668 tpdi3_nq_F : Time := 0.833 ns; 5669 tpdi4_nq_R : Time := 0.574 ns; 5670 tpdi4_nq_F : Time := 0.819 ns; 5671 tpdi5_nq_R : Time := 0.496 ns; 5672 tpdi5_nq_F : Time := 0.865 ns; 5673 twdi0_R : Time := 0.000 ns; 5674 twdi0_F : Time := 0.000 ns; 5675 twdi1_R : Time := 0.000 ns; 5676 twdi1_F : Time := 0.000 ns; 5677 twdi2_R : Time := 0.000 ns; 5678 twdi2_F : Time := 0.000 ns; 5679 twdi3_R : Time := 0.000 ns; 5680 twdi3_F : Time := 0.000 ns; 5681 twdi4_R : Time := 0.000 ns; 5682 twdi4_F : Time := 0.000 ns; 5683 twdi5_R : Time := 0.000 ns; 5684 twdi5_F : Time := 0.000 ns); 5685 5686 port( 5687 i0 : in STD_LOGIC; 5688 i1 : in STD_LOGIC; 5689 i2 : in STD_LOGIC; 5690 i3 : in STD_LOGIC; 5691 i4 : in STD_LOGIC; 5692 i5 : in STD_LOGIC; 5693 nq : out STD_LOGIC); 5694end noa2a2a23_x4; 5695 5696-- architecture body -- 5697library IEEE_ASIC; 5698use IEEE.STD_LOGIC_MISC.all; 5699use SYNOPSYS.attributes.backplane; 5700use SYNOPSYS.attributes.PRIVATE; 5701use SYNOPSYS.attributes.ASIC_CELL; 5702use SYNOPSYS.attributes.PROPAGATE_VALUE; 5703 5704architecture FTSM of noa2a2a23_x4 is 5705 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 5706 attribute PRIVATE of FTSM : architecture is TRUE; 5707 attribute ASIC_CELL of FTSM : architecture is TRUE; 5708 5709 -- Backannotation attributes 5710 attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is "U12/tLH"; 5711 attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is "U12/tHL"; 5712 attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U11/tLH"; 5713 attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U11/tHL"; 5714 attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U10/tLH"; 5715 attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U10/tHL"; 5716 attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U9/tLH"; 5717 attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U9/tHL"; 5718 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U8/tLH"; 5719 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U8/tHL"; 5720 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U7/tLH"; 5721 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U7/tHL"; 5722 attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; 5723 attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; 5724 attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; 5725 attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; 5726 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 5727 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 5728 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 5729 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 5730 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 5731 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 5732 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 5733 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 5734 5735 signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); 5736 signal prop_nq : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); 5737 signal n1, n2, n3 : STD_LOGIC; 5738 5739 component AND3MAC 5740 generic( 5741 tpdY_R : Time := 0 ns; 5742 tpdY_F : Time := 0 ns; 5743 strn : STRENGTH := strn_X01); 5744 port( 5745 I0 : in STD_LOGIC; 5746 I1 : in STD_LOGIC; 5747 I2 : in STD_LOGIC; 5748 Y : out STD_LOGIC); 5749 end component; 5750 5751 component NAND2MAC 5752 generic( 5753 tpdY_R : Time := 0 ns; 5754 tpdY_F : Time := 0 ns; 5755 strn : STRENGTH := strn_X01); 5756 port( 5757 I0 : in STD_LOGIC; 5758 I1 : in STD_LOGIC; 5759 Y : out STD_LOGIC); 5760 end component; 5761 5762begin 5763 5764 -- Extrinsic delay buffers 5765 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5766 generic map( tLH => twdi0_R, tHL => twdi0_F) 5767 port map( Input => i0, Output => connect(0)); 5768 5769 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5770 generic map( tLH => twdi1_R, tHL => twdi1_F) 5771 port map( Input => i1, Output => connect(1)); 5772 5773 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5774 generic map( tLH => twdi2_R, tHL => twdi2_F) 5775 port map( Input => i2, Output => connect(2)); 5776 5777 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5778 generic map( tLH => twdi3_R, tHL => twdi3_F) 5779 port map( Input => i3, Output => connect(3)); 5780 5781 U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5782 generic map( tLH => twdi4_R, tHL => twdi4_F) 5783 port map( Input => i4, Output => connect(4)); 5784 5785 U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5786 generic map( tLH => twdi5_R, tHL => twdi5_F) 5787 port map( Input => i5, Output => connect(5)); 5788 5789 -- Intrinsic delay buffers 5790 U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5791 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 5792 port map( Input => connect(0), Output => prop_nq(0)); 5793 5794 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5795 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 5796 port map( Input => connect(1), Output => prop_nq(1)); 5797 5798 U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5799 generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) 5800 port map( Input => connect(2), Output => prop_nq(2)); 5801 5802 U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5803 generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) 5804 port map( Input => connect(3), Output => prop_nq(3)); 5805 5806 U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5807 generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) 5808 port map( Input => connect(4), Output => prop_nq(4)); 5809 5810 U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5811 generic map( tLH => tpdi5_nq_F, tHL => tpdi5_nq_R) 5812 port map( Input => connect(5), Output => prop_nq(5)); 5813 5814 -- Netlist 5815 U13 : AND3MAC 5816 port map( I0 => n1, I1 => n2, I2 => n3, Y => nq); 5817 5818 U14 : NAND2MAC 5819 port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n2); 5820 5821 U15 : NAND2MAC 5822 port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); 5823 5824 U16 : NAND2MAC 5825 port map( I0 => prop_nq(4), I1 => prop_nq(5), Y => n3); 5826 5827 5828end FTSM; 5829 5830configuration CFG_noa2a2a23_x4_FTSM of noa2a2a23_x4 is 5831 for FTSM 5832 end for; 5833end CFG_noa2a2a23_x4_FTSM; 5834 5835 5836----- CELL noa2a22_x1 ----- 5837library IEEE; 5838use IEEE.STD_LOGIC_1164.all; 5839library SYNOPSYS; 5840use SYNOPSYS.attributes.REAL_NAME; 5841 5842-- entity declaration -- 5843entity noa2a22_x1 is 5844 generic( 5845 Timing_mesg: Boolean := True; 5846 Timing_xgen: Boolean := False; 5847 tpdi0_nq_R : Time := 0.151 ns; 5848 tpdi0_nq_F : Time := 0.327 ns; 5849 tpdi1_nq_R : Time := 0.218 ns; 5850 tpdi1_nq_F : Time := 0.287 ns; 5851 tpdi2_nq_R : Time := 0.284 ns; 5852 tpdi2_nq_F : Time := 0.289 ns; 5853 tpdi3_nq_R : Time := 0.372 ns; 5854 tpdi3_nq_F : Time := 0.256 ns; 5855 twdi0_R : Time := 0.000 ns; 5856 twdi0_F : Time := 0.000 ns; 5857 twdi1_R : Time := 0.000 ns; 5858 twdi1_F : Time := 0.000 ns; 5859 twdi2_R : Time := 0.000 ns; 5860 twdi2_F : Time := 0.000 ns; 5861 twdi3_R : Time := 0.000 ns; 5862 twdi3_F : Time := 0.000 ns); 5863 5864 port( 5865 i0 : in STD_LOGIC; 5866 i1 : in STD_LOGIC; 5867 i2 : in STD_LOGIC; 5868 i3 : in STD_LOGIC; 5869 nq : out STD_LOGIC); 5870end noa2a22_x1; 5871 5872-- architecture body -- 5873library IEEE_ASIC; 5874use IEEE.STD_LOGIC_MISC.all; 5875use SYNOPSYS.attributes.backplane; 5876use SYNOPSYS.attributes.PRIVATE; 5877use SYNOPSYS.attributes.ASIC_CELL; 5878use SYNOPSYS.attributes.PROPAGATE_VALUE; 5879 5880architecture FTSM of noa2a22_x1 is 5881 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 5882 attribute PRIVATE of FTSM : architecture is TRUE; 5883 attribute ASIC_CELL of FTSM : architecture is TRUE; 5884 5885 -- Backannotation attributes 5886 attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; 5887 attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; 5888 attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; 5889 attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; 5890 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; 5891 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; 5892 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; 5893 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; 5894 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 5895 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 5896 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 5897 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 5898 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 5899 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 5900 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 5901 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 5902 5903 signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 5904 signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 5905 signal n1, n2 : STD_LOGIC; 5906 5907 component AND2MAC 5908 generic( 5909 tpdY_R : Time := 0 ns; 5910 tpdY_F : Time := 0 ns; 5911 strn : STRENGTH := strn_X01); 5912 port( 5913 I0 : in STD_LOGIC; 5914 I1 : in STD_LOGIC; 5915 Y : out STD_LOGIC); 5916 end component; 5917 5918 component NAND2MAC 5919 generic( 5920 tpdY_R : Time := 0 ns; 5921 tpdY_F : Time := 0 ns; 5922 strn : STRENGTH := strn_X01); 5923 port( 5924 I0 : in STD_LOGIC; 5925 I1 : in STD_LOGIC; 5926 Y : out STD_LOGIC); 5927 end component; 5928 5929begin 5930 5931 -- Extrinsic delay buffers 5932 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5933 generic map( tLH => twdi0_R, tHL => twdi0_F) 5934 port map( Input => i0, Output => connect(0)); 5935 5936 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5937 generic map( tLH => twdi1_R, tHL => twdi1_F) 5938 port map( Input => i1, Output => connect(1)); 5939 5940 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5941 generic map( tLH => twdi2_R, tHL => twdi2_F) 5942 port map( Input => i2, Output => connect(2)); 5943 5944 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 5945 generic map( tLH => twdi3_R, tHL => twdi3_F) 5946 port map( Input => i3, Output => connect(3)); 5947 5948 -- Intrinsic delay buffers 5949 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5950 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 5951 port map( Input => connect(0), Output => prop_nq(0)); 5952 5953 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5954 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 5955 port map( Input => connect(1), Output => prop_nq(1)); 5956 5957 U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5958 generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) 5959 port map( Input => connect(2), Output => prop_nq(2)); 5960 5961 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 5962 generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) 5963 port map( Input => connect(3), Output => prop_nq(3)); 5964 5965 -- Netlist 5966 U9 : AND2MAC 5967 port map( I0 => n1, I1 => n2, Y => nq); 5968 5969 U10 : NAND2MAC 5970 port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n2); 5971 5972 U11 : NAND2MAC 5973 port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); 5974 5975 5976end FTSM; 5977 5978configuration CFG_noa2a22_x1_FTSM of noa2a22_x1 is 5979 for FTSM 5980 end for; 5981end CFG_noa2a22_x1_FTSM; 5982 5983 5984----- CELL noa2a22_x4 ----- 5985library IEEE; 5986use IEEE.STD_LOGIC_1164.all; 5987library SYNOPSYS; 5988use SYNOPSYS.attributes.REAL_NAME; 5989 5990-- entity declaration -- 5991entity noa2a22_x4 is 5992 generic( 5993 Timing_mesg: Boolean := True; 5994 Timing_xgen: Boolean := False; 5995 tpdi0_nq_R : Time := 0.562 ns; 5996 tpdi0_nq_F : Time := 0.745 ns; 5997 tpdi1_nq_R : Time := 0.646 ns; 5998 tpdi1_nq_F : Time := 0.714 ns; 5999 tpdi2_nq_R : Time := 0.701 ns; 6000 tpdi2_nq_F : Time := 0.703 ns; 6001 tpdi3_nq_R : Time := 0.805 ns; 6002 tpdi3_nq_F : Time := 0.677 ns; 6003 twdi0_R : Time := 0.000 ns; 6004 twdi0_F : Time := 0.000 ns; 6005 twdi1_R : Time := 0.000 ns; 6006 twdi1_F : Time := 0.000 ns; 6007 twdi2_R : Time := 0.000 ns; 6008 twdi2_F : Time := 0.000 ns; 6009 twdi3_R : Time := 0.000 ns; 6010 twdi3_F : Time := 0.000 ns); 6011 6012 port( 6013 i0 : in STD_LOGIC; 6014 i1 : in STD_LOGIC; 6015 i2 : in STD_LOGIC; 6016 i3 : in STD_LOGIC; 6017 nq : out STD_LOGIC); 6018end noa2a22_x4; 6019 6020-- architecture body -- 6021library IEEE_ASIC; 6022use IEEE.STD_LOGIC_MISC.all; 6023use SYNOPSYS.attributes.backplane; 6024use SYNOPSYS.attributes.PRIVATE; 6025use SYNOPSYS.attributes.ASIC_CELL; 6026use SYNOPSYS.attributes.PROPAGATE_VALUE; 6027 6028architecture FTSM of noa2a22_x4 is 6029 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 6030 attribute PRIVATE of FTSM : architecture is TRUE; 6031 attribute ASIC_CELL of FTSM : architecture is TRUE; 6032 6033 -- Backannotation attributes 6034 attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; 6035 attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; 6036 attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; 6037 attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; 6038 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; 6039 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; 6040 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; 6041 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; 6042 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 6043 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 6044 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 6045 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 6046 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 6047 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 6048 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 6049 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 6050 6051 signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 6052 signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 6053 signal n1, n2 : STD_LOGIC; 6054 6055 component AND2MAC 6056 generic( 6057 tpdY_R : Time := 0 ns; 6058 tpdY_F : Time := 0 ns; 6059 strn : STRENGTH := strn_X01); 6060 port( 6061 I0 : in STD_LOGIC; 6062 I1 : in STD_LOGIC; 6063 Y : out STD_LOGIC); 6064 end component; 6065 6066 component NAND2MAC 6067 generic( 6068 tpdY_R : Time := 0 ns; 6069 tpdY_F : Time := 0 ns; 6070 strn : STRENGTH := strn_X01); 6071 port( 6072 I0 : in STD_LOGIC; 6073 I1 : in STD_LOGIC; 6074 Y : out STD_LOGIC); 6075 end component; 6076 6077begin 6078 6079 -- Extrinsic delay buffers 6080 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 6081 generic map( tLH => twdi0_R, tHL => twdi0_F) 6082 port map( Input => i0, Output => connect(0)); 6083 6084 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 6085 generic map( tLH => twdi1_R, tHL => twdi1_F) 6086 port map( Input => i1, Output => connect(1)); 6087 6088 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 6089 generic map( tLH => twdi2_R, tHL => twdi2_F) 6090 port map( Input => i2, Output => connect(2)); 6091 6092 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 6093 generic map( tLH => twdi3_R, tHL => twdi3_F) 6094 port map( Input => i3, Output => connect(3)); 6095 6096 -- Intrinsic delay buffers 6097 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 6098 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 6099 port map( Input => connect(0), Output => prop_nq(0)); 6100 6101 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 6102 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 6103 port map( Input => connect(1), Output => prop_nq(1)); 6104 6105 U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 6106 generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) 6107 port map( Input => connect(2), Output => prop_nq(2)); 6108 6109 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 6110 generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) 6111 port map( Input => connect(3), Output => prop_nq(3)); 6112 6113 -- Netlist 6114 U9 : AND2MAC 6115 port map( I0 => n1, I1 => n2, Y => nq); 6116 6117 U10 : NAND2MAC 6118 port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n2); 6119 6120 U11 : NAND2MAC 6121 port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); 6122 6123 6124end FTSM; 6125 6126configuration CFG_noa2a22_x4_FTSM of noa2a22_x4 is 6127 for FTSM 6128 end for; 6129end CFG_noa2a22_x4_FTSM; 6130 6131 6132----- CELL noa2ao222_x1 ----- 6133library IEEE; 6134use IEEE.STD_LOGIC_1164.all; 6135library SYNOPSYS; 6136use SYNOPSYS.attributes.REAL_NAME; 6137 6138-- entity declaration -- 6139entity noa2ao222_x1 is 6140 generic( 6141 Timing_mesg: Boolean := True; 6142 Timing_xgen: Boolean := False; 6143 tpdi0_nq_R : Time := 0.348 ns; 6144 tpdi0_nq_F : Time := 0.422 ns; 6145 tpdi1_nq_R : Time := 0.440 ns; 6146 tpdi1_nq_F : Time := 0.378 ns; 6147 tpdi2_nq_R : Time := 0.186 ns; 6148 tpdi2_nq_F : Time := 0.473 ns; 6149 tpdi3_nq_R : Time := 0.256 ns; 6150 tpdi3_nq_F : Time := 0.459 ns; 6151 tpdi4_nq_R : Time := 0.240 ns; 6152 tpdi4_nq_F : Time := 0.309 ns; 6153 twdi0_R : Time := 0.000 ns; 6154 twdi0_F : Time := 0.000 ns; 6155 twdi1_R : Time := 0.000 ns; 6156 twdi1_F : Time := 0.000 ns; 6157 twdi2_R : Time := 0.000 ns; 6158 twdi2_F : Time := 0.000 ns; 6159 twdi3_R : Time := 0.000 ns; 6160 twdi3_F : Time := 0.000 ns; 6161 twdi4_R : Time := 0.000 ns; 6162 twdi4_F : Time := 0.000 ns); 6163 6164 port( 6165 i0 : in STD_LOGIC; 6166 i1 : in STD_LOGIC; 6167 i2 : in STD_LOGIC; 6168 i3 : in STD_LOGIC; 6169 i4 : in STD_LOGIC; 6170 nq : out STD_LOGIC); 6171end noa2ao222_x1; 6172 6173-- architecture body -- 6174library IEEE_ASIC; 6175use IEEE.STD_LOGIC_MISC.all; 6176use SYNOPSYS.attributes.backplane; 6177use SYNOPSYS.attributes.PRIVATE; 6178use SYNOPSYS.attributes.ASIC_CELL; 6179use SYNOPSYS.attributes.PROPAGATE_VALUE; 6180 6181architecture FTSM of noa2ao222_x1 is 6182 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 6183 attribute PRIVATE of FTSM : architecture is TRUE; 6184 attribute ASIC_CELL of FTSM : architecture is TRUE; 6185 6186 -- Backannotation attributes 6187 attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U10/tLH"; 6188 attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U10/tHL"; 6189 attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U9/tLH"; 6190 attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U9/tHL"; 6191 attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U8/tLH"; 6192 attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U8/tHL"; 6193 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U7/tLH"; 6194 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U7/tHL"; 6195 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U6/tLH"; 6196 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U6/tHL"; 6197 attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; 6198 attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; 6199 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 6200 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 6201 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 6202 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 6203 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 6204 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 6205 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 6206 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 6207 6208 signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); 6209 signal prop_nq : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); 6210 signal n1, n2, n3 : STD_LOGIC; 6211 6212 component AND2MAC 6213 generic( 6214 tpdY_R : Time := 0 ns; 6215 tpdY_F : Time := 0 ns; 6216 strn : STRENGTH := strn_X01); 6217 port( 6218 I0 : in STD_LOGIC; 6219 I1 : in STD_LOGIC; 6220 Y : out STD_LOGIC); 6221 end component; 6222 6223 component OR2MAC 6224 generic( 6225 tpdY_R : Time := 0 ns; 6226 tpdY_F : Time := 0 ns; 6227 strn : STRENGTH := strn_X01); 6228 port( 6229 I0 : in STD_LOGIC; 6230 I1 : in STD_LOGIC; 6231 Y : out STD_LOGIC); 6232 end component; 6233 6234 component NAND2MAC 6235 generic( 6236 tpdY_R : Time := 0 ns; 6237 tpdY_F : Time := 0 ns; 6238 strn : STRENGTH := strn_X01); 6239 port( 6240 I0 : in STD_LOGIC; 6241 I1 : in STD_LOGIC; 6242 Y : out STD_LOGIC); 6243 end component; 6244 6245begin 6246 6247 -- Extrinsic delay buffers 6248 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 6249 generic map( tLH => twdi0_R, tHL => twdi0_F) 6250 port map( Input => i0, Output => connect(0)); 6251 6252 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 6253 generic map( tLH => twdi1_R, tHL => twdi1_F) 6254 port map( Input => i1, Output => connect(1)); 6255 6256 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 6257 generic map( tLH => twdi2_R, tHL => twdi2_F) 6258 port map( Input => i2, Output => connect(2)); 6259 6260 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 6261 generic map( tLH => twdi3_R, tHL => twdi3_F) 6262 port map( Input => i3, Output => connect(3)); 6263 6264 U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 6265 generic map( tLH => twdi4_R, tHL => twdi4_F) 6266 port map( Input => i4, Output => connect(4)); 6267 6268 -- Intrinsic delay buffers 6269 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 6270 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 6271 port map( Input => connect(0), Output => prop_nq(0)); 6272 6273 U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 6274 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 6275 port map( Input => connect(1), Output => prop_nq(1)); 6276 6277 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 6278 generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) 6279 port map( Input => connect(2), Output => prop_nq(2)); 6280 6281 U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 6282 generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) 6283 port map( Input => connect(3), Output => prop_nq(3)); 6284 6285 U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 6286 generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) 6287 port map( Input => connect(4), Output => prop_nq(4)); 6288 6289 -- Netlist 6290 U11 : AND2MAC 6291 port map( I0 => n1, I1 => n2, Y => nq); 6292 6293 U12 : OR2MAC 6294 port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n3); 6295 6296 U13 : NAND2MAC 6297 port map( I0 => prop_nq(4), I1 => n3, Y => n2); 6298 6299 U14 : NAND2MAC 6300 port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); 6301 6302 6303end FTSM; 6304 6305configuration CFG_noa2ao222_x1_FTSM of noa2ao222_x1 is 6306 for FTSM 6307 end for; 6308end CFG_noa2ao222_x1_FTSM; 6309 6310 6311----- CELL noa2ao222_x4 ----- 6312library IEEE; 6313use IEEE.STD_LOGIC_1164.all; 6314library SYNOPSYS; 6315use SYNOPSYS.attributes.REAL_NAME; 6316 6317-- entity declaration -- 6318entity noa2ao222_x4 is 6319 generic( 6320 Timing_mesg: Boolean := True; 6321 Timing_xgen: Boolean := False; 6322 tpdi0_nq_R : Time := 0.684 ns; 6323 tpdi0_nq_F : Time := 0.801 ns; 6324 tpdi1_nq_R : Time := 0.780 ns; 6325 tpdi1_nq_F : Time := 0.758 ns; 6326 tpdi2_nq_R : Time := 0.638 ns; 6327 tpdi2_nq_F : Time := 0.809 ns; 6328 tpdi3_nq_R : Time := 0.732 ns; 6329 tpdi3_nq_F : Time := 0.795 ns; 6330 tpdi4_nq_R : Time := 0.718 ns; 6331 tpdi4_nq_F : Time := 0.664 ns; 6332 twdi0_R : Time := 0.000 ns; 6333 twdi0_F : Time := 0.000 ns; 6334 twdi1_R : Time := 0.000 ns; 6335 twdi1_F : Time := 0.000 ns; 6336 twdi2_R : Time := 0.000 ns; 6337 twdi2_F : Time := 0.000 ns; 6338 twdi3_R : Time := 0.000 ns; 6339 twdi3_F : Time := 0.000 ns; 6340 twdi4_R : Time := 0.000 ns; 6341 twdi4_F : Time := 0.000 ns); 6342 6343 port( 6344 i0 : in STD_LOGIC; 6345 i1 : in STD_LOGIC; 6346 i2 : in STD_LOGIC; 6347 i3 : in STD_LOGIC; 6348 i4 : in STD_LOGIC; 6349 nq : out STD_LOGIC); 6350end noa2ao222_x4; 6351 6352-- architecture body -- 6353library IEEE_ASIC; 6354use IEEE.STD_LOGIC_MISC.all; 6355use SYNOPSYS.attributes.backplane; 6356use SYNOPSYS.attributes.PRIVATE; 6357use SYNOPSYS.attributes.ASIC_CELL; 6358use SYNOPSYS.attributes.PROPAGATE_VALUE; 6359 6360architecture FTSM of noa2ao222_x4 is 6361 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 6362 attribute PRIVATE of FTSM : architecture is TRUE; 6363 attribute ASIC_CELL of FTSM : architecture is TRUE; 6364 6365 -- Backannotation attributes 6366 attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U10/tLH"; 6367 attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U10/tHL"; 6368 attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U9/tLH"; 6369 attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U9/tHL"; 6370 attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U8/tLH"; 6371 attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U8/tHL"; 6372 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U7/tLH"; 6373 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U7/tHL"; 6374 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U6/tLH"; 6375 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U6/tHL"; 6376 attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; 6377 attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; 6378 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 6379 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 6380 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 6381 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 6382 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 6383 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 6384 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 6385 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 6386 6387 signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); 6388 signal prop_nq : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); 6389 signal n1, n2, n3 : STD_LOGIC; 6390 6391 component AND2MAC 6392 generic( 6393 tpdY_R : Time := 0 ns; 6394 tpdY_F : Time := 0 ns; 6395 strn : STRENGTH := strn_X01); 6396 port( 6397 I0 : in STD_LOGIC; 6398 I1 : in STD_LOGIC; 6399 Y : out STD_LOGIC); 6400 end component; 6401 6402 component OR2MAC 6403 generic( 6404 tpdY_R : Time := 0 ns; 6405 tpdY_F : Time := 0 ns; 6406 strn : STRENGTH := strn_X01); 6407 port( 6408 I0 : in STD_LOGIC; 6409 I1 : in STD_LOGIC; 6410 Y : out STD_LOGIC); 6411 end component; 6412 6413 component NAND2MAC 6414 generic( 6415 tpdY_R : Time := 0 ns; 6416 tpdY_F : Time := 0 ns; 6417 strn : STRENGTH := strn_X01); 6418 port( 6419 I0 : in STD_LOGIC; 6420 I1 : in STD_LOGIC; 6421 Y : out STD_LOGIC); 6422 end component; 6423 6424begin 6425 6426 -- Extrinsic delay buffers 6427 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 6428 generic map( tLH => twdi0_R, tHL => twdi0_F) 6429 port map( Input => i0, Output => connect(0)); 6430 6431 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 6432 generic map( tLH => twdi1_R, tHL => twdi1_F) 6433 port map( Input => i1, Output => connect(1)); 6434 6435 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 6436 generic map( tLH => twdi2_R, tHL => twdi2_F) 6437 port map( Input => i2, Output => connect(2)); 6438 6439 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 6440 generic map( tLH => twdi3_R, tHL => twdi3_F) 6441 port map( Input => i3, Output => connect(3)); 6442 6443 U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 6444 generic map( tLH => twdi4_R, tHL => twdi4_F) 6445 port map( Input => i4, Output => connect(4)); 6446 6447 -- Intrinsic delay buffers 6448 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 6449 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 6450 port map( Input => connect(0), Output => prop_nq(0)); 6451 6452 U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 6453 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 6454 port map( Input => connect(1), Output => prop_nq(1)); 6455 6456 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 6457 generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) 6458 port map( Input => connect(2), Output => prop_nq(2)); 6459 6460 U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 6461 generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) 6462 port map( Input => connect(3), Output => prop_nq(3)); 6463 6464 U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 6465 generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) 6466 port map( Input => connect(4), Output => prop_nq(4)); 6467 6468 -- Netlist 6469 U11 : AND2MAC 6470 port map( I0 => n1, I1 => n2, Y => nq); 6471 6472 U12 : OR2MAC 6473 port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n3); 6474 6475 U13 : NAND2MAC 6476 port map( I0 => prop_nq(4), I1 => n3, Y => n2); 6477 6478 U14 : NAND2MAC 6479 port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); 6480 6481 6482end FTSM; 6483 6484configuration CFG_noa2ao222_x4_FTSM of noa2ao222_x4 is 6485 for FTSM 6486 end for; 6487end CFG_noa2ao222_x4_FTSM; 6488 6489 6490----- CELL noa3ao322_x1 ----- 6491library IEEE; 6492use IEEE.STD_LOGIC_1164.all; 6493library SYNOPSYS; 6494use SYNOPSYS.attributes.REAL_NAME; 6495 6496-- entity declaration -- 6497entity noa3ao322_x1 is 6498 generic( 6499 Timing_mesg: Boolean := True; 6500 Timing_xgen: Boolean := False; 6501 tpdi0_nq_R : Time := 0.396 ns; 6502 tpdi0_nq_F : Time := 0.616 ns; 6503 tpdi1_nq_R : Time := 0.486 ns; 6504 tpdi1_nq_F : Time := 0.552 ns; 6505 tpdi2_nq_R : Time := 0.546 ns; 6506 tpdi2_nq_F : Time := 0.488 ns; 6507 tpdi3_nq_R : Time := 0.196 ns; 6508 tpdi3_nq_F : Time := 0.599 ns; 6509 tpdi4_nq_R : Time := 0.264 ns; 6510 tpdi4_nq_F : Time := 0.608 ns; 6511 tpdi5_nq_R : Time := 0.328 ns; 6512 tpdi5_nq_F : Time := 0.581 ns; 6513 tpdi6_nq_R : Time := 0.246 ns; 6514 tpdi6_nq_F : Time := 0.311 ns; 6515 twdi0_R : Time := 0.000 ns; 6516 twdi0_F : Time := 0.000 ns; 6517 twdi1_R : Time := 0.000 ns; 6518 twdi1_F : Time := 0.000 ns; 6519 twdi2_R : Time := 0.000 ns; 6520 twdi2_F : Time := 0.000 ns; 6521 twdi3_R : Time := 0.000 ns; 6522 twdi3_F : Time := 0.000 ns; 6523 twdi4_R : Time := 0.000 ns; 6524 twdi4_F : Time := 0.000 ns; 6525 twdi5_R : Time := 0.000 ns; 6526 twdi5_F : Time := 0.000 ns; 6527 twdi6_R : Time := 0.000 ns; 6528 twdi6_F : Time := 0.000 ns); 6529 6530 port( 6531 i0 : in STD_LOGIC; 6532 i1 : in STD_LOGIC; 6533 i2 : in STD_LOGIC; 6534 i3 : in STD_LOGIC; 6535 i4 : in STD_LOGIC; 6536 i5 : in STD_LOGIC; 6537 i6 : in STD_LOGIC; 6538 nq : out STD_LOGIC); 6539end noa3ao322_x1; 6540 6541-- architecture body -- 6542library IEEE_ASIC; 6543use IEEE.STD_LOGIC_MISC.all; 6544use SYNOPSYS.attributes.backplane; 6545use SYNOPSYS.attributes.PRIVATE; 6546use SYNOPSYS.attributes.ASIC_CELL; 6547use SYNOPSYS.attributes.PROPAGATE_VALUE; 6548 6549architecture FTSM of noa3ao322_x1 is 6550 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 6551 attribute PRIVATE of FTSM : architecture is TRUE; 6552 attribute ASIC_CELL of FTSM : architecture is TRUE; 6553 6554 -- Backannotation attributes 6555 attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is "U14/tLH"; 6556 attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is "U14/tHL"; 6557 attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is "U13/tLH"; 6558 attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is "U13/tHL"; 6559 attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U12/tLH"; 6560 attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U12/tHL"; 6561 attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U11/tLH"; 6562 attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U11/tHL"; 6563 attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U10/tLH"; 6564 attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U10/tHL"; 6565 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U9/tLH"; 6566 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U9/tHL"; 6567 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U8/tLH"; 6568 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U8/tHL"; 6569 attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; 6570 attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; 6571 attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; 6572 attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; 6573 attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; 6574 attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; 6575 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 6576 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 6577 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 6578 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 6579 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 6580 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 6581 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 6582 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 6583 6584 signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); 6585 signal prop_nq : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); 6586 signal n1, n2, n3 : STD_LOGIC; 6587 6588 component AND2MAC 6589 generic( 6590 tpdY_R : Time := 0 ns; 6591 tpdY_F : Time := 0 ns; 6592 strn : STRENGTH := strn_X01); 6593 port( 6594 I0 : in STD_LOGIC; 6595 I1 : in STD_LOGIC; 6596 Y : out STD_LOGIC); 6597 end component; 6598 6599 component NAND3MAC 6600 generic( 6601 tpdY_R : Time := 0 ns; 6602 tpdY_F : Time := 0 ns; 6603 strn : STRENGTH := strn_X01); 6604 port( 6605 I0 : in STD_LOGIC; 6606 I1 : in STD_LOGIC; 6607 I2 : in STD_LOGIC; 6608 Y : out STD_LOGIC); 6609 end component; 6610 6611 component OR3MAC 6612 generic( 6613 tpdY_R : Time := 0 ns; 6614 tpdY_F : Time := 0 ns; 6615 strn : STRENGTH := strn_X01); 6616 port( 6617 I0 : in STD_LOGIC; 6618 I1 : in STD_LOGIC; 6619 I2 : in STD_LOGIC; 6620 Y : out STD_LOGIC); 6621 end component; 6622 6623 component NAND2MAC 6624 generic( 6625 tpdY_R : Time := 0 ns; 6626 tpdY_F : Time := 0 ns; 6627 strn : STRENGTH := strn_X01); 6628 port( 6629 I0 : in STD_LOGIC; 6630 I1 : in STD_LOGIC; 6631 Y : out STD_LOGIC); 6632 end component; 6633 6634begin 6635 6636 -- Extrinsic delay buffers 6637 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 6638 generic map( tLH => twdi0_R, tHL => twdi0_F) 6639 port map( Input => i0, Output => connect(0)); 6640 6641 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 6642 generic map( tLH => twdi1_R, tHL => twdi1_F) 6643 port map( Input => i1, Output => connect(1)); 6644 6645 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 6646 generic map( tLH => twdi2_R, tHL => twdi2_F) 6647 port map( Input => i2, Output => connect(2)); 6648 6649 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 6650 generic map( tLH => twdi3_R, tHL => twdi3_F) 6651 port map( Input => i3, Output => connect(3)); 6652 6653 U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 6654 generic map( tLH => twdi4_R, tHL => twdi4_F) 6655 port map( Input => i4, Output => connect(4)); 6656 6657 U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 6658 generic map( tLH => twdi5_R, tHL => twdi5_F) 6659 port map( Input => i5, Output => connect(5)); 6660 6661 U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 6662 generic map( tLH => twdi6_R, tHL => twdi6_F) 6663 port map( Input => i6, Output => connect(6)); 6664 6665 -- Intrinsic delay buffers 6666 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 6667 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 6668 port map( Input => connect(0), Output => prop_nq(0)); 6669 6670 U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 6671 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 6672 port map( Input => connect(1), Output => prop_nq(1)); 6673 6674 U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 6675 generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) 6676 port map( Input => connect(2), Output => prop_nq(2)); 6677 6678 U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 6679 generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) 6680 port map( Input => connect(3), Output => prop_nq(3)); 6681 6682 U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 6683 generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) 6684 port map( Input => connect(4), Output => prop_nq(4)); 6685 6686 U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 6687 generic map( tLH => tpdi5_nq_F, tHL => tpdi5_nq_R) 6688 port map( Input => connect(5), Output => prop_nq(5)); 6689 6690 U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 6691 generic map( tLH => tpdi6_nq_F, tHL => tpdi6_nq_R) 6692 port map( Input => connect(6), Output => prop_nq(6)); 6693 6694 -- Netlist 6695 U15 : AND2MAC 6696 port map( I0 => n1, I1 => n2, Y => nq); 6697 6698 U16 : NAND3MAC 6699 port map( I0 => prop_nq(1), I1 => prop_nq(2), I2 => prop_nq(0), Y => 6700 n2); 6701 6702 U17 : OR3MAC 6703 port map( I0 => prop_nq(3), I1 => prop_nq(4), I2 => prop_nq(5), Y => 6704 n3); 6705 6706 U18 : NAND2MAC 6707 port map( I0 => prop_nq(6), I1 => n3, Y => n1); 6708 6709 6710end FTSM; 6711 6712configuration CFG_noa3ao322_x1_FTSM of noa3ao322_x1 is 6713 for FTSM 6714 end for; 6715end CFG_noa3ao322_x1_FTSM; 6716 6717 6718----- CELL noa3ao322_x4 ----- 6719library IEEE; 6720use IEEE.STD_LOGIC_1164.all; 6721library SYNOPSYS; 6722use SYNOPSYS.attributes.REAL_NAME; 6723 6724-- entity declaration -- 6725entity noa3ao322_x4 is 6726 generic( 6727 Timing_mesg: Boolean := True; 6728 Timing_xgen: Boolean := False; 6729 tpdi0_nq_R : Time := 0.819 ns; 6730 tpdi0_nq_F : Time := 0.987 ns; 6731 tpdi1_nq_R : Time := 0.914 ns; 6732 tpdi1_nq_F : Time := 0.931 ns; 6733 tpdi2_nq_R : Time := 0.990 ns; 6734 tpdi2_nq_F : Time := 0.874 ns; 6735 tpdi3_nq_R : Time := 0.729 ns; 6736 tpdi3_nq_F : Time := 0.926 ns; 6737 tpdi4_nq_R : Time := 0.821 ns; 6738 tpdi4_nq_F : Time := 0.924 ns; 6739 tpdi5_nq_R : Time := 0.907 ns; 6740 tpdi5_nq_F : Time := 0.900 ns; 6741 tpdi6_nq_R : Time := 0.738 ns; 6742 tpdi6_nq_F : Time := 0.718 ns; 6743 twdi0_R : Time := 0.000 ns; 6744 twdi0_F : Time := 0.000 ns; 6745 twdi1_R : Time := 0.000 ns; 6746 twdi1_F : Time := 0.000 ns; 6747 twdi2_R : Time := 0.000 ns; 6748 twdi2_F : Time := 0.000 ns; 6749 twdi3_R : Time := 0.000 ns; 6750 twdi3_F : Time := 0.000 ns; 6751 twdi4_R : Time := 0.000 ns; 6752 twdi4_F : Time := 0.000 ns; 6753 twdi5_R : Time := 0.000 ns; 6754 twdi5_F : Time := 0.000 ns; 6755 twdi6_R : Time := 0.000 ns; 6756 twdi6_F : Time := 0.000 ns); 6757 6758 port( 6759 i0 : in STD_LOGIC; 6760 i1 : in STD_LOGIC; 6761 i2 : in STD_LOGIC; 6762 i3 : in STD_LOGIC; 6763 i4 : in STD_LOGIC; 6764 i5 : in STD_LOGIC; 6765 i6 : in STD_LOGIC; 6766 nq : out STD_LOGIC); 6767end noa3ao322_x4; 6768 6769-- architecture body -- 6770library IEEE_ASIC; 6771use IEEE.STD_LOGIC_MISC.all; 6772use SYNOPSYS.attributes.backplane; 6773use SYNOPSYS.attributes.PRIVATE; 6774use SYNOPSYS.attributes.ASIC_CELL; 6775use SYNOPSYS.attributes.PROPAGATE_VALUE; 6776 6777architecture FTSM of noa3ao322_x4 is 6778 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 6779 attribute PRIVATE of FTSM : architecture is TRUE; 6780 attribute ASIC_CELL of FTSM : architecture is TRUE; 6781 6782 -- Backannotation attributes 6783 attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is "U14/tLH"; 6784 attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is "U14/tHL"; 6785 attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is "U13/tLH"; 6786 attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is "U13/tHL"; 6787 attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U12/tLH"; 6788 attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U12/tHL"; 6789 attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U11/tLH"; 6790 attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U11/tHL"; 6791 attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U10/tLH"; 6792 attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U10/tHL"; 6793 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U9/tLH"; 6794 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U9/tHL"; 6795 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U8/tLH"; 6796 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U8/tHL"; 6797 attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; 6798 attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; 6799 attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; 6800 attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; 6801 attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; 6802 attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; 6803 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 6804 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 6805 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 6806 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 6807 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 6808 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 6809 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 6810 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 6811 6812 signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); 6813 signal prop_nq : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); 6814 signal n1, n2, n3 : STD_LOGIC; 6815 6816 component AND2MAC 6817 generic( 6818 tpdY_R : Time := 0 ns; 6819 tpdY_F : Time := 0 ns; 6820 strn : STRENGTH := strn_X01); 6821 port( 6822 I0 : in STD_LOGIC; 6823 I1 : in STD_LOGIC; 6824 Y : out STD_LOGIC); 6825 end component; 6826 6827 component NAND3MAC 6828 generic( 6829 tpdY_R : Time := 0 ns; 6830 tpdY_F : Time := 0 ns; 6831 strn : STRENGTH := strn_X01); 6832 port( 6833 I0 : in STD_LOGIC; 6834 I1 : in STD_LOGIC; 6835 I2 : in STD_LOGIC; 6836 Y : out STD_LOGIC); 6837 end component; 6838 6839 component OR3MAC 6840 generic( 6841 tpdY_R : Time := 0 ns; 6842 tpdY_F : Time := 0 ns; 6843 strn : STRENGTH := strn_X01); 6844 port( 6845 I0 : in STD_LOGIC; 6846 I1 : in STD_LOGIC; 6847 I2 : in STD_LOGIC; 6848 Y : out STD_LOGIC); 6849 end component; 6850 6851 component NAND2MAC 6852 generic( 6853 tpdY_R : Time := 0 ns; 6854 tpdY_F : Time := 0 ns; 6855 strn : STRENGTH := strn_X01); 6856 port( 6857 I0 : in STD_LOGIC; 6858 I1 : in STD_LOGIC; 6859 Y : out STD_LOGIC); 6860 end component; 6861 6862begin 6863 6864 -- Extrinsic delay buffers 6865 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 6866 generic map( tLH => twdi0_R, tHL => twdi0_F) 6867 port map( Input => i0, Output => connect(0)); 6868 6869 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 6870 generic map( tLH => twdi1_R, tHL => twdi1_F) 6871 port map( Input => i1, Output => connect(1)); 6872 6873 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 6874 generic map( tLH => twdi2_R, tHL => twdi2_F) 6875 port map( Input => i2, Output => connect(2)); 6876 6877 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 6878 generic map( tLH => twdi3_R, tHL => twdi3_F) 6879 port map( Input => i3, Output => connect(3)); 6880 6881 U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 6882 generic map( tLH => twdi4_R, tHL => twdi4_F) 6883 port map( Input => i4, Output => connect(4)); 6884 6885 U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 6886 generic map( tLH => twdi5_R, tHL => twdi5_F) 6887 port map( Input => i5, Output => connect(5)); 6888 6889 U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 6890 generic map( tLH => twdi6_R, tHL => twdi6_F) 6891 port map( Input => i6, Output => connect(6)); 6892 6893 -- Intrinsic delay buffers 6894 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 6895 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 6896 port map( Input => connect(0), Output => prop_nq(0)); 6897 6898 U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 6899 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 6900 port map( Input => connect(1), Output => prop_nq(1)); 6901 6902 U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 6903 generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) 6904 port map( Input => connect(2), Output => prop_nq(2)); 6905 6906 U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 6907 generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) 6908 port map( Input => connect(3), Output => prop_nq(3)); 6909 6910 U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 6911 generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) 6912 port map( Input => connect(4), Output => prop_nq(4)); 6913 6914 U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 6915 generic map( tLH => tpdi5_nq_F, tHL => tpdi5_nq_R) 6916 port map( Input => connect(5), Output => prop_nq(5)); 6917 6918 U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 6919 generic map( tLH => tpdi6_nq_F, tHL => tpdi6_nq_R) 6920 port map( Input => connect(6), Output => prop_nq(6)); 6921 6922 -- Netlist 6923 U15 : AND2MAC 6924 port map( I0 => n1, I1 => n2, Y => nq); 6925 6926 U16 : NAND3MAC 6927 port map( I0 => prop_nq(1), I1 => prop_nq(2), I2 => prop_nq(0), Y => 6928 n2); 6929 6930 U17 : OR3MAC 6931 port map( I0 => prop_nq(3), I1 => prop_nq(4), I2 => prop_nq(5), Y => 6932 n3); 6933 6934 U18 : NAND2MAC 6935 port map( I0 => prop_nq(6), I1 => n3, Y => n1); 6936 6937 6938end FTSM; 6939 6940configuration CFG_noa3ao322_x4_FTSM of noa3ao322_x4 is 6941 for FTSM 6942 end for; 6943end CFG_noa3ao322_x4_FTSM; 6944 6945 6946----- CELL noa22_x1 ----- 6947library IEEE; 6948use IEEE.STD_LOGIC_1164.all; 6949library SYNOPSYS; 6950use SYNOPSYS.attributes.REAL_NAME; 6951 6952-- entity declaration -- 6953entity noa22_x1 is 6954 generic( 6955 Timing_mesg: Boolean := True; 6956 Timing_xgen: Boolean := False; 6957 tpdi0_nq_R : Time := 0.151 ns; 6958 tpdi0_nq_F : Time := 0.327 ns; 6959 tpdi1_nq_R : Time := 0.218 ns; 6960 tpdi1_nq_F : Time := 0.287 ns; 6961 tpdi2_nq_R : Time := 0.218 ns; 6962 tpdi2_nq_F : Time := 0.241 ns; 6963 twdi0_R : Time := 0.000 ns; 6964 twdi0_F : Time := 0.000 ns; 6965 twdi1_R : Time := 0.000 ns; 6966 twdi1_F : Time := 0.000 ns; 6967 twdi2_R : Time := 0.000 ns; 6968 twdi2_F : Time := 0.000 ns); 6969 6970 port( 6971 i0 : in STD_LOGIC; 6972 i1 : in STD_LOGIC; 6973 i2 : in STD_LOGIC; 6974 nq : out STD_LOGIC); 6975end noa22_x1; 6976 6977-- architecture body -- 6978library IEEE_ASIC; 6979use IEEE.STD_LOGIC_MISC.all; 6980use SYNOPSYS.attributes.backplane; 6981use SYNOPSYS.attributes.PRIVATE; 6982use SYNOPSYS.attributes.ASIC_CELL; 6983use SYNOPSYS.attributes.PROPAGATE_VALUE; 6984 6985architecture FTSM of noa22_x1 is 6986 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 6987 attribute PRIVATE of FTSM : architecture is TRUE; 6988 attribute ASIC_CELL of FTSM : architecture is TRUE; 6989 6990 -- Backannotation attributes 6991 attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; 6992 attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; 6993 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; 6994 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; 6995 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; 6996 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; 6997 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 6998 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 6999 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 7000 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 7001 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 7002 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 7003 7004 signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 7005 signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 7006 signal n1 : STD_LOGIC; 7007 7008 component NOR2MAC 7009 generic( 7010 tpdY_R : Time := 0 ns; 7011 tpdY_F : Time := 0 ns; 7012 strn : STRENGTH := strn_X01); 7013 port( 7014 I0 : in STD_LOGIC; 7015 I1 : in STD_LOGIC; 7016 Y : out STD_LOGIC); 7017 end component; 7018 7019 component AND2MAC 7020 generic( 7021 tpdY_R : Time := 0 ns; 7022 tpdY_F : Time := 0 ns; 7023 strn : STRENGTH := strn_X01); 7024 port( 7025 I0 : in STD_LOGIC; 7026 I1 : in STD_LOGIC; 7027 Y : out STD_LOGIC); 7028 end component; 7029 7030begin 7031 7032 -- Extrinsic delay buffers 7033 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 7034 generic map( tLH => twdi0_R, tHL => twdi0_F) 7035 port map( Input => i0, Output => connect(0)); 7036 7037 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 7038 generic map( tLH => twdi1_R, tHL => twdi1_F) 7039 port map( Input => i1, Output => connect(1)); 7040 7041 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 7042 generic map( tLH => twdi2_R, tHL => twdi2_F) 7043 port map( Input => i2, Output => connect(2)); 7044 7045 -- Intrinsic delay buffers 7046 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 7047 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 7048 port map( Input => connect(0), Output => prop_nq(0)); 7049 7050 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 7051 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 7052 port map( Input => connect(1), Output => prop_nq(1)); 7053 7054 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 7055 generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) 7056 port map( Input => connect(2), Output => prop_nq(2)); 7057 7058 -- Netlist 7059 U7 : NOR2MAC 7060 port map( I0 => prop_nq(2), I1 => n1, Y => nq); 7061 7062 U8 : AND2MAC 7063 port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); 7064 7065 7066end FTSM; 7067 7068configuration CFG_noa22_x1_FTSM of noa22_x1 is 7069 for FTSM 7070 end for; 7071end CFG_noa22_x1_FTSM; 7072 7073 7074----- CELL noa22_x4 ----- 7075library IEEE; 7076use IEEE.STD_LOGIC_1164.all; 7077library SYNOPSYS; 7078use SYNOPSYS.attributes.REAL_NAME; 7079 7080-- entity declaration -- 7081entity noa22_x4 is 7082 generic( 7083 Timing_mesg: Boolean := True; 7084 Timing_xgen: Boolean := False; 7085 tpdi0_nq_R : Time := 0.550 ns; 7086 tpdi0_nq_F : Time := 0.740 ns; 7087 tpdi1_nq_R : Time := 0.643 ns; 7088 tpdi1_nq_F : Time := 0.709 ns; 7089 tpdi2_nq_R : Time := 0.610 ns; 7090 tpdi2_nq_F : Time := 0.646 ns; 7091 twdi0_R : Time := 0.000 ns; 7092 twdi0_F : Time := 0.000 ns; 7093 twdi1_R : Time := 0.000 ns; 7094 twdi1_F : Time := 0.000 ns; 7095 twdi2_R : Time := 0.000 ns; 7096 twdi2_F : Time := 0.000 ns); 7097 7098 port( 7099 i0 : in STD_LOGIC; 7100 i1 : in STD_LOGIC; 7101 i2 : in STD_LOGIC; 7102 nq : out STD_LOGIC); 7103end noa22_x4; 7104 7105-- architecture body -- 7106library IEEE_ASIC; 7107use IEEE.STD_LOGIC_MISC.all; 7108use SYNOPSYS.attributes.backplane; 7109use SYNOPSYS.attributes.PRIVATE; 7110use SYNOPSYS.attributes.ASIC_CELL; 7111use SYNOPSYS.attributes.PROPAGATE_VALUE; 7112 7113architecture FTSM of noa22_x4 is 7114 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 7115 attribute PRIVATE of FTSM : architecture is TRUE; 7116 attribute ASIC_CELL of FTSM : architecture is TRUE; 7117 7118 -- Backannotation attributes 7119 attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; 7120 attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; 7121 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; 7122 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; 7123 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; 7124 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; 7125 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 7126 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 7127 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 7128 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 7129 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 7130 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 7131 7132 signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 7133 signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 7134 signal n1 : STD_LOGIC; 7135 7136 component NOR2MAC 7137 generic( 7138 tpdY_R : Time := 0 ns; 7139 tpdY_F : Time := 0 ns; 7140 strn : STRENGTH := strn_X01); 7141 port( 7142 I0 : in STD_LOGIC; 7143 I1 : in STD_LOGIC; 7144 Y : out STD_LOGIC); 7145 end component; 7146 7147 component AND2MAC 7148 generic( 7149 tpdY_R : Time := 0 ns; 7150 tpdY_F : Time := 0 ns; 7151 strn : STRENGTH := strn_X01); 7152 port( 7153 I0 : in STD_LOGIC; 7154 I1 : in STD_LOGIC; 7155 Y : out STD_LOGIC); 7156 end component; 7157 7158begin 7159 7160 -- Extrinsic delay buffers 7161 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 7162 generic map( tLH => twdi0_R, tHL => twdi0_F) 7163 port map( Input => i0, Output => connect(0)); 7164 7165 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 7166 generic map( tLH => twdi1_R, tHL => twdi1_F) 7167 port map( Input => i1, Output => connect(1)); 7168 7169 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 7170 generic map( tLH => twdi2_R, tHL => twdi2_F) 7171 port map( Input => i2, Output => connect(2)); 7172 7173 -- Intrinsic delay buffers 7174 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 7175 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 7176 port map( Input => connect(0), Output => prop_nq(0)); 7177 7178 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 7179 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 7180 port map( Input => connect(1), Output => prop_nq(1)); 7181 7182 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 7183 generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) 7184 port map( Input => connect(2), Output => prop_nq(2)); 7185 7186 -- Netlist 7187 U7 : NOR2MAC 7188 port map( I0 => prop_nq(2), I1 => n1, Y => nq); 7189 7190 U8 : AND2MAC 7191 port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); 7192 7193 7194end FTSM; 7195 7196configuration CFG_noa22_x4_FTSM of noa22_x4 is 7197 for FTSM 7198 end for; 7199end CFG_noa22_x4_FTSM; 7200 7201 7202----- CELL nts_x1 ----- 7203library IEEE; 7204use IEEE.STD_LOGIC_1164.all; 7205library SYNOPSYS; 7206use SYNOPSYS.attributes.REAL_NAME; 7207 7208-- entity declaration -- 7209entity nts_x1 is 7210 generic( 7211 Timing_mesg: Boolean := True; 7212 Timing_xgen: Boolean := False; 7213 tpdcmd_nq_R : Time := 0.249 ns; 7214 tpdcmd_nq_F : Time := 0.041 ns; 7215 tpdcmd_nq_LZ : Time := 0.249 ns; 7216 tpdcmd_nq_HZ : Time := 0.041 ns; 7217 tpdi_nq_R : Time := 0.169 ns; 7218 tpdi_nq_F : Time := 0.201 ns; 7219 twdi_R : Time := 0.000 ns; 7220 twdi_F : Time := 0.000 ns; 7221 twdcmd_R : Time := 0.000 ns; 7222 twdcmd_F : Time := 0.000 ns); 7223 7224 port( 7225 i : in STD_LOGIC; 7226 cmd : in STD_LOGIC; 7227 nq : out STD_LOGIC); 7228end nts_x1; 7229 7230-- architecture body -- 7231library IEEE_ASIC; 7232use IEEE.STD_LOGIC_MISC.all; 7233use SYNOPSYS.attributes.backplane; 7234use SYNOPSYS.attributes.PRIVATE; 7235use SYNOPSYS.attributes.ASIC_CELL; 7236use SYNOPSYS.attributes.PROPAGATE_VALUE; 7237 7238architecture FTSM of nts_x1 is 7239 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 7240 attribute PRIVATE of FTSM : architecture is TRUE; 7241 attribute ASIC_CELL of FTSM : architecture is TRUE; 7242 7243 -- Backannotation attributes 7244 attribute PROPAGATE_VALUE of tpdi_nq_F: constant is "U4/tLH"; 7245 attribute PROPAGATE_VALUE of tpdi_nq_R: constant is "U4/tHL"; 7246 attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is "U3/tHL, U3/tLH"; 7247 attribute PROPAGATE_VALUE of tpdcmd_nq_HZ: constant is "U3/tLH, U3/tHL"; 7248 attribute PROPAGATE_VALUE of tpdcmd_nq_LZ: constant is "U3/tLH, U3/tHL"; 7249 attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is "U3/tLH, U3/tHL"; 7250 attribute PROPAGATE_VALUE of twdcmd_F: constant is "U2/tHL"; 7251 attribute PROPAGATE_VALUE of twdcmd_R: constant is "U2/tLH"; 7252 attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; 7253 attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; 7254 7255 signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 7256 signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 7257 7258 component INV3SHEMAC 7259 generic( 7260 tpdY_R : Time := 0 ns; 7261 tpdY_F : Time := 0 ns; 7262 strn : STRENGTH := strn_X01); 7263 port( 7264 I0 : in STD_LOGIC; 7265 OE : in STD_LOGIC; 7266 Y : out STD_LOGIC); 7267 end component; 7268 7269begin 7270 7271 -- Extrinsic delay buffers 7272 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 7273 generic map( tLH => twdi_R, tHL => twdi_F) 7274 port map( Input => i, Output => connect(1)); 7275 7276 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 7277 generic map( tLH => twdcmd_R, tHL => twdcmd_F) 7278 port map( Input => cmd, Output => connect(0)); 7279 7280 -- Intrinsic delay buffers 7281 U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 7282 generic map( tLH => tpdcmd_nq_R, tHL => tpdcmd_nq_R) 7283 port map( Input => connect(0), Output => prop_nq(0)); 7284 7285 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 7286 generic map( tLH => tpdi_nq_F, tHL => tpdi_nq_R) 7287 port map( Input => connect(1), Output => prop_nq(1)); 7288 7289 -- Netlist 7290 U5 : INV3SHEMAC 7291 port map( I0 => prop_nq(1), OE => prop_nq(0), Y => nq); 7292 7293 7294end FTSM; 7295 7296configuration CFG_nts_x1_FTSM of nts_x1 is 7297 for FTSM 7298 end for; 7299end CFG_nts_x1_FTSM; 7300 7301 7302----- CELL nts_x2 ----- 7303library IEEE; 7304use IEEE.STD_LOGIC_1164.all; 7305library SYNOPSYS; 7306use SYNOPSYS.attributes.REAL_NAME; 7307 7308-- entity declaration -- 7309entity nts_x2 is 7310 generic( 7311 Timing_mesg: Boolean := True; 7312 Timing_xgen: Boolean := False; 7313 tpdcmd_nq_R : Time := 0.330 ns; 7314 tpdcmd_nq_F : Time := 0.033 ns; 7315 tpdcmd_nq_LZ : Time := 0.330 ns; 7316 tpdcmd_nq_HZ : Time := 0.033 ns; 7317 tpdi_nq_R : Time := 0.167 ns; 7318 tpdi_nq_F : Time := 0.201 ns; 7319 twdi_R : Time := 0.000 ns; 7320 twdi_F : Time := 0.000 ns; 7321 twdcmd_R : Time := 0.000 ns; 7322 twdcmd_F : Time := 0.000 ns); 7323 7324 port( 7325 i : in STD_LOGIC; 7326 cmd : in STD_LOGIC; 7327 nq : out STD_LOGIC); 7328end nts_x2; 7329 7330-- architecture body -- 7331library IEEE_ASIC; 7332use IEEE.STD_LOGIC_MISC.all; 7333use SYNOPSYS.attributes.backplane; 7334use SYNOPSYS.attributes.PRIVATE; 7335use SYNOPSYS.attributes.ASIC_CELL; 7336use SYNOPSYS.attributes.PROPAGATE_VALUE; 7337 7338architecture FTSM of nts_x2 is 7339 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 7340 attribute PRIVATE of FTSM : architecture is TRUE; 7341 attribute ASIC_CELL of FTSM : architecture is TRUE; 7342 7343 -- Backannotation attributes 7344 attribute PROPAGATE_VALUE of tpdi_nq_F: constant is "U4/tLH"; 7345 attribute PROPAGATE_VALUE of tpdi_nq_R: constant is "U4/tHL"; 7346 attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is "U3/tHL, U3/tLH"; 7347 attribute PROPAGATE_VALUE of tpdcmd_nq_HZ: constant is "U3/tLH, U3/tHL"; 7348 attribute PROPAGATE_VALUE of tpdcmd_nq_LZ: constant is "U3/tLH, U3/tHL"; 7349 attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is "U3/tLH, U3/tHL"; 7350 attribute PROPAGATE_VALUE of twdcmd_F: constant is "U2/tHL"; 7351 attribute PROPAGATE_VALUE of twdcmd_R: constant is "U2/tLH"; 7352 attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; 7353 attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; 7354 7355 signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 7356 signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 7357 7358 component INV3SHEMAC 7359 generic( 7360 tpdY_R : Time := 0 ns; 7361 tpdY_F : Time := 0 ns; 7362 strn : STRENGTH := strn_X01); 7363 port( 7364 I0 : in STD_LOGIC; 7365 OE : in STD_LOGIC; 7366 Y : out STD_LOGIC); 7367 end component; 7368 7369begin 7370 7371 -- Extrinsic delay buffers 7372 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 7373 generic map( tLH => twdi_R, tHL => twdi_F) 7374 port map( Input => i, Output => connect(1)); 7375 7376 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 7377 generic map( tLH => twdcmd_R, tHL => twdcmd_F) 7378 port map( Input => cmd, Output => connect(0)); 7379 7380 -- Intrinsic delay buffers 7381 U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 7382 generic map( tLH => tpdcmd_nq_R, tHL => tpdcmd_nq_R) 7383 port map( Input => connect(0), Output => prop_nq(0)); 7384 7385 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 7386 generic map( tLH => tpdi_nq_F, tHL => tpdi_nq_R) 7387 port map( Input => connect(1), Output => prop_nq(1)); 7388 7389 -- Netlist 7390 U5 : INV3SHEMAC 7391 port map( I0 => prop_nq(1), OE => prop_nq(0), Y => nq); 7392 7393 7394end FTSM; 7395 7396configuration CFG_nts_x2_FTSM of nts_x2 is 7397 for FTSM 7398 end for; 7399end CFG_nts_x2_FTSM; 7400 7401 7402----- CELL nxr2_x1 ----- 7403library IEEE; 7404use IEEE.STD_LOGIC_1164.all; 7405library SYNOPSYS; 7406use SYNOPSYS.attributes.REAL_NAME; 7407 7408-- entity declaration -- 7409entity nxr2_x1 is 7410 generic( 7411 Timing_mesg: Boolean := True; 7412 Timing_xgen: Boolean := False; 7413 tpdi0_nq_R : Time := 0.288 ns; 7414 tpdi0_nq_F : Time := 0.293 ns; 7415 tpdi1_nq_R : Time := 0.156 ns; 7416 tpdi1_nq_F : Time := 0.327 ns; 7417 twdi0_R : Time := 0.000 ns; 7418 twdi0_F : Time := 0.000 ns; 7419 twdi1_R : Time := 0.000 ns; 7420 twdi1_F : Time := 0.000 ns); 7421 7422 port( 7423 i0 : in STD_LOGIC; 7424 i1 : in STD_LOGIC; 7425 nq : out STD_LOGIC); 7426end nxr2_x1; 7427 7428-- architecture body -- 7429library IEEE_ASIC; 7430use IEEE.STD_LOGIC_MISC.all; 7431use SYNOPSYS.attributes.backplane; 7432use SYNOPSYS.attributes.PRIVATE; 7433use SYNOPSYS.attributes.ASIC_CELL; 7434use SYNOPSYS.attributes.PROPAGATE_VALUE; 7435 7436architecture FTSM of nxr2_x1 is 7437 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 7438 attribute PRIVATE of FTSM : architecture is TRUE; 7439 attribute ASIC_CELL of FTSM : architecture is TRUE; 7440 7441 -- Backannotation attributes 7442 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U4/tLH"; 7443 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U4/tHL"; 7444 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U3/tLH"; 7445 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U3/tHL"; 7446 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 7447 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 7448 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 7449 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 7450 7451 signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 7452 signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 7453 7454 component NXOR2MAC 7455 generic( 7456 tpdY_R : Time := 0 ns; 7457 tpdY_F : Time := 0 ns; 7458 strn : STRENGTH := strn_X01); 7459 port( 7460 I0 : in STD_LOGIC; 7461 I1 : in STD_LOGIC; 7462 Y : out STD_LOGIC); 7463 end component; 7464 7465begin 7466 7467 -- Extrinsic delay buffers 7468 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 7469 generic map( tLH => twdi0_R, tHL => twdi0_F) 7470 port map( Input => i0, Output => connect(0)); 7471 7472 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 7473 generic map( tLH => twdi1_R, tHL => twdi1_F) 7474 port map( Input => i1, Output => connect(1)); 7475 7476 -- Intrinsic delay buffers 7477 U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 7478 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 7479 port map( Input => connect(0), Output => prop_nq(0)); 7480 7481 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 7482 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 7483 port map( Input => connect(1), Output => prop_nq(1)); 7484 7485 -- Netlist 7486 U5 : NXOR2MAC 7487 port map( I0 => prop_nq(1), I1 => prop_nq(0), Y => nq); 7488 7489 7490end FTSM; 7491 7492configuration CFG_nxr2_x1_FTSM of nxr2_x1 is 7493 for FTSM 7494 end for; 7495end CFG_nxr2_x1_FTSM; 7496 7497 7498----- CELL nxr2_x4 ----- 7499library IEEE; 7500use IEEE.STD_LOGIC_1164.all; 7501library SYNOPSYS; 7502use SYNOPSYS.attributes.REAL_NAME; 7503 7504-- entity declaration -- 7505entity nxr2_x4 is 7506 generic( 7507 Timing_mesg: Boolean := True; 7508 Timing_xgen: Boolean := False; 7509 tpdi0_nq_R : Time := 0.522 ns; 7510 tpdi0_nq_F : Time := 0.553 ns; 7511 tpdi1_nq_R : Time := 0.553 ns; 7512 tpdi1_nq_F : Time := 0.542 ns; 7513 twdi0_R : Time := 0.000 ns; 7514 twdi0_F : Time := 0.000 ns; 7515 twdi1_R : Time := 0.000 ns; 7516 twdi1_F : Time := 0.000 ns); 7517 7518 port( 7519 i0 : in STD_LOGIC; 7520 i1 : in STD_LOGIC; 7521 nq : out STD_LOGIC); 7522end nxr2_x4; 7523 7524-- architecture body -- 7525library IEEE_ASIC; 7526use IEEE.STD_LOGIC_MISC.all; 7527use SYNOPSYS.attributes.backplane; 7528use SYNOPSYS.attributes.PRIVATE; 7529use SYNOPSYS.attributes.ASIC_CELL; 7530use SYNOPSYS.attributes.PROPAGATE_VALUE; 7531 7532architecture FTSM of nxr2_x4 is 7533 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 7534 attribute PRIVATE of FTSM : architecture is TRUE; 7535 attribute ASIC_CELL of FTSM : architecture is TRUE; 7536 7537 -- Backannotation attributes 7538 attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U4/tLH"; 7539 attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U4/tHL"; 7540 attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U3/tLH"; 7541 attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U3/tHL"; 7542 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 7543 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 7544 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 7545 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 7546 7547 signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 7548 signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 7549 7550 component NXOR2MAC 7551 generic( 7552 tpdY_R : Time := 0 ns; 7553 tpdY_F : Time := 0 ns; 7554 strn : STRENGTH := strn_X01); 7555 port( 7556 I0 : in STD_LOGIC; 7557 I1 : in STD_LOGIC; 7558 Y : out STD_LOGIC); 7559 end component; 7560 7561begin 7562 7563 -- Extrinsic delay buffers 7564 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 7565 generic map( tLH => twdi0_R, tHL => twdi0_F) 7566 port map( Input => i0, Output => connect(0)); 7567 7568 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 7569 generic map( tLH => twdi1_R, tHL => twdi1_F) 7570 port map( Input => i1, Output => connect(1)); 7571 7572 -- Intrinsic delay buffers 7573 U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 7574 generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) 7575 port map( Input => connect(0), Output => prop_nq(0)); 7576 7577 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 7578 generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) 7579 port map( Input => connect(1), Output => prop_nq(1)); 7580 7581 -- Netlist 7582 U5 : NXOR2MAC 7583 port map( I0 => prop_nq(1), I1 => prop_nq(0), Y => nq); 7584 7585 7586end FTSM; 7587 7588configuration CFG_nxr2_x4_FTSM of nxr2_x4 is 7589 for FTSM 7590 end for; 7591end CFG_nxr2_x4_FTSM; 7592 7593 7594----- CELL o2_x2 ----- 7595library IEEE; 7596use IEEE.STD_LOGIC_1164.all; 7597library SYNOPSYS; 7598use SYNOPSYS.attributes.REAL_NAME; 7599 7600-- entity declaration -- 7601entity o2_x2 is 7602 generic( 7603 Timing_mesg: Boolean := True; 7604 Timing_xgen: Boolean := False; 7605 tpdi0_q_R : Time := 0.406 ns; 7606 tpdi0_q_F : Time := 0.310 ns; 7607 tpdi1_q_R : Time := 0.335 ns; 7608 tpdi1_q_F : Time := 0.364 ns; 7609 twdi0_R : Time := 0.000 ns; 7610 twdi0_F : Time := 0.000 ns; 7611 twdi1_R : Time := 0.000 ns; 7612 twdi1_F : Time := 0.000 ns); 7613 7614 port( 7615 i0 : in STD_LOGIC; 7616 i1 : in STD_LOGIC; 7617 q : out STD_LOGIC); 7618end o2_x2; 7619 7620-- architecture body -- 7621library IEEE_ASIC; 7622use IEEE.STD_LOGIC_MISC.all; 7623use SYNOPSYS.attributes.backplane; 7624use SYNOPSYS.attributes.PRIVATE; 7625use SYNOPSYS.attributes.ASIC_CELL; 7626use SYNOPSYS.attributes.PROPAGATE_VALUE; 7627 7628architecture FTSM of o2_x2 is 7629 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 7630 attribute PRIVATE of FTSM : architecture is TRUE; 7631 attribute ASIC_CELL of FTSM : architecture is TRUE; 7632 7633 -- Backannotation attributes 7634 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; 7635 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; 7636 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tLH"; 7637 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tHL"; 7638 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 7639 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 7640 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 7641 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 7642 7643 signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 7644 signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 7645 7646 component OR2MAC 7647 generic( 7648 tpdY_R : Time := 0 ns; 7649 tpdY_F : Time := 0 ns; 7650 strn : STRENGTH := strn_X01); 7651 port( 7652 I0 : in STD_LOGIC; 7653 I1 : in STD_LOGIC; 7654 Y : out STD_LOGIC); 7655 end component; 7656 7657begin 7658 7659 -- Extrinsic delay buffers 7660 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 7661 generic map( tLH => twdi0_R, tHL => twdi0_F) 7662 port map( Input => i0, Output => connect(0)); 7663 7664 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 7665 generic map( tLH => twdi1_R, tHL => twdi1_F) 7666 port map( Input => i1, Output => connect(1)); 7667 7668 -- Intrinsic delay buffers 7669 U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 7670 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 7671 port map( Input => connect(0), Output => prop_q(0)); 7672 7673 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 7674 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 7675 port map( Input => connect(1), Output => prop_q(1)); 7676 7677 -- Netlist 7678 U5 : OR2MAC 7679 port map( I0 => prop_q(1), I1 => prop_q(0), Y => q); 7680 7681 7682end FTSM; 7683 7684configuration CFG_o2_x2_FTSM of o2_x2 is 7685 for FTSM 7686 end for; 7687end CFG_o2_x2_FTSM; 7688 7689 7690----- CELL o2_x4 ----- 7691library IEEE; 7692use IEEE.STD_LOGIC_1164.all; 7693library SYNOPSYS; 7694use SYNOPSYS.attributes.REAL_NAME; 7695 7696-- entity declaration -- 7697entity o2_x4 is 7698 generic( 7699 Timing_mesg: Boolean := True; 7700 Timing_xgen: Boolean := False; 7701 tpdi0_q_R : Time := 0.491 ns; 7702 tpdi0_q_F : Time := 0.394 ns; 7703 tpdi1_q_R : Time := 0.427 ns; 7704 tpdi1_q_F : Time := 0.464 ns; 7705 twdi0_R : Time := 0.000 ns; 7706 twdi0_F : Time := 0.000 ns; 7707 twdi1_R : Time := 0.000 ns; 7708 twdi1_F : Time := 0.000 ns); 7709 7710 port( 7711 i0 : in STD_LOGIC; 7712 i1 : in STD_LOGIC; 7713 q : out STD_LOGIC); 7714end o2_x4; 7715 7716-- architecture body -- 7717library IEEE_ASIC; 7718use IEEE.STD_LOGIC_MISC.all; 7719use SYNOPSYS.attributes.backplane; 7720use SYNOPSYS.attributes.PRIVATE; 7721use SYNOPSYS.attributes.ASIC_CELL; 7722use SYNOPSYS.attributes.PROPAGATE_VALUE; 7723 7724architecture FTSM of o2_x4 is 7725 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 7726 attribute PRIVATE of FTSM : architecture is TRUE; 7727 attribute ASIC_CELL of FTSM : architecture is TRUE; 7728 7729 -- Backannotation attributes 7730 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; 7731 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; 7732 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tLH"; 7733 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tHL"; 7734 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 7735 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 7736 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 7737 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 7738 7739 signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 7740 signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 7741 7742 component OR2MAC 7743 generic( 7744 tpdY_R : Time := 0 ns; 7745 tpdY_F : Time := 0 ns; 7746 strn : STRENGTH := strn_X01); 7747 port( 7748 I0 : in STD_LOGIC; 7749 I1 : in STD_LOGIC; 7750 Y : out STD_LOGIC); 7751 end component; 7752 7753begin 7754 7755 -- Extrinsic delay buffers 7756 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 7757 generic map( tLH => twdi0_R, tHL => twdi0_F) 7758 port map( Input => i0, Output => connect(0)); 7759 7760 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 7761 generic map( tLH => twdi1_R, tHL => twdi1_F) 7762 port map( Input => i1, Output => connect(1)); 7763 7764 -- Intrinsic delay buffers 7765 U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 7766 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 7767 port map( Input => connect(0), Output => prop_q(0)); 7768 7769 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 7770 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 7771 port map( Input => connect(1), Output => prop_q(1)); 7772 7773 -- Netlist 7774 U5 : OR2MAC 7775 port map( I0 => prop_q(1), I1 => prop_q(0), Y => q); 7776 7777 7778end FTSM; 7779 7780configuration CFG_o2_x4_FTSM of o2_x4 is 7781 for FTSM 7782 end for; 7783end CFG_o2_x4_FTSM; 7784 7785 7786----- CELL o3_x2 ----- 7787library IEEE; 7788use IEEE.STD_LOGIC_1164.all; 7789library SYNOPSYS; 7790use SYNOPSYS.attributes.REAL_NAME; 7791 7792-- entity declaration -- 7793entity o3_x2 is 7794 generic( 7795 Timing_mesg: Boolean := True; 7796 Timing_xgen: Boolean := False; 7797 tpdi0_q_R : Time := 0.494 ns; 7798 tpdi0_q_F : Time := 0.407 ns; 7799 tpdi1_q_R : Time := 0.430 ns; 7800 tpdi1_q_F : Time := 0.482 ns; 7801 tpdi2_q_R : Time := 0.360 ns; 7802 tpdi2_q_F : Time := 0.506 ns; 7803 twdi0_R : Time := 0.000 ns; 7804 twdi0_F : Time := 0.000 ns; 7805 twdi1_R : Time := 0.000 ns; 7806 twdi1_F : Time := 0.000 ns; 7807 twdi2_R : Time := 0.000 ns; 7808 twdi2_F : Time := 0.000 ns); 7809 7810 port( 7811 i0 : in STD_LOGIC; 7812 i1 : in STD_LOGIC; 7813 i2 : in STD_LOGIC; 7814 q : out STD_LOGIC); 7815end o3_x2; 7816 7817-- architecture body -- 7818library IEEE_ASIC; 7819use IEEE.STD_LOGIC_MISC.all; 7820use SYNOPSYS.attributes.backplane; 7821use SYNOPSYS.attributes.PRIVATE; 7822use SYNOPSYS.attributes.ASIC_CELL; 7823use SYNOPSYS.attributes.PROPAGATE_VALUE; 7824 7825architecture FTSM of o3_x2 is 7826 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 7827 attribute PRIVATE of FTSM : architecture is TRUE; 7828 attribute ASIC_CELL of FTSM : architecture is TRUE; 7829 7830 -- Backannotation attributes 7831 attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; 7832 attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; 7833 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; 7834 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; 7835 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; 7836 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; 7837 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 7838 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 7839 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 7840 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 7841 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 7842 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 7843 7844 signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 7845 signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 7846 7847 component OR3MAC 7848 generic( 7849 tpdY_R : Time := 0 ns; 7850 tpdY_F : Time := 0 ns; 7851 strn : STRENGTH := strn_X01); 7852 port( 7853 I0 : in STD_LOGIC; 7854 I1 : in STD_LOGIC; 7855 I2 : in STD_LOGIC; 7856 Y : out STD_LOGIC); 7857 end component; 7858 7859begin 7860 7861 -- Extrinsic delay buffers 7862 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 7863 generic map( tLH => twdi0_R, tHL => twdi0_F) 7864 port map( Input => i0, Output => connect(0)); 7865 7866 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 7867 generic map( tLH => twdi1_R, tHL => twdi1_F) 7868 port map( Input => i1, Output => connect(1)); 7869 7870 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 7871 generic map( tLH => twdi2_R, tHL => twdi2_F) 7872 port map( Input => i2, Output => connect(2)); 7873 7874 -- Intrinsic delay buffers 7875 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 7876 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 7877 port map( Input => connect(0), Output => prop_q(0)); 7878 7879 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 7880 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 7881 port map( Input => connect(1), Output => prop_q(1)); 7882 7883 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 7884 generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) 7885 port map( Input => connect(2), Output => prop_q(2)); 7886 7887 -- Netlist 7888 U7 : OR3MAC 7889 port map( I0 => prop_q(0), I1 => prop_q(1), I2 => prop_q(2), Y => 7890 q); 7891 7892 7893end FTSM; 7894 7895configuration CFG_o3_x2_FTSM of o3_x2 is 7896 for FTSM 7897 end for; 7898end CFG_o3_x2_FTSM; 7899 7900 7901----- CELL o3_x4 ----- 7902library IEEE; 7903use IEEE.STD_LOGIC_1164.all; 7904library SYNOPSYS; 7905use SYNOPSYS.attributes.REAL_NAME; 7906 7907-- entity declaration -- 7908entity o3_x4 is 7909 generic( 7910 Timing_mesg: Boolean := True; 7911 Timing_xgen: Boolean := False; 7912 tpdi0_q_R : Time := 0.569 ns; 7913 tpdi0_q_F : Time := 0.501 ns; 7914 tpdi1_q_R : Time := 0.510 ns; 7915 tpdi1_q_F : Time := 0.585 ns; 7916 tpdi2_q_R : Time := 0.447 ns; 7917 tpdi2_q_F : Time := 0.622 ns; 7918 twdi0_R : Time := 0.000 ns; 7919 twdi0_F : Time := 0.000 ns; 7920 twdi1_R : Time := 0.000 ns; 7921 twdi1_F : Time := 0.000 ns; 7922 twdi2_R : Time := 0.000 ns; 7923 twdi2_F : Time := 0.000 ns); 7924 7925 port( 7926 i0 : in STD_LOGIC; 7927 i1 : in STD_LOGIC; 7928 i2 : in STD_LOGIC; 7929 q : out STD_LOGIC); 7930end o3_x4; 7931 7932-- architecture body -- 7933library IEEE_ASIC; 7934use IEEE.STD_LOGIC_MISC.all; 7935use SYNOPSYS.attributes.backplane; 7936use SYNOPSYS.attributes.PRIVATE; 7937use SYNOPSYS.attributes.ASIC_CELL; 7938use SYNOPSYS.attributes.PROPAGATE_VALUE; 7939 7940architecture FTSM of o3_x4 is 7941 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 7942 attribute PRIVATE of FTSM : architecture is TRUE; 7943 attribute ASIC_CELL of FTSM : architecture is TRUE; 7944 7945 -- Backannotation attributes 7946 attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; 7947 attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; 7948 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; 7949 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; 7950 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; 7951 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; 7952 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 7953 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 7954 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 7955 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 7956 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 7957 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 7958 7959 signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 7960 signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 7961 7962 component OR3MAC 7963 generic( 7964 tpdY_R : Time := 0 ns; 7965 tpdY_F : Time := 0 ns; 7966 strn : STRENGTH := strn_X01); 7967 port( 7968 I0 : in STD_LOGIC; 7969 I1 : in STD_LOGIC; 7970 I2 : in STD_LOGIC; 7971 Y : out STD_LOGIC); 7972 end component; 7973 7974begin 7975 7976 -- Extrinsic delay buffers 7977 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 7978 generic map( tLH => twdi0_R, tHL => twdi0_F) 7979 port map( Input => i0, Output => connect(0)); 7980 7981 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 7982 generic map( tLH => twdi1_R, tHL => twdi1_F) 7983 port map( Input => i1, Output => connect(1)); 7984 7985 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 7986 generic map( tLH => twdi2_R, tHL => twdi2_F) 7987 port map( Input => i2, Output => connect(2)); 7988 7989 -- Intrinsic delay buffers 7990 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 7991 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 7992 port map( Input => connect(0), Output => prop_q(0)); 7993 7994 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 7995 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 7996 port map( Input => connect(1), Output => prop_q(1)); 7997 7998 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 7999 generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) 8000 port map( Input => connect(2), Output => prop_q(2)); 8001 8002 -- Netlist 8003 U7 : OR3MAC 8004 port map( I0 => prop_q(0), I1 => prop_q(1), I2 => prop_q(2), Y => 8005 q); 8006 8007 8008end FTSM; 8009 8010configuration CFG_o3_x4_FTSM of o3_x4 is 8011 for FTSM 8012 end for; 8013end CFG_o3_x4_FTSM; 8014 8015 8016----- CELL o4_x2 ----- 8017library IEEE; 8018use IEEE.STD_LOGIC_1164.all; 8019library SYNOPSYS; 8020use SYNOPSYS.attributes.REAL_NAME; 8021 8022-- entity declaration -- 8023entity o4_x2 is 8024 generic( 8025 Timing_mesg: Boolean := True; 8026 Timing_xgen: Boolean := False; 8027 tpdi0_q_R : Time := 0.508 ns; 8028 tpdi0_q_F : Time := 0.601 ns; 8029 tpdi1_q_R : Time := 0.446 ns; 8030 tpdi1_q_F : Time := 0.631 ns; 8031 tpdi2_q_R : Time := 0.567 ns; 8032 tpdi2_q_F : Time := 0.531 ns; 8033 tpdi3_q_R : Time := 0.378 ns; 8034 tpdi3_q_F : Time := 0.626 ns; 8035 twdi0_R : Time := 0.000 ns; 8036 twdi0_F : Time := 0.000 ns; 8037 twdi1_R : Time := 0.000 ns; 8038 twdi1_F : Time := 0.000 ns; 8039 twdi2_R : Time := 0.000 ns; 8040 twdi2_F : Time := 0.000 ns; 8041 twdi3_R : Time := 0.000 ns; 8042 twdi3_F : Time := 0.000 ns); 8043 8044 port( 8045 i0 : in STD_LOGIC; 8046 i1 : in STD_LOGIC; 8047 i2 : in STD_LOGIC; 8048 i3 : in STD_LOGIC; 8049 q : out STD_LOGIC); 8050end o4_x2; 8051 8052-- architecture body -- 8053library IEEE_ASIC; 8054use IEEE.STD_LOGIC_MISC.all; 8055use SYNOPSYS.attributes.backplane; 8056use SYNOPSYS.attributes.PRIVATE; 8057use SYNOPSYS.attributes.ASIC_CELL; 8058use SYNOPSYS.attributes.PROPAGATE_VALUE; 8059 8060architecture FTSM of o4_x2 is 8061 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 8062 attribute PRIVATE of FTSM : architecture is TRUE; 8063 attribute ASIC_CELL of FTSM : architecture is TRUE; 8064 8065 -- Backannotation attributes 8066 attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; 8067 attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; 8068 attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; 8069 attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; 8070 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; 8071 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; 8072 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; 8073 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; 8074 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 8075 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 8076 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 8077 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 8078 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 8079 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 8080 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 8081 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 8082 8083 signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 8084 signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 8085 8086 component OR4MAC 8087 generic( 8088 tpdY_R : Time := 0 ns; 8089 tpdY_F : Time := 0 ns; 8090 strn : STRENGTH := strn_X01); 8091 port( 8092 I0 : in STD_LOGIC; 8093 I1 : in STD_LOGIC; 8094 I2 : in STD_LOGIC; 8095 I3 : in STD_LOGIC; 8096 Y : out STD_LOGIC); 8097 end component; 8098 8099begin 8100 8101 -- Extrinsic delay buffers 8102 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 8103 generic map( tLH => twdi0_R, tHL => twdi0_F) 8104 port map( Input => i0, Output => connect(0)); 8105 8106 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 8107 generic map( tLH => twdi1_R, tHL => twdi1_F) 8108 port map( Input => i1, Output => connect(1)); 8109 8110 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 8111 generic map( tLH => twdi2_R, tHL => twdi2_F) 8112 port map( Input => i2, Output => connect(2)); 8113 8114 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 8115 generic map( tLH => twdi3_R, tHL => twdi3_F) 8116 port map( Input => i3, Output => connect(3)); 8117 8118 -- Intrinsic delay buffers 8119 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 8120 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 8121 port map( Input => connect(0), Output => prop_q(0)); 8122 8123 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 8124 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 8125 port map( Input => connect(1), Output => prop_q(1)); 8126 8127 U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 8128 generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) 8129 port map( Input => connect(2), Output => prop_q(2)); 8130 8131 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 8132 generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) 8133 port map( Input => connect(3), Output => prop_q(3)); 8134 8135 -- Netlist 8136 U9 : OR4MAC 8137 port map( I0 => prop_q(2), I1 => prop_q(3), I2 => prop_q(0), I3 => 8138 prop_q(1), Y => q); 8139 8140 8141end FTSM; 8142 8143configuration CFG_o4_x2_FTSM of o4_x2 is 8144 for FTSM 8145 end for; 8146end CFG_o4_x2_FTSM; 8147 8148 8149----- CELL o4_x4 ----- 8150library IEEE; 8151use IEEE.STD_LOGIC_1164.all; 8152library SYNOPSYS; 8153use SYNOPSYS.attributes.REAL_NAME; 8154 8155-- entity declaration -- 8156entity o4_x4 is 8157 generic( 8158 Timing_mesg: Boolean := True; 8159 Timing_xgen: Boolean := False; 8160 tpdi0_q_R : Time := 0.574 ns; 8161 tpdi0_q_F : Time := 0.638 ns; 8162 tpdi1_q_R : Time := 0.492 ns; 8163 tpdi1_q_F : Time := 0.650 ns; 8164 tpdi2_q_R : Time := 0.649 ns; 8165 tpdi2_q_F : Time := 0.611 ns; 8166 tpdi3_q_R : Time := 0.721 ns; 8167 tpdi3_q_F : Time := 0.536 ns; 8168 twdi0_R : Time := 0.000 ns; 8169 twdi0_F : Time := 0.000 ns; 8170 twdi1_R : Time := 0.000 ns; 8171 twdi1_F : Time := 0.000 ns; 8172 twdi2_R : Time := 0.000 ns; 8173 twdi2_F : Time := 0.000 ns; 8174 twdi3_R : Time := 0.000 ns; 8175 twdi3_F : Time := 0.000 ns); 8176 8177 port( 8178 i0 : in STD_LOGIC; 8179 i1 : in STD_LOGIC; 8180 i2 : in STD_LOGIC; 8181 i3 : in STD_LOGIC; 8182 q : out STD_LOGIC); 8183end o4_x4; 8184 8185-- architecture body -- 8186library IEEE_ASIC; 8187use IEEE.STD_LOGIC_MISC.all; 8188use SYNOPSYS.attributes.backplane; 8189use SYNOPSYS.attributes.PRIVATE; 8190use SYNOPSYS.attributes.ASIC_CELL; 8191use SYNOPSYS.attributes.PROPAGATE_VALUE; 8192 8193architecture FTSM of o4_x4 is 8194 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 8195 attribute PRIVATE of FTSM : architecture is TRUE; 8196 attribute ASIC_CELL of FTSM : architecture is TRUE; 8197 8198 -- Backannotation attributes 8199 attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; 8200 attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; 8201 attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; 8202 attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; 8203 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; 8204 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; 8205 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; 8206 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; 8207 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 8208 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 8209 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 8210 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 8211 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 8212 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 8213 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 8214 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 8215 8216 signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 8217 signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 8218 8219 component OR4MAC 8220 generic( 8221 tpdY_R : Time := 0 ns; 8222 tpdY_F : Time := 0 ns; 8223 strn : STRENGTH := strn_X01); 8224 port( 8225 I0 : in STD_LOGIC; 8226 I1 : in STD_LOGIC; 8227 I2 : in STD_LOGIC; 8228 I3 : in STD_LOGIC; 8229 Y : out STD_LOGIC); 8230 end component; 8231 8232begin 8233 8234 -- Extrinsic delay buffers 8235 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 8236 generic map( tLH => twdi0_R, tHL => twdi0_F) 8237 port map( Input => i0, Output => connect(0)); 8238 8239 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 8240 generic map( tLH => twdi1_R, tHL => twdi1_F) 8241 port map( Input => i1, Output => connect(1)); 8242 8243 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 8244 generic map( tLH => twdi2_R, tHL => twdi2_F) 8245 port map( Input => i2, Output => connect(2)); 8246 8247 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 8248 generic map( tLH => twdi3_R, tHL => twdi3_F) 8249 port map( Input => i3, Output => connect(3)); 8250 8251 -- Intrinsic delay buffers 8252 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 8253 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 8254 port map( Input => connect(0), Output => prop_q(0)); 8255 8256 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 8257 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 8258 port map( Input => connect(1), Output => prop_q(1)); 8259 8260 U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 8261 generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) 8262 port map( Input => connect(2), Output => prop_q(2)); 8263 8264 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 8265 generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) 8266 port map( Input => connect(3), Output => prop_q(3)); 8267 8268 -- Netlist 8269 U9 : OR4MAC 8270 port map( I0 => prop_q(2), I1 => prop_q(3), I2 => prop_q(0), I3 => 8271 prop_q(1), Y => q); 8272 8273 8274end FTSM; 8275 8276configuration CFG_o4_x4_FTSM of o4_x4 is 8277 for FTSM 8278 end for; 8279end CFG_o4_x4_FTSM; 8280 8281 8282----- CELL oa2a2a2a24_x2 ----- 8283library IEEE; 8284use IEEE.STD_LOGIC_1164.all; 8285library SYNOPSYS; 8286use SYNOPSYS.attributes.REAL_NAME; 8287 8288-- entity declaration -- 8289entity oa2a2a2a24_x2 is 8290 generic( 8291 Timing_mesg: Boolean := True; 8292 Timing_xgen: Boolean := False; 8293 tpdi0_q_R : Time := 0.780 ns; 8294 tpdi0_q_F : Time := 0.797 ns; 8295 tpdi1_q_R : Time := 0.909 ns; 8296 tpdi1_q_F : Time := 0.753 ns; 8297 tpdi2_q_R : Time := 0.682 ns; 8298 tpdi2_q_F : Time := 0.856 ns; 8299 tpdi3_q_R : Time := 0.803 ns; 8300 tpdi3_q_F : Time := 0.810 ns; 8301 tpdi4_q_R : Time := 0.565 ns; 8302 tpdi4_q_F : Time := 0.813 ns; 8303 tpdi5_q_R : Time := 0.467 ns; 8304 tpdi5_q_F : Time := 0.861 ns; 8305 tpdi6_q_R : Time := 0.426 ns; 8306 tpdi6_q_F : Time := 0.748 ns; 8307 tpdi7_q_R : Time := 0.346 ns; 8308 tpdi7_q_F : Time := 0.800 ns; 8309 twdi0_R : Time := 0.000 ns; 8310 twdi0_F : Time := 0.000 ns; 8311 twdi1_R : Time := 0.000 ns; 8312 twdi1_F : Time := 0.000 ns; 8313 twdi2_R : Time := 0.000 ns; 8314 twdi2_F : Time := 0.000 ns; 8315 twdi3_R : Time := 0.000 ns; 8316 twdi3_F : Time := 0.000 ns; 8317 twdi4_R : Time := 0.000 ns; 8318 twdi4_F : Time := 0.000 ns; 8319 twdi5_R : Time := 0.000 ns; 8320 twdi5_F : Time := 0.000 ns; 8321 twdi6_R : Time := 0.000 ns; 8322 twdi6_F : Time := 0.000 ns; 8323 twdi7_R : Time := 0.000 ns; 8324 twdi7_F : Time := 0.000 ns); 8325 8326 port( 8327 i0 : in STD_LOGIC; 8328 i1 : in STD_LOGIC; 8329 i2 : in STD_LOGIC; 8330 i3 : in STD_LOGIC; 8331 i4 : in STD_LOGIC; 8332 i5 : in STD_LOGIC; 8333 i6 : in STD_LOGIC; 8334 i7 : in STD_LOGIC; 8335 q : out STD_LOGIC); 8336end oa2a2a2a24_x2; 8337 8338-- architecture body -- 8339library IEEE_ASIC; 8340use IEEE.STD_LOGIC_MISC.all; 8341use SYNOPSYS.attributes.backplane; 8342use SYNOPSYS.attributes.PRIVATE; 8343use SYNOPSYS.attributes.ASIC_CELL; 8344use SYNOPSYS.attributes.PROPAGATE_VALUE; 8345 8346architecture FTSM of oa2a2a2a24_x2 is 8347 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 8348 attribute PRIVATE of FTSM : architecture is TRUE; 8349 attribute ASIC_CELL of FTSM : architecture is TRUE; 8350 8351 -- Backannotation attributes 8352 attribute PROPAGATE_VALUE of tpdi7_q_R: constant is "U16/tLH"; 8353 attribute PROPAGATE_VALUE of tpdi7_q_F: constant is "U16/tHL"; 8354 attribute PROPAGATE_VALUE of tpdi6_q_R: constant is "U15/tLH"; 8355 attribute PROPAGATE_VALUE of tpdi6_q_F: constant is "U15/tHL"; 8356 attribute PROPAGATE_VALUE of tpdi5_q_R: constant is "U14/tLH"; 8357 attribute PROPAGATE_VALUE of tpdi5_q_F: constant is "U14/tHL"; 8358 attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U13/tLH"; 8359 attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U13/tHL"; 8360 attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U12/tLH"; 8361 attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U12/tHL"; 8362 attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U11/tLH"; 8363 attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U11/tHL"; 8364 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U10/tLH"; 8365 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U10/tHL"; 8366 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U9/tLH"; 8367 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U9/tHL"; 8368 attribute PROPAGATE_VALUE of twdi7_F: constant is "U8/tHL"; 8369 attribute PROPAGATE_VALUE of twdi7_R: constant is "U8/tLH"; 8370 attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; 8371 attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; 8372 attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; 8373 attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; 8374 attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; 8375 attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; 8376 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 8377 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 8378 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 8379 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 8380 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 8381 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 8382 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 8383 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 8384 8385 signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); 8386 signal prop_q : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); 8387 signal n1, n2, n3, n4 : STD_LOGIC; 8388 8389 component NAND4MAC 8390 generic( 8391 tpdY_R : Time := 0 ns; 8392 tpdY_F : Time := 0 ns; 8393 strn : STRENGTH := strn_X01); 8394 port( 8395 I0 : in STD_LOGIC; 8396 I1 : in STD_LOGIC; 8397 I2 : in STD_LOGIC; 8398 I3 : in STD_LOGIC; 8399 Y : out STD_LOGIC); 8400 end component; 8401 8402 component NAND2MAC 8403 generic( 8404 tpdY_R : Time := 0 ns; 8405 tpdY_F : Time := 0 ns; 8406 strn : STRENGTH := strn_X01); 8407 port( 8408 I0 : in STD_LOGIC; 8409 I1 : in STD_LOGIC; 8410 Y : out STD_LOGIC); 8411 end component; 8412 8413begin 8414 8415 -- Extrinsic delay buffers 8416 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 8417 generic map( tLH => twdi0_R, tHL => twdi0_F) 8418 port map( Input => i0, Output => connect(0)); 8419 8420 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 8421 generic map( tLH => twdi1_R, tHL => twdi1_F) 8422 port map( Input => i1, Output => connect(1)); 8423 8424 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 8425 generic map( tLH => twdi2_R, tHL => twdi2_F) 8426 port map( Input => i2, Output => connect(2)); 8427 8428 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 8429 generic map( tLH => twdi3_R, tHL => twdi3_F) 8430 port map( Input => i3, Output => connect(3)); 8431 8432 U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 8433 generic map( tLH => twdi4_R, tHL => twdi4_F) 8434 port map( Input => i4, Output => connect(4)); 8435 8436 U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 8437 generic map( tLH => twdi5_R, tHL => twdi5_F) 8438 port map( Input => i5, Output => connect(5)); 8439 8440 U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 8441 generic map( tLH => twdi6_R, tHL => twdi6_F) 8442 port map( Input => i6, Output => connect(6)); 8443 8444 U8 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 8445 generic map( tLH => twdi7_R, tHL => twdi7_F) 8446 port map( Input => i7, Output => connect(7)); 8447 8448 -- Intrinsic delay buffers 8449 U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 8450 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 8451 port map( Input => connect(0), Output => prop_q(0)); 8452 8453 U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 8454 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 8455 port map( Input => connect(1), Output => prop_q(1)); 8456 8457 U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 8458 generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) 8459 port map( Input => connect(2), Output => prop_q(2)); 8460 8461 U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 8462 generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) 8463 port map( Input => connect(3), Output => prop_q(3)); 8464 8465 U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 8466 generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) 8467 port map( Input => connect(4), Output => prop_q(4)); 8468 8469 U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 8470 generic map( tLH => tpdi5_q_R, tHL => tpdi5_q_F) 8471 port map( Input => connect(5), Output => prop_q(5)); 8472 8473 U15 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 8474 generic map( tLH => tpdi6_q_R, tHL => tpdi6_q_F) 8475 port map( Input => connect(6), Output => prop_q(6)); 8476 8477 U16 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 8478 generic map( tLH => tpdi7_q_R, tHL => tpdi7_q_F) 8479 port map( Input => connect(7), Output => prop_q(7)); 8480 8481 -- Netlist 8482 U17 : NAND4MAC 8483 port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => q); 8484 8485 U18 : NAND2MAC 8486 port map( I0 => prop_q(6), I1 => prop_q(7), Y => n4); 8487 8488 U19 : NAND2MAC 8489 port map( I0 => prop_q(4), I1 => prop_q(5), Y => n3); 8490 8491 U20 : NAND2MAC 8492 port map( I0 => prop_q(2), I1 => prop_q(3), Y => n2); 8493 8494 U21 : NAND2MAC 8495 port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); 8496 8497 8498end FTSM; 8499 8500configuration CFG_oa2a2a2a24_x2_FTSM of oa2a2a2a24_x2 is 8501 for FTSM 8502 end for; 8503end CFG_oa2a2a2a24_x2_FTSM; 8504 8505 8506----- CELL oa2a2a2a24_x4 ----- 8507library IEEE; 8508use IEEE.STD_LOGIC_1164.all; 8509library SYNOPSYS; 8510use SYNOPSYS.attributes.REAL_NAME; 8511 8512-- entity declaration -- 8513entity oa2a2a2a24_x4 is 8514 generic( 8515 Timing_mesg: Boolean := True; 8516 Timing_xgen: Boolean := False; 8517 tpdi0_q_R : Time := 0.823 ns; 8518 tpdi0_q_F : Time := 0.879 ns; 8519 tpdi1_q_R : Time := 0.955 ns; 8520 tpdi1_q_F : Time := 0.835 ns; 8521 tpdi2_q_R : Time := 0.726 ns; 8522 tpdi2_q_F : Time := 0.940 ns; 8523 tpdi3_q_R : Time := 0.851 ns; 8524 tpdi3_q_F : Time := 0.895 ns; 8525 tpdi4_q_R : Time := 0.619 ns; 8526 tpdi4_q_F : Time := 0.902 ns; 8527 tpdi5_q_R : Time := 0.515 ns; 8528 tpdi5_q_F : Time := 0.949 ns; 8529 tpdi6_q_R : Time := 0.487 ns; 8530 tpdi6_q_F : Time := 0.845 ns; 8531 tpdi7_q_R : Time := 0.399 ns; 8532 tpdi7_q_F : Time := 0.895 ns; 8533 twdi0_R : Time := 0.000 ns; 8534 twdi0_F : Time := 0.000 ns; 8535 twdi1_R : Time := 0.000 ns; 8536 twdi1_F : Time := 0.000 ns; 8537 twdi2_R : Time := 0.000 ns; 8538 twdi2_F : Time := 0.000 ns; 8539 twdi3_R : Time := 0.000 ns; 8540 twdi3_F : Time := 0.000 ns; 8541 twdi4_R : Time := 0.000 ns; 8542 twdi4_F : Time := 0.000 ns; 8543 twdi5_R : Time := 0.000 ns; 8544 twdi5_F : Time := 0.000 ns; 8545 twdi6_R : Time := 0.000 ns; 8546 twdi6_F : Time := 0.000 ns; 8547 twdi7_R : Time := 0.000 ns; 8548 twdi7_F : Time := 0.000 ns); 8549 8550 port( 8551 i0 : in STD_LOGIC; 8552 i1 : in STD_LOGIC; 8553 i2 : in STD_LOGIC; 8554 i3 : in STD_LOGIC; 8555 i4 : in STD_LOGIC; 8556 i5 : in STD_LOGIC; 8557 i6 : in STD_LOGIC; 8558 i7 : in STD_LOGIC; 8559 q : out STD_LOGIC); 8560end oa2a2a2a24_x4; 8561 8562-- architecture body -- 8563library IEEE_ASIC; 8564use IEEE.STD_LOGIC_MISC.all; 8565use SYNOPSYS.attributes.backplane; 8566use SYNOPSYS.attributes.PRIVATE; 8567use SYNOPSYS.attributes.ASIC_CELL; 8568use SYNOPSYS.attributes.PROPAGATE_VALUE; 8569 8570architecture FTSM of oa2a2a2a24_x4 is 8571 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 8572 attribute PRIVATE of FTSM : architecture is TRUE; 8573 attribute ASIC_CELL of FTSM : architecture is TRUE; 8574 8575 -- Backannotation attributes 8576 attribute PROPAGATE_VALUE of tpdi7_q_R: constant is "U16/tLH"; 8577 attribute PROPAGATE_VALUE of tpdi7_q_F: constant is "U16/tHL"; 8578 attribute PROPAGATE_VALUE of tpdi6_q_R: constant is "U15/tLH"; 8579 attribute PROPAGATE_VALUE of tpdi6_q_F: constant is "U15/tHL"; 8580 attribute PROPAGATE_VALUE of tpdi5_q_R: constant is "U14/tLH"; 8581 attribute PROPAGATE_VALUE of tpdi5_q_F: constant is "U14/tHL"; 8582 attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U13/tLH"; 8583 attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U13/tHL"; 8584 attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U12/tLH"; 8585 attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U12/tHL"; 8586 attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U11/tLH"; 8587 attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U11/tHL"; 8588 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U10/tLH"; 8589 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U10/tHL"; 8590 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U9/tLH"; 8591 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U9/tHL"; 8592 attribute PROPAGATE_VALUE of twdi7_F: constant is "U8/tHL"; 8593 attribute PROPAGATE_VALUE of twdi7_R: constant is "U8/tLH"; 8594 attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; 8595 attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; 8596 attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; 8597 attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; 8598 attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; 8599 attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; 8600 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 8601 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 8602 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 8603 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 8604 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 8605 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 8606 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 8607 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 8608 8609 signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); 8610 signal prop_q : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); 8611 signal n1, n2, n3, n4 : STD_LOGIC; 8612 8613 component NAND4MAC 8614 generic( 8615 tpdY_R : Time := 0 ns; 8616 tpdY_F : Time := 0 ns; 8617 strn : STRENGTH := strn_X01); 8618 port( 8619 I0 : in STD_LOGIC; 8620 I1 : in STD_LOGIC; 8621 I2 : in STD_LOGIC; 8622 I3 : in STD_LOGIC; 8623 Y : out STD_LOGIC); 8624 end component; 8625 8626 component NAND2MAC 8627 generic( 8628 tpdY_R : Time := 0 ns; 8629 tpdY_F : Time := 0 ns; 8630 strn : STRENGTH := strn_X01); 8631 port( 8632 I0 : in STD_LOGIC; 8633 I1 : in STD_LOGIC; 8634 Y : out STD_LOGIC); 8635 end component; 8636 8637begin 8638 8639 -- Extrinsic delay buffers 8640 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 8641 generic map( tLH => twdi0_R, tHL => twdi0_F) 8642 port map( Input => i0, Output => connect(0)); 8643 8644 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 8645 generic map( tLH => twdi1_R, tHL => twdi1_F) 8646 port map( Input => i1, Output => connect(1)); 8647 8648 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 8649 generic map( tLH => twdi2_R, tHL => twdi2_F) 8650 port map( Input => i2, Output => connect(2)); 8651 8652 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 8653 generic map( tLH => twdi3_R, tHL => twdi3_F) 8654 port map( Input => i3, Output => connect(3)); 8655 8656 U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 8657 generic map( tLH => twdi4_R, tHL => twdi4_F) 8658 port map( Input => i4, Output => connect(4)); 8659 8660 U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 8661 generic map( tLH => twdi5_R, tHL => twdi5_F) 8662 port map( Input => i5, Output => connect(5)); 8663 8664 U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 8665 generic map( tLH => twdi6_R, tHL => twdi6_F) 8666 port map( Input => i6, Output => connect(6)); 8667 8668 U8 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 8669 generic map( tLH => twdi7_R, tHL => twdi7_F) 8670 port map( Input => i7, Output => connect(7)); 8671 8672 -- Intrinsic delay buffers 8673 U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 8674 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 8675 port map( Input => connect(0), Output => prop_q(0)); 8676 8677 U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 8678 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 8679 port map( Input => connect(1), Output => prop_q(1)); 8680 8681 U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 8682 generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) 8683 port map( Input => connect(2), Output => prop_q(2)); 8684 8685 U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 8686 generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) 8687 port map( Input => connect(3), Output => prop_q(3)); 8688 8689 U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 8690 generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) 8691 port map( Input => connect(4), Output => prop_q(4)); 8692 8693 U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 8694 generic map( tLH => tpdi5_q_R, tHL => tpdi5_q_F) 8695 port map( Input => connect(5), Output => prop_q(5)); 8696 8697 U15 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 8698 generic map( tLH => tpdi6_q_R, tHL => tpdi6_q_F) 8699 port map( Input => connect(6), Output => prop_q(6)); 8700 8701 U16 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 8702 generic map( tLH => tpdi7_q_R, tHL => tpdi7_q_F) 8703 port map( Input => connect(7), Output => prop_q(7)); 8704 8705 -- Netlist 8706 U17 : NAND4MAC 8707 port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => q); 8708 8709 U18 : NAND2MAC 8710 port map( I0 => prop_q(6), I1 => prop_q(7), Y => n4); 8711 8712 U19 : NAND2MAC 8713 port map( I0 => prop_q(4), I1 => prop_q(5), Y => n3); 8714 8715 U20 : NAND2MAC 8716 port map( I0 => prop_q(2), I1 => prop_q(3), Y => n2); 8717 8718 U21 : NAND2MAC 8719 port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); 8720 8721 8722end FTSM; 8723 8724configuration CFG_oa2a2a2a24_x4_FTSM of oa2a2a2a24_x4 is 8725 for FTSM 8726 end for; 8727end CFG_oa2a2a2a24_x4_FTSM; 8728 8729 8730----- CELL oa2a2a23_x2 ----- 8731library IEEE; 8732use IEEE.STD_LOGIC_1164.all; 8733library SYNOPSYS; 8734use SYNOPSYS.attributes.REAL_NAME; 8735 8736-- entity declaration -- 8737entity oa2a2a23_x2 is 8738 generic( 8739 Timing_mesg: Boolean := True; 8740 Timing_xgen: Boolean := False; 8741 tpdi0_q_R : Time := 0.653 ns; 8742 tpdi0_q_F : Time := 0.578 ns; 8743 tpdi1_q_R : Time := 0.775 ns; 8744 tpdi1_q_F : Time := 0.542 ns; 8745 tpdi2_q_R : Time := 0.441 ns; 8746 tpdi2_q_F : Time := 0.639 ns; 8747 tpdi3_q_R : Time := 0.540 ns; 8748 tpdi3_q_F : Time := 0.600 ns; 8749 tpdi4_q_R : Time := 0.402 ns; 8750 tpdi4_q_F : Time := 0.591 ns; 8751 tpdi5_q_R : Time := 0.321 ns; 8752 tpdi5_q_F : Time := 0.636 ns; 8753 twdi0_R : Time := 0.000 ns; 8754 twdi0_F : Time := 0.000 ns; 8755 twdi1_R : Time := 0.000 ns; 8756 twdi1_F : Time := 0.000 ns; 8757 twdi2_R : Time := 0.000 ns; 8758 twdi2_F : Time := 0.000 ns; 8759 twdi3_R : Time := 0.000 ns; 8760 twdi3_F : Time := 0.000 ns; 8761 twdi4_R : Time := 0.000 ns; 8762 twdi4_F : Time := 0.000 ns; 8763 twdi5_R : Time := 0.000 ns; 8764 twdi5_F : Time := 0.000 ns); 8765 8766 port( 8767 i0 : in STD_LOGIC; 8768 i1 : in STD_LOGIC; 8769 i2 : in STD_LOGIC; 8770 i3 : in STD_LOGIC; 8771 i4 : in STD_LOGIC; 8772 i5 : in STD_LOGIC; 8773 q : out STD_LOGIC); 8774end oa2a2a23_x2; 8775 8776-- architecture body -- 8777library IEEE_ASIC; 8778use IEEE.STD_LOGIC_MISC.all; 8779use SYNOPSYS.attributes.backplane; 8780use SYNOPSYS.attributes.PRIVATE; 8781use SYNOPSYS.attributes.ASIC_CELL; 8782use SYNOPSYS.attributes.PROPAGATE_VALUE; 8783 8784architecture FTSM of oa2a2a23_x2 is 8785 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 8786 attribute PRIVATE of FTSM : architecture is TRUE; 8787 attribute ASIC_CELL of FTSM : architecture is TRUE; 8788 8789 -- Backannotation attributes 8790 attribute PROPAGATE_VALUE of tpdi5_q_R: constant is "U12/tLH"; 8791 attribute PROPAGATE_VALUE of tpdi5_q_F: constant is "U12/tHL"; 8792 attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U11/tLH"; 8793 attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U11/tHL"; 8794 attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U10/tLH"; 8795 attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U10/tHL"; 8796 attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U9/tLH"; 8797 attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U9/tHL"; 8798 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U8/tLH"; 8799 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U8/tHL"; 8800 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U7/tLH"; 8801 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U7/tHL"; 8802 attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; 8803 attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; 8804 attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; 8805 attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; 8806 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 8807 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 8808 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 8809 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 8810 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 8811 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 8812 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 8813 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 8814 8815 signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); 8816 signal prop_q : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); 8817 signal n1, n2, n3 : STD_LOGIC; 8818 8819 component NAND3MAC 8820 generic( 8821 tpdY_R : Time := 0 ns; 8822 tpdY_F : Time := 0 ns; 8823 strn : STRENGTH := strn_X01); 8824 port( 8825 I0 : in STD_LOGIC; 8826 I1 : in STD_LOGIC; 8827 I2 : in STD_LOGIC; 8828 Y : out STD_LOGIC); 8829 end component; 8830 8831 component NAND2MAC 8832 generic( 8833 tpdY_R : Time := 0 ns; 8834 tpdY_F : Time := 0 ns; 8835 strn : STRENGTH := strn_X01); 8836 port( 8837 I0 : in STD_LOGIC; 8838 I1 : in STD_LOGIC; 8839 Y : out STD_LOGIC); 8840 end component; 8841 8842begin 8843 8844 -- Extrinsic delay buffers 8845 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 8846 generic map( tLH => twdi0_R, tHL => twdi0_F) 8847 port map( Input => i0, Output => connect(0)); 8848 8849 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 8850 generic map( tLH => twdi1_R, tHL => twdi1_F) 8851 port map( Input => i1, Output => connect(1)); 8852 8853 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 8854 generic map( tLH => twdi2_R, tHL => twdi2_F) 8855 port map( Input => i2, Output => connect(2)); 8856 8857 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 8858 generic map( tLH => twdi3_R, tHL => twdi3_F) 8859 port map( Input => i3, Output => connect(3)); 8860 8861 U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 8862 generic map( tLH => twdi4_R, tHL => twdi4_F) 8863 port map( Input => i4, Output => connect(4)); 8864 8865 U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 8866 generic map( tLH => twdi5_R, tHL => twdi5_F) 8867 port map( Input => i5, Output => connect(5)); 8868 8869 -- Intrinsic delay buffers 8870 U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 8871 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 8872 port map( Input => connect(0), Output => prop_q(0)); 8873 8874 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 8875 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 8876 port map( Input => connect(1), Output => prop_q(1)); 8877 8878 U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 8879 generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) 8880 port map( Input => connect(2), Output => prop_q(2)); 8881 8882 U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 8883 generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) 8884 port map( Input => connect(3), Output => prop_q(3)); 8885 8886 U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 8887 generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) 8888 port map( Input => connect(4), Output => prop_q(4)); 8889 8890 U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 8891 generic map( tLH => tpdi5_q_R, tHL => tpdi5_q_F) 8892 port map( Input => connect(5), Output => prop_q(5)); 8893 8894 -- Netlist 8895 U13 : NAND3MAC 8896 port map( I0 => n1, I1 => n2, I2 => n3, Y => q); 8897 8898 U14 : NAND2MAC 8899 port map( I0 => prop_q(4), I1 => prop_q(5), Y => n2); 8900 8901 U15 : NAND2MAC 8902 port map( I0 => prop_q(2), I1 => prop_q(3), Y => n1); 8903 8904 U16 : NAND2MAC 8905 port map( I0 => prop_q(0), I1 => prop_q(1), Y => n3); 8906 8907 8908end FTSM; 8909 8910configuration CFG_oa2a2a23_x2_FTSM of oa2a2a23_x2 is 8911 for FTSM 8912 end for; 8913end CFG_oa2a2a23_x2_FTSM; 8914 8915 8916----- CELL oa2a2a23_x4 ----- 8917library IEEE; 8918use IEEE.STD_LOGIC_1164.all; 8919library SYNOPSYS; 8920use SYNOPSYS.attributes.REAL_NAME; 8921 8922-- entity declaration -- 8923entity oa2a2a23_x4 is 8924 generic( 8925 Timing_mesg: Boolean := True; 8926 Timing_xgen: Boolean := False; 8927 tpdi0_q_R : Time := 0.699 ns; 8928 tpdi0_q_F : Time := 0.648 ns; 8929 tpdi1_q_R : Time := 0.822 ns; 8930 tpdi1_q_F : Time := 0.613 ns; 8931 tpdi2_q_R : Time := 0.493 ns; 8932 tpdi2_q_F : Time := 0.715 ns; 8933 tpdi3_q_R : Time := 0.594 ns; 8934 tpdi3_q_F : Time := 0.677 ns; 8935 tpdi4_q_R : Time := 0.464 ns; 8936 tpdi4_q_F : Time := 0.673 ns; 8937 tpdi5_q_R : Time := 0.379 ns; 8938 tpdi5_q_F : Time := 0.714 ns; 8939 twdi0_R : Time := 0.000 ns; 8940 twdi0_F : Time := 0.000 ns; 8941 twdi1_R : Time := 0.000 ns; 8942 twdi1_F : Time := 0.000 ns; 8943 twdi2_R : Time := 0.000 ns; 8944 twdi2_F : Time := 0.000 ns; 8945 twdi3_R : Time := 0.000 ns; 8946 twdi3_F : Time := 0.000 ns; 8947 twdi4_R : Time := 0.000 ns; 8948 twdi4_F : Time := 0.000 ns; 8949 twdi5_R : Time := 0.000 ns; 8950 twdi5_F : Time := 0.000 ns); 8951 8952 port( 8953 i0 : in STD_LOGIC; 8954 i1 : in STD_LOGIC; 8955 i2 : in STD_LOGIC; 8956 i3 : in STD_LOGIC; 8957 i4 : in STD_LOGIC; 8958 i5 : in STD_LOGIC; 8959 q : out STD_LOGIC); 8960end oa2a2a23_x4; 8961 8962-- architecture body -- 8963library IEEE_ASIC; 8964use IEEE.STD_LOGIC_MISC.all; 8965use SYNOPSYS.attributes.backplane; 8966use SYNOPSYS.attributes.PRIVATE; 8967use SYNOPSYS.attributes.ASIC_CELL; 8968use SYNOPSYS.attributes.PROPAGATE_VALUE; 8969 8970architecture FTSM of oa2a2a23_x4 is 8971 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 8972 attribute PRIVATE of FTSM : architecture is TRUE; 8973 attribute ASIC_CELL of FTSM : architecture is TRUE; 8974 8975 -- Backannotation attributes 8976 attribute PROPAGATE_VALUE of tpdi5_q_R: constant is "U12/tLH"; 8977 attribute PROPAGATE_VALUE of tpdi5_q_F: constant is "U12/tHL"; 8978 attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U11/tLH"; 8979 attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U11/tHL"; 8980 attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U10/tLH"; 8981 attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U10/tHL"; 8982 attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U9/tLH"; 8983 attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U9/tHL"; 8984 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U8/tLH"; 8985 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U8/tHL"; 8986 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U7/tLH"; 8987 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U7/tHL"; 8988 attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; 8989 attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; 8990 attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; 8991 attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; 8992 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 8993 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 8994 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 8995 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 8996 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 8997 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 8998 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 8999 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 9000 9001 signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); 9002 signal prop_q : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); 9003 signal n1, n2, n3 : STD_LOGIC; 9004 9005 component NAND3MAC 9006 generic( 9007 tpdY_R : Time := 0 ns; 9008 tpdY_F : Time := 0 ns; 9009 strn : STRENGTH := strn_X01); 9010 port( 9011 I0 : in STD_LOGIC; 9012 I1 : in STD_LOGIC; 9013 I2 : in STD_LOGIC; 9014 Y : out STD_LOGIC); 9015 end component; 9016 9017 component NAND2MAC 9018 generic( 9019 tpdY_R : Time := 0 ns; 9020 tpdY_F : Time := 0 ns; 9021 strn : STRENGTH := strn_X01); 9022 port( 9023 I0 : in STD_LOGIC; 9024 I1 : in STD_LOGIC; 9025 Y : out STD_LOGIC); 9026 end component; 9027 9028begin 9029 9030 -- Extrinsic delay buffers 9031 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9032 generic map( tLH => twdi0_R, tHL => twdi0_F) 9033 port map( Input => i0, Output => connect(0)); 9034 9035 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9036 generic map( tLH => twdi1_R, tHL => twdi1_F) 9037 port map( Input => i1, Output => connect(1)); 9038 9039 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9040 generic map( tLH => twdi2_R, tHL => twdi2_F) 9041 port map( Input => i2, Output => connect(2)); 9042 9043 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9044 generic map( tLH => twdi3_R, tHL => twdi3_F) 9045 port map( Input => i3, Output => connect(3)); 9046 9047 U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9048 generic map( tLH => twdi4_R, tHL => twdi4_F) 9049 port map( Input => i4, Output => connect(4)); 9050 9051 U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9052 generic map( tLH => twdi5_R, tHL => twdi5_F) 9053 port map( Input => i5, Output => connect(5)); 9054 9055 -- Intrinsic delay buffers 9056 U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9057 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 9058 port map( Input => connect(0), Output => prop_q(0)); 9059 9060 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9061 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 9062 port map( Input => connect(1), Output => prop_q(1)); 9063 9064 U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9065 generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) 9066 port map( Input => connect(2), Output => prop_q(2)); 9067 9068 U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9069 generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) 9070 port map( Input => connect(3), Output => prop_q(3)); 9071 9072 U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9073 generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) 9074 port map( Input => connect(4), Output => prop_q(4)); 9075 9076 U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9077 generic map( tLH => tpdi5_q_R, tHL => tpdi5_q_F) 9078 port map( Input => connect(5), Output => prop_q(5)); 9079 9080 -- Netlist 9081 U13 : NAND3MAC 9082 port map( I0 => n1, I1 => n2, I2 => n3, Y => q); 9083 9084 U14 : NAND2MAC 9085 port map( I0 => prop_q(4), I1 => prop_q(5), Y => n2); 9086 9087 U15 : NAND2MAC 9088 port map( I0 => prop_q(2), I1 => prop_q(3), Y => n1); 9089 9090 U16 : NAND2MAC 9091 port map( I0 => prop_q(0), I1 => prop_q(1), Y => n3); 9092 9093 9094end FTSM; 9095 9096configuration CFG_oa2a2a23_x4_FTSM of oa2a2a23_x4 is 9097 for FTSM 9098 end for; 9099end CFG_oa2a2a23_x4_FTSM; 9100 9101 9102----- CELL oa2a22_x2 ----- 9103library IEEE; 9104use IEEE.STD_LOGIC_1164.all; 9105library SYNOPSYS; 9106use SYNOPSYS.attributes.REAL_NAME; 9107 9108-- entity declaration -- 9109entity oa2a22_x2 is 9110 generic( 9111 Timing_mesg: Boolean := True; 9112 Timing_xgen: Boolean := False; 9113 tpdi0_q_R : Time := 0.403 ns; 9114 tpdi0_q_F : Time := 0.564 ns; 9115 tpdi1_q_R : Time := 0.495 ns; 9116 tpdi1_q_F : Time := 0.534 ns; 9117 tpdi2_q_R : Time := 0.646 ns; 9118 tpdi2_q_F : Time := 0.487 ns; 9119 tpdi3_q_R : Time := 0.537 ns; 9120 tpdi3_q_F : Time := 0.512 ns; 9121 twdi0_R : Time := 0.000 ns; 9122 twdi0_F : Time := 0.000 ns; 9123 twdi1_R : Time := 0.000 ns; 9124 twdi1_F : Time := 0.000 ns; 9125 twdi2_R : Time := 0.000 ns; 9126 twdi2_F : Time := 0.000 ns; 9127 twdi3_R : Time := 0.000 ns; 9128 twdi3_F : Time := 0.000 ns); 9129 9130 port( 9131 i0 : in STD_LOGIC; 9132 i1 : in STD_LOGIC; 9133 i2 : in STD_LOGIC; 9134 i3 : in STD_LOGIC; 9135 q : out STD_LOGIC); 9136end oa2a22_x2; 9137 9138-- architecture body -- 9139library IEEE_ASIC; 9140use IEEE.STD_LOGIC_MISC.all; 9141use SYNOPSYS.attributes.backplane; 9142use SYNOPSYS.attributes.PRIVATE; 9143use SYNOPSYS.attributes.ASIC_CELL; 9144use SYNOPSYS.attributes.PROPAGATE_VALUE; 9145 9146architecture FTSM of oa2a22_x2 is 9147 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 9148 attribute PRIVATE of FTSM : architecture is TRUE; 9149 attribute ASIC_CELL of FTSM : architecture is TRUE; 9150 9151 -- Backannotation attributes 9152 attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; 9153 attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; 9154 attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; 9155 attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; 9156 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; 9157 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; 9158 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; 9159 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; 9160 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 9161 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 9162 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 9163 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 9164 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 9165 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 9166 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 9167 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 9168 9169 signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 9170 signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 9171 signal n1, n2 : STD_LOGIC; 9172 9173 component NAND2MAC 9174 generic( 9175 tpdY_R : Time := 0 ns; 9176 tpdY_F : Time := 0 ns; 9177 strn : STRENGTH := strn_X01); 9178 port( 9179 I0 : in STD_LOGIC; 9180 I1 : in STD_LOGIC; 9181 Y : out STD_LOGIC); 9182 end component; 9183 9184begin 9185 9186 -- Extrinsic delay buffers 9187 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9188 generic map( tLH => twdi0_R, tHL => twdi0_F) 9189 port map( Input => i0, Output => connect(0)); 9190 9191 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9192 generic map( tLH => twdi1_R, tHL => twdi1_F) 9193 port map( Input => i1, Output => connect(1)); 9194 9195 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9196 generic map( tLH => twdi2_R, tHL => twdi2_F) 9197 port map( Input => i2, Output => connect(2)); 9198 9199 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9200 generic map( tLH => twdi3_R, tHL => twdi3_F) 9201 port map( Input => i3, Output => connect(3)); 9202 9203 -- Intrinsic delay buffers 9204 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9205 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 9206 port map( Input => connect(0), Output => prop_q(0)); 9207 9208 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9209 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 9210 port map( Input => connect(1), Output => prop_q(1)); 9211 9212 U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9213 generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) 9214 port map( Input => connect(2), Output => prop_q(2)); 9215 9216 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9217 generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) 9218 port map( Input => connect(3), Output => prop_q(3)); 9219 9220 -- Netlist 9221 U9 : NAND2MAC 9222 port map( I0 => n1, I1 => n2, Y => q); 9223 9224 U10 : NAND2MAC 9225 port map( I0 => prop_q(2), I1 => prop_q(3), Y => n2); 9226 9227 U11 : NAND2MAC 9228 port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); 9229 9230 9231end FTSM; 9232 9233configuration CFG_oa2a22_x2_FTSM of oa2a22_x2 is 9234 for FTSM 9235 end for; 9236end CFG_oa2a22_x2_FTSM; 9237 9238 9239----- CELL oa2a22_x4 ----- 9240library IEEE; 9241use IEEE.STD_LOGIC_1164.all; 9242library SYNOPSYS; 9243use SYNOPSYS.attributes.REAL_NAME; 9244 9245-- entity declaration -- 9246entity oa2a22_x4 is 9247 generic( 9248 Timing_mesg: Boolean := True; 9249 Timing_xgen: Boolean := False; 9250 tpdi0_q_R : Time := 0.519 ns; 9251 tpdi0_q_F : Time := 0.696 ns; 9252 tpdi1_q_R : Time := 0.624 ns; 9253 tpdi1_q_F : Time := 0.669 ns; 9254 tpdi2_q_R : Time := 0.763 ns; 9255 tpdi2_q_F : Time := 0.596 ns; 9256 tpdi3_q_R : Time := 0.644 ns; 9257 tpdi3_q_F : Time := 0.619 ns; 9258 twdi0_R : Time := 0.000 ns; 9259 twdi0_F : Time := 0.000 ns; 9260 twdi1_R : Time := 0.000 ns; 9261 twdi1_F : Time := 0.000 ns; 9262 twdi2_R : Time := 0.000 ns; 9263 twdi2_F : Time := 0.000 ns; 9264 twdi3_R : Time := 0.000 ns; 9265 twdi3_F : Time := 0.000 ns); 9266 9267 port( 9268 i0 : in STD_LOGIC; 9269 i1 : in STD_LOGIC; 9270 i2 : in STD_LOGIC; 9271 i3 : in STD_LOGIC; 9272 q : out STD_LOGIC); 9273end oa2a22_x4; 9274 9275-- architecture body -- 9276library IEEE_ASIC; 9277use IEEE.STD_LOGIC_MISC.all; 9278use SYNOPSYS.attributes.backplane; 9279use SYNOPSYS.attributes.PRIVATE; 9280use SYNOPSYS.attributes.ASIC_CELL; 9281use SYNOPSYS.attributes.PROPAGATE_VALUE; 9282 9283architecture FTSM of oa2a22_x4 is 9284 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 9285 attribute PRIVATE of FTSM : architecture is TRUE; 9286 attribute ASIC_CELL of FTSM : architecture is TRUE; 9287 9288 -- Backannotation attributes 9289 attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; 9290 attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; 9291 attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; 9292 attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; 9293 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; 9294 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; 9295 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; 9296 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; 9297 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 9298 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 9299 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 9300 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 9301 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 9302 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 9303 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 9304 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 9305 9306 signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 9307 signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 9308 signal n1, n2 : STD_LOGIC; 9309 9310 component NAND2MAC 9311 generic( 9312 tpdY_R : Time := 0 ns; 9313 tpdY_F : Time := 0 ns; 9314 strn : STRENGTH := strn_X01); 9315 port( 9316 I0 : in STD_LOGIC; 9317 I1 : in STD_LOGIC; 9318 Y : out STD_LOGIC); 9319 end component; 9320 9321begin 9322 9323 -- Extrinsic delay buffers 9324 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9325 generic map( tLH => twdi0_R, tHL => twdi0_F) 9326 port map( Input => i0, Output => connect(0)); 9327 9328 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9329 generic map( tLH => twdi1_R, tHL => twdi1_F) 9330 port map( Input => i1, Output => connect(1)); 9331 9332 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9333 generic map( tLH => twdi2_R, tHL => twdi2_F) 9334 port map( Input => i2, Output => connect(2)); 9335 9336 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9337 generic map( tLH => twdi3_R, tHL => twdi3_F) 9338 port map( Input => i3, Output => connect(3)); 9339 9340 -- Intrinsic delay buffers 9341 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9342 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 9343 port map( Input => connect(0), Output => prop_q(0)); 9344 9345 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9346 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 9347 port map( Input => connect(1), Output => prop_q(1)); 9348 9349 U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9350 generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) 9351 port map( Input => connect(2), Output => prop_q(2)); 9352 9353 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9354 generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) 9355 port map( Input => connect(3), Output => prop_q(3)); 9356 9357 -- Netlist 9358 U9 : NAND2MAC 9359 port map( I0 => n1, I1 => n2, Y => q); 9360 9361 U10 : NAND2MAC 9362 port map( I0 => prop_q(2), I1 => prop_q(3), Y => n2); 9363 9364 U11 : NAND2MAC 9365 port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); 9366 9367 9368end FTSM; 9369 9370configuration CFG_oa2a22_x4_FTSM of oa2a22_x4 is 9371 for FTSM 9372 end for; 9373end CFG_oa2a22_x4_FTSM; 9374 9375 9376----- CELL oa2ao222_x2 ----- 9377library IEEE; 9378use IEEE.STD_LOGIC_1164.all; 9379library SYNOPSYS; 9380use SYNOPSYS.attributes.REAL_NAME; 9381 9382-- entity declaration -- 9383entity oa2ao222_x2 is 9384 generic( 9385 Timing_mesg: Boolean := True; 9386 Timing_xgen: Boolean := False; 9387 tpdi0_q_R : Time := 0.495 ns; 9388 tpdi0_q_F : Time := 0.581 ns; 9389 tpdi1_q_R : Time := 0.598 ns; 9390 tpdi1_q_F : Time := 0.539 ns; 9391 tpdi2_q_R : Time := 0.464 ns; 9392 tpdi2_q_F : Time := 0.604 ns; 9393 tpdi3_q_R : Time := 0.556 ns; 9394 tpdi3_q_F : Time := 0.578 ns; 9395 tpdi4_q_R : Time := 0.558 ns; 9396 tpdi4_q_F : Time := 0.453 ns; 9397 twdi0_R : Time := 0.000 ns; 9398 twdi0_F : Time := 0.000 ns; 9399 twdi1_R : Time := 0.000 ns; 9400 twdi1_F : Time := 0.000 ns; 9401 twdi2_R : Time := 0.000 ns; 9402 twdi2_F : Time := 0.000 ns; 9403 twdi3_R : Time := 0.000 ns; 9404 twdi3_F : Time := 0.000 ns; 9405 twdi4_R : Time := 0.000 ns; 9406 twdi4_F : Time := 0.000 ns); 9407 9408 port( 9409 i0 : in STD_LOGIC; 9410 i1 : in STD_LOGIC; 9411 i2 : in STD_LOGIC; 9412 i3 : in STD_LOGIC; 9413 i4 : in STD_LOGIC; 9414 q : out STD_LOGIC); 9415end oa2ao222_x2; 9416 9417-- architecture body -- 9418library IEEE_ASIC; 9419use IEEE.STD_LOGIC_MISC.all; 9420use SYNOPSYS.attributes.backplane; 9421use SYNOPSYS.attributes.PRIVATE; 9422use SYNOPSYS.attributes.ASIC_CELL; 9423use SYNOPSYS.attributes.PROPAGATE_VALUE; 9424 9425architecture FTSM of oa2ao222_x2 is 9426 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 9427 attribute PRIVATE of FTSM : architecture is TRUE; 9428 attribute ASIC_CELL of FTSM : architecture is TRUE; 9429 9430 -- Backannotation attributes 9431 attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U10/tLH"; 9432 attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U10/tHL"; 9433 attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U9/tLH"; 9434 attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U9/tHL"; 9435 attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U8/tLH"; 9436 attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U8/tHL"; 9437 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U7/tLH"; 9438 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U7/tHL"; 9439 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U6/tLH"; 9440 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U6/tHL"; 9441 attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; 9442 attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; 9443 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 9444 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 9445 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 9446 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 9447 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 9448 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 9449 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 9450 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 9451 9452 signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); 9453 signal prop_q : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); 9454 signal n1, n2, n3 : STD_LOGIC; 9455 9456 component NAND2MAC 9457 generic( 9458 tpdY_R : Time := 0 ns; 9459 tpdY_F : Time := 0 ns; 9460 strn : STRENGTH := strn_X01); 9461 port( 9462 I0 : in STD_LOGIC; 9463 I1 : in STD_LOGIC; 9464 Y : out STD_LOGIC); 9465 end component; 9466 9467 component OR2MAC 9468 generic( 9469 tpdY_R : Time := 0 ns; 9470 tpdY_F : Time := 0 ns; 9471 strn : STRENGTH := strn_X01); 9472 port( 9473 I0 : in STD_LOGIC; 9474 I1 : in STD_LOGIC; 9475 Y : out STD_LOGIC); 9476 end component; 9477 9478begin 9479 9480 -- Extrinsic delay buffers 9481 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9482 generic map( tLH => twdi0_R, tHL => twdi0_F) 9483 port map( Input => i0, Output => connect(0)); 9484 9485 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9486 generic map( tLH => twdi1_R, tHL => twdi1_F) 9487 port map( Input => i1, Output => connect(1)); 9488 9489 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9490 generic map( tLH => twdi2_R, tHL => twdi2_F) 9491 port map( Input => i2, Output => connect(2)); 9492 9493 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9494 generic map( tLH => twdi3_R, tHL => twdi3_F) 9495 port map( Input => i3, Output => connect(3)); 9496 9497 U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9498 generic map( tLH => twdi4_R, tHL => twdi4_F) 9499 port map( Input => i4, Output => connect(4)); 9500 9501 -- Intrinsic delay buffers 9502 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9503 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 9504 port map( Input => connect(0), Output => prop_q(0)); 9505 9506 U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9507 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 9508 port map( Input => connect(1), Output => prop_q(1)); 9509 9510 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9511 generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) 9512 port map( Input => connect(2), Output => prop_q(2)); 9513 9514 U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9515 generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) 9516 port map( Input => connect(3), Output => prop_q(3)); 9517 9518 U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9519 generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) 9520 port map( Input => connect(4), Output => prop_q(4)); 9521 9522 -- Netlist 9523 U11 : NAND2MAC 9524 port map( I0 => n1, I1 => n2, Y => q); 9525 9526 U12 : OR2MAC 9527 port map( I0 => prop_q(3), I1 => prop_q(2), Y => n3); 9528 9529 U13 : NAND2MAC 9530 port map( I0 => prop_q(4), I1 => n3, Y => n2); 9531 9532 U14 : NAND2MAC 9533 port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); 9534 9535 9536end FTSM; 9537 9538configuration CFG_oa2ao222_x2_FTSM of oa2ao222_x2 is 9539 for FTSM 9540 end for; 9541end CFG_oa2ao222_x2_FTSM; 9542 9543 9544----- CELL oa2ao222_x4 ----- 9545library IEEE; 9546use IEEE.STD_LOGIC_1164.all; 9547library SYNOPSYS; 9548use SYNOPSYS.attributes.REAL_NAME; 9549 9550-- entity declaration -- 9551entity oa2ao222_x4 is 9552 generic( 9553 Timing_mesg: Boolean := True; 9554 Timing_xgen: Boolean := False; 9555 tpdi0_q_R : Time := 0.553 ns; 9556 tpdi0_q_F : Time := 0.657 ns; 9557 tpdi1_q_R : Time := 0.662 ns; 9558 tpdi1_q_F : Time := 0.616 ns; 9559 tpdi2_q_R : Time := 0.552 ns; 9560 tpdi2_q_F : Time := 0.693 ns; 9561 tpdi3_q_R : Time := 0.640 ns; 9562 tpdi3_q_F : Time := 0.660 ns; 9563 tpdi4_q_R : Time := 0.656 ns; 9564 tpdi4_q_F : Time := 0.529 ns; 9565 twdi0_R : Time := 0.000 ns; 9566 twdi0_F : Time := 0.000 ns; 9567 twdi1_R : Time := 0.000 ns; 9568 twdi1_F : Time := 0.000 ns; 9569 twdi2_R : Time := 0.000 ns; 9570 twdi2_F : Time := 0.000 ns; 9571 twdi3_R : Time := 0.000 ns; 9572 twdi3_F : Time := 0.000 ns; 9573 twdi4_R : Time := 0.000 ns; 9574 twdi4_F : Time := 0.000 ns); 9575 9576 port( 9577 i0 : in STD_LOGIC; 9578 i1 : in STD_LOGIC; 9579 i2 : in STD_LOGIC; 9580 i3 : in STD_LOGIC; 9581 i4 : in STD_LOGIC; 9582 q : out STD_LOGIC); 9583end oa2ao222_x4; 9584 9585-- architecture body -- 9586library IEEE_ASIC; 9587use IEEE.STD_LOGIC_MISC.all; 9588use SYNOPSYS.attributes.backplane; 9589use SYNOPSYS.attributes.PRIVATE; 9590use SYNOPSYS.attributes.ASIC_CELL; 9591use SYNOPSYS.attributes.PROPAGATE_VALUE; 9592 9593architecture FTSM of oa2ao222_x4 is 9594 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 9595 attribute PRIVATE of FTSM : architecture is TRUE; 9596 attribute ASIC_CELL of FTSM : architecture is TRUE; 9597 9598 -- Backannotation attributes 9599 attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U10/tLH"; 9600 attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U10/tHL"; 9601 attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U9/tLH"; 9602 attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U9/tHL"; 9603 attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U8/tLH"; 9604 attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U8/tHL"; 9605 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U7/tLH"; 9606 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U7/tHL"; 9607 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U6/tLH"; 9608 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U6/tHL"; 9609 attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; 9610 attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; 9611 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 9612 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 9613 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 9614 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 9615 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 9616 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 9617 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 9618 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 9619 9620 signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); 9621 signal prop_q : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); 9622 signal n1, n2, n3 : STD_LOGIC; 9623 9624 component NAND2MAC 9625 generic( 9626 tpdY_R : Time := 0 ns; 9627 tpdY_F : Time := 0 ns; 9628 strn : STRENGTH := strn_X01); 9629 port( 9630 I0 : in STD_LOGIC; 9631 I1 : in STD_LOGIC; 9632 Y : out STD_LOGIC); 9633 end component; 9634 9635 component OR2MAC 9636 generic( 9637 tpdY_R : Time := 0 ns; 9638 tpdY_F : Time := 0 ns; 9639 strn : STRENGTH := strn_X01); 9640 port( 9641 I0 : in STD_LOGIC; 9642 I1 : in STD_LOGIC; 9643 Y : out STD_LOGIC); 9644 end component; 9645 9646begin 9647 9648 -- Extrinsic delay buffers 9649 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9650 generic map( tLH => twdi0_R, tHL => twdi0_F) 9651 port map( Input => i0, Output => connect(0)); 9652 9653 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9654 generic map( tLH => twdi1_R, tHL => twdi1_F) 9655 port map( Input => i1, Output => connect(1)); 9656 9657 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9658 generic map( tLH => twdi2_R, tHL => twdi2_F) 9659 port map( Input => i2, Output => connect(2)); 9660 9661 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9662 generic map( tLH => twdi3_R, tHL => twdi3_F) 9663 port map( Input => i3, Output => connect(3)); 9664 9665 U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9666 generic map( tLH => twdi4_R, tHL => twdi4_F) 9667 port map( Input => i4, Output => connect(4)); 9668 9669 -- Intrinsic delay buffers 9670 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9671 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 9672 port map( Input => connect(0), Output => prop_q(0)); 9673 9674 U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9675 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 9676 port map( Input => connect(1), Output => prop_q(1)); 9677 9678 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9679 generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) 9680 port map( Input => connect(2), Output => prop_q(2)); 9681 9682 U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9683 generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) 9684 port map( Input => connect(3), Output => prop_q(3)); 9685 9686 U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9687 generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) 9688 port map( Input => connect(4), Output => prop_q(4)); 9689 9690 -- Netlist 9691 U11 : NAND2MAC 9692 port map( I0 => n1, I1 => n2, Y => q); 9693 9694 U12 : OR2MAC 9695 port map( I0 => prop_q(3), I1 => prop_q(2), Y => n3); 9696 9697 U13 : NAND2MAC 9698 port map( I0 => prop_q(4), I1 => n3, Y => n2); 9699 9700 U14 : NAND2MAC 9701 port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); 9702 9703 9704end FTSM; 9705 9706configuration CFG_oa2ao222_x4_FTSM of oa2ao222_x4 is 9707 for FTSM 9708 end for; 9709end CFG_oa2ao222_x4_FTSM; 9710 9711 9712----- CELL oa3ao322_x2 ----- 9713library IEEE; 9714use IEEE.STD_LOGIC_1164.all; 9715library SYNOPSYS; 9716use SYNOPSYS.attributes.REAL_NAME; 9717 9718-- entity declaration -- 9719entity oa3ao322_x2 is 9720 generic( 9721 Timing_mesg: Boolean := True; 9722 Timing_xgen: Boolean := False; 9723 tpdi0_q_R : Time := 0.638 ns; 9724 tpdi0_q_F : Time := 0.820 ns; 9725 tpdi1_q_R : Time := 0.735 ns; 9726 tpdi1_q_F : Time := 0.764 ns; 9727 tpdi2_q_R : Time := 0.806 ns; 9728 tpdi2_q_F : Time := 0.707 ns; 9729 tpdi3_q_R : Time := 0.560 ns; 9730 tpdi3_q_F : Time := 0.765 ns; 9731 tpdi4_q_R : Time := 0.649 ns; 9732 tpdi4_q_F : Time := 0.760 ns; 9733 tpdi5_q_R : Time := 0.734 ns; 9734 tpdi5_q_F : Time := 0.734 ns; 9735 tpdi6_q_R : Time := 0.563 ns; 9736 tpdi6_q_F : Time := 0.540 ns; 9737 twdi0_R : Time := 0.000 ns; 9738 twdi0_F : Time := 0.000 ns; 9739 twdi1_R : Time := 0.000 ns; 9740 twdi1_F : Time := 0.000 ns; 9741 twdi2_R : Time := 0.000 ns; 9742 twdi2_F : Time := 0.000 ns; 9743 twdi3_R : Time := 0.000 ns; 9744 twdi3_F : Time := 0.000 ns; 9745 twdi4_R : Time := 0.000 ns; 9746 twdi4_F : Time := 0.000 ns; 9747 twdi5_R : Time := 0.000 ns; 9748 twdi5_F : Time := 0.000 ns; 9749 twdi6_R : Time := 0.000 ns; 9750 twdi6_F : Time := 0.000 ns); 9751 9752 port( 9753 i0 : in STD_LOGIC; 9754 i1 : in STD_LOGIC; 9755 i2 : in STD_LOGIC; 9756 i3 : in STD_LOGIC; 9757 i4 : in STD_LOGIC; 9758 i5 : in STD_LOGIC; 9759 i6 : in STD_LOGIC; 9760 q : out STD_LOGIC); 9761end oa3ao322_x2; 9762 9763-- architecture body -- 9764library IEEE_ASIC; 9765use IEEE.STD_LOGIC_MISC.all; 9766use SYNOPSYS.attributes.backplane; 9767use SYNOPSYS.attributes.PRIVATE; 9768use SYNOPSYS.attributes.ASIC_CELL; 9769use SYNOPSYS.attributes.PROPAGATE_VALUE; 9770 9771architecture FTSM of oa3ao322_x2 is 9772 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 9773 attribute PRIVATE of FTSM : architecture is TRUE; 9774 attribute ASIC_CELL of FTSM : architecture is TRUE; 9775 9776 -- Backannotation attributes 9777 attribute PROPAGATE_VALUE of tpdi6_q_R: constant is "U14/tLH"; 9778 attribute PROPAGATE_VALUE of tpdi6_q_F: constant is "U14/tHL"; 9779 attribute PROPAGATE_VALUE of tpdi5_q_R: constant is "U13/tLH"; 9780 attribute PROPAGATE_VALUE of tpdi5_q_F: constant is "U13/tHL"; 9781 attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U12/tLH"; 9782 attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U12/tHL"; 9783 attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U11/tLH"; 9784 attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U11/tHL"; 9785 attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U10/tLH"; 9786 attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U10/tHL"; 9787 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U9/tLH"; 9788 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U9/tHL"; 9789 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U8/tLH"; 9790 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U8/tHL"; 9791 attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; 9792 attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; 9793 attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; 9794 attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; 9795 attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; 9796 attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; 9797 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 9798 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 9799 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 9800 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 9801 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 9802 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 9803 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 9804 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 9805 9806 signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); 9807 signal prop_q : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); 9808 signal n1, n2, n3 : STD_LOGIC; 9809 9810 component NAND2MAC 9811 generic( 9812 tpdY_R : Time := 0 ns; 9813 tpdY_F : Time := 0 ns; 9814 strn : STRENGTH := strn_X01); 9815 port( 9816 I0 : in STD_LOGIC; 9817 I1 : in STD_LOGIC; 9818 Y : out STD_LOGIC); 9819 end component; 9820 9821 component OR3MAC 9822 generic( 9823 tpdY_R : Time := 0 ns; 9824 tpdY_F : Time := 0 ns; 9825 strn : STRENGTH := strn_X01); 9826 port( 9827 I0 : in STD_LOGIC; 9828 I1 : in STD_LOGIC; 9829 I2 : in STD_LOGIC; 9830 Y : out STD_LOGIC); 9831 end component; 9832 9833 component NAND3MAC 9834 generic( 9835 tpdY_R : Time := 0 ns; 9836 tpdY_F : Time := 0 ns; 9837 strn : STRENGTH := strn_X01); 9838 port( 9839 I0 : in STD_LOGIC; 9840 I1 : in STD_LOGIC; 9841 I2 : in STD_LOGIC; 9842 Y : out STD_LOGIC); 9843 end component; 9844 9845begin 9846 9847 -- Extrinsic delay buffers 9848 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9849 generic map( tLH => twdi0_R, tHL => twdi0_F) 9850 port map( Input => i0, Output => connect(0)); 9851 9852 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9853 generic map( tLH => twdi1_R, tHL => twdi1_F) 9854 port map( Input => i1, Output => connect(1)); 9855 9856 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9857 generic map( tLH => twdi2_R, tHL => twdi2_F) 9858 port map( Input => i2, Output => connect(2)); 9859 9860 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9861 generic map( tLH => twdi3_R, tHL => twdi3_F) 9862 port map( Input => i3, Output => connect(3)); 9863 9864 U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9865 generic map( tLH => twdi4_R, tHL => twdi4_F) 9866 port map( Input => i4, Output => connect(4)); 9867 9868 U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9869 generic map( tLH => twdi5_R, tHL => twdi5_F) 9870 port map( Input => i5, Output => connect(5)); 9871 9872 U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 9873 generic map( tLH => twdi6_R, tHL => twdi6_F) 9874 port map( Input => i6, Output => connect(6)); 9875 9876 -- Intrinsic delay buffers 9877 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9878 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 9879 port map( Input => connect(0), Output => prop_q(0)); 9880 9881 U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9882 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 9883 port map( Input => connect(1), Output => prop_q(1)); 9884 9885 U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9886 generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) 9887 port map( Input => connect(2), Output => prop_q(2)); 9888 9889 U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9890 generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) 9891 port map( Input => connect(3), Output => prop_q(3)); 9892 9893 U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9894 generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) 9895 port map( Input => connect(4), Output => prop_q(4)); 9896 9897 U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9898 generic map( tLH => tpdi5_q_R, tHL => tpdi5_q_F) 9899 port map( Input => connect(5), Output => prop_q(5)); 9900 9901 U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 9902 generic map( tLH => tpdi6_q_R, tHL => tpdi6_q_F) 9903 port map( Input => connect(6), Output => prop_q(6)); 9904 9905 -- Netlist 9906 U15 : NAND2MAC 9907 port map( I0 => n1, I1 => n2, Y => q); 9908 9909 U16 : OR3MAC 9910 port map( I0 => prop_q(3), I1 => prop_q(4), I2 => prop_q(5), Y => 9911 n3); 9912 9913 U17 : NAND3MAC 9914 port map( I0 => prop_q(1), I1 => prop_q(2), I2 => prop_q(0), Y => 9915 n2); 9916 9917 U18 : NAND2MAC 9918 port map( I0 => prop_q(6), I1 => n3, Y => n1); 9919 9920 9921end FTSM; 9922 9923configuration CFG_oa3ao322_x2_FTSM of oa3ao322_x2 is 9924 for FTSM 9925 end for; 9926end CFG_oa3ao322_x2_FTSM; 9927 9928 9929----- CELL oa3ao322_x4 ----- 9930library IEEE; 9931use IEEE.STD_LOGIC_1164.all; 9932library SYNOPSYS; 9933use SYNOPSYS.attributes.REAL_NAME; 9934 9935-- entity declaration -- 9936entity oa3ao322_x4 is 9937 generic( 9938 Timing_mesg: Boolean := True; 9939 Timing_xgen: Boolean := False; 9940 tpdi0_q_R : Time := 0.717 ns; 9941 tpdi0_q_F : Time := 0.946 ns; 9942 tpdi1_q_R : Time := 0.818 ns; 9943 tpdi1_q_F : Time := 0.890 ns; 9944 tpdi2_q_R : Time := 0.894 ns; 9945 tpdi2_q_F : Time := 0.834 ns; 9946 tpdi3_q_R : Time := 0.673 ns; 9947 tpdi3_q_F : Time := 0.898 ns; 9948 tpdi4_q_R : Time := 0.758 ns; 9949 tpdi4_q_F : Time := 0.896 ns; 9950 tpdi5_q_R : Time := 0.839 ns; 9951 tpdi5_q_F : Time := 0.865 ns; 9952 tpdi6_q_R : Time := 0.684 ns; 9953 tpdi6_q_F : Time := 0.651 ns; 9954 twdi0_R : Time := 0.000 ns; 9955 twdi0_F : Time := 0.000 ns; 9956 twdi1_R : Time := 0.000 ns; 9957 twdi1_F : Time := 0.000 ns; 9958 twdi2_R : Time := 0.000 ns; 9959 twdi2_F : Time := 0.000 ns; 9960 twdi3_R : Time := 0.000 ns; 9961 twdi3_F : Time := 0.000 ns; 9962 twdi4_R : Time := 0.000 ns; 9963 twdi4_F : Time := 0.000 ns; 9964 twdi5_R : Time := 0.000 ns; 9965 twdi5_F : Time := 0.000 ns; 9966 twdi6_R : Time := 0.000 ns; 9967 twdi6_F : Time := 0.000 ns); 9968 9969 port( 9970 i0 : in STD_LOGIC; 9971 i1 : in STD_LOGIC; 9972 i2 : in STD_LOGIC; 9973 i3 : in STD_LOGIC; 9974 i4 : in STD_LOGIC; 9975 i5 : in STD_LOGIC; 9976 i6 : in STD_LOGIC; 9977 q : out STD_LOGIC); 9978end oa3ao322_x4; 9979 9980-- architecture body -- 9981library IEEE_ASIC; 9982use IEEE.STD_LOGIC_MISC.all; 9983use SYNOPSYS.attributes.backplane; 9984use SYNOPSYS.attributes.PRIVATE; 9985use SYNOPSYS.attributes.ASIC_CELL; 9986use SYNOPSYS.attributes.PROPAGATE_VALUE; 9987 9988architecture FTSM of oa3ao322_x4 is 9989 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 9990 attribute PRIVATE of FTSM : architecture is TRUE; 9991 attribute ASIC_CELL of FTSM : architecture is TRUE; 9992 9993 -- Backannotation attributes 9994 attribute PROPAGATE_VALUE of tpdi6_q_R: constant is "U14/tLH"; 9995 attribute PROPAGATE_VALUE of tpdi6_q_F: constant is "U14/tHL"; 9996 attribute PROPAGATE_VALUE of tpdi5_q_R: constant is "U13/tLH"; 9997 attribute PROPAGATE_VALUE of tpdi5_q_F: constant is "U13/tHL"; 9998 attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U12/tLH"; 9999 attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U12/tHL"; 10000 attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U11/tLH"; 10001 attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U11/tHL"; 10002 attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U10/tLH"; 10003 attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U10/tHL"; 10004 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U9/tLH"; 10005 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U9/tHL"; 10006 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U8/tLH"; 10007 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U8/tHL"; 10008 attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; 10009 attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; 10010 attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; 10011 attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; 10012 attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; 10013 attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; 10014 attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; 10015 attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; 10016 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 10017 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 10018 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 10019 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 10020 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 10021 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 10022 10023 signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); 10024 signal prop_q : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); 10025 signal n1, n2, n3 : STD_LOGIC; 10026 10027 component NAND2MAC 10028 generic( 10029 tpdY_R : Time := 0 ns; 10030 tpdY_F : Time := 0 ns; 10031 strn : STRENGTH := strn_X01); 10032 port( 10033 I0 : in STD_LOGIC; 10034 I1 : in STD_LOGIC; 10035 Y : out STD_LOGIC); 10036 end component; 10037 10038 component OR3MAC 10039 generic( 10040 tpdY_R : Time := 0 ns; 10041 tpdY_F : Time := 0 ns; 10042 strn : STRENGTH := strn_X01); 10043 port( 10044 I0 : in STD_LOGIC; 10045 I1 : in STD_LOGIC; 10046 I2 : in STD_LOGIC; 10047 Y : out STD_LOGIC); 10048 end component; 10049 10050 component NAND3MAC 10051 generic( 10052 tpdY_R : Time := 0 ns; 10053 tpdY_F : Time := 0 ns; 10054 strn : STRENGTH := strn_X01); 10055 port( 10056 I0 : in STD_LOGIC; 10057 I1 : in STD_LOGIC; 10058 I2 : in STD_LOGIC; 10059 Y : out STD_LOGIC); 10060 end component; 10061 10062begin 10063 10064 -- Extrinsic delay buffers 10065 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 10066 generic map( tLH => twdi0_R, tHL => twdi0_F) 10067 port map( Input => i0, Output => connect(0)); 10068 10069 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 10070 generic map( tLH => twdi1_R, tHL => twdi1_F) 10071 port map( Input => i1, Output => connect(1)); 10072 10073 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 10074 generic map( tLH => twdi2_R, tHL => twdi2_F) 10075 port map( Input => i2, Output => connect(2)); 10076 10077 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 10078 generic map( tLH => twdi3_R, tHL => twdi3_F) 10079 port map( Input => i3, Output => connect(3)); 10080 10081 U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 10082 generic map( tLH => twdi4_R, tHL => twdi4_F) 10083 port map( Input => i4, Output => connect(4)); 10084 10085 U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 10086 generic map( tLH => twdi5_R, tHL => twdi5_F) 10087 port map( Input => i5, Output => connect(5)); 10088 10089 U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 10090 generic map( tLH => twdi6_R, tHL => twdi6_F) 10091 port map( Input => i6, Output => connect(6)); 10092 10093 -- Intrinsic delay buffers 10094 U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 10095 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 10096 port map( Input => connect(0), Output => prop_q(0)); 10097 10098 U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 10099 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 10100 port map( Input => connect(1), Output => prop_q(1)); 10101 10102 U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 10103 generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) 10104 port map( Input => connect(2), Output => prop_q(2)); 10105 10106 U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 10107 generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) 10108 port map( Input => connect(3), Output => prop_q(3)); 10109 10110 U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 10111 generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) 10112 port map( Input => connect(4), Output => prop_q(4)); 10113 10114 U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 10115 generic map( tLH => tpdi5_q_R, tHL => tpdi5_q_F) 10116 port map( Input => connect(5), Output => prop_q(5)); 10117 10118 U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 10119 generic map( tLH => tpdi6_q_R, tHL => tpdi6_q_F) 10120 port map( Input => connect(6), Output => prop_q(6)); 10121 10122 -- Netlist 10123 U15 : NAND2MAC 10124 port map( I0 => n1, I1 => n2, Y => q); 10125 10126 U16 : OR3MAC 10127 port map( I0 => prop_q(3), I1 => prop_q(4), I2 => prop_q(5), Y => 10128 n3); 10129 10130 U17 : NAND3MAC 10131 port map( I0 => prop_q(1), I1 => prop_q(2), I2 => prop_q(0), Y => 10132 n2); 10133 10134 U18 : NAND2MAC 10135 port map( I0 => prop_q(6), I1 => n3, Y => n1); 10136 10137 10138end FTSM; 10139 10140configuration CFG_oa3ao322_x4_FTSM of oa3ao322_x4 is 10141 for FTSM 10142 end for; 10143end CFG_oa3ao322_x4_FTSM; 10144 10145 10146----- CELL oa22_x2 ----- 10147library IEEE; 10148use IEEE.STD_LOGIC_1164.all; 10149library SYNOPSYS; 10150use SYNOPSYS.attributes.REAL_NAME; 10151 10152-- entity declaration -- 10153entity oa22_x2 is 10154 generic( 10155 Timing_mesg: Boolean := True; 10156 Timing_xgen: Boolean := False; 10157 tpdi0_q_R : Time := 0.390 ns; 10158 tpdi0_q_F : Time := 0.555 ns; 10159 tpdi1_q_R : Time := 0.488 ns; 10160 tpdi1_q_F : Time := 0.525 ns; 10161 tpdi2_q_R : Time := 0.438 ns; 10162 tpdi2_q_F : Time := 0.454 ns; 10163 twdi0_R : Time := 0.000 ns; 10164 twdi0_F : Time := 0.000 ns; 10165 twdi1_R : Time := 0.000 ns; 10166 twdi1_F : Time := 0.000 ns; 10167 twdi2_R : Time := 0.000 ns; 10168 twdi2_F : Time := 0.000 ns); 10169 10170 port( 10171 i0 : in STD_LOGIC; 10172 i1 : in STD_LOGIC; 10173 i2 : in STD_LOGIC; 10174 q : out STD_LOGIC); 10175end oa22_x2; 10176 10177-- architecture body -- 10178library IEEE_ASIC; 10179use IEEE.STD_LOGIC_MISC.all; 10180use SYNOPSYS.attributes.backplane; 10181use SYNOPSYS.attributes.PRIVATE; 10182use SYNOPSYS.attributes.ASIC_CELL; 10183use SYNOPSYS.attributes.PROPAGATE_VALUE; 10184 10185architecture FTSM of oa22_x2 is 10186 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 10187 attribute PRIVATE of FTSM : architecture is TRUE; 10188 attribute ASIC_CELL of FTSM : architecture is TRUE; 10189 10190 -- Backannotation attributes 10191 attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; 10192 attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; 10193 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; 10194 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; 10195 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; 10196 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; 10197 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 10198 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 10199 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 10200 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 10201 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 10202 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 10203 10204 signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 10205 signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 10206 signal n1 : STD_LOGIC; 10207 10208 component OR2MAC 10209 generic( 10210 tpdY_R : Time := 0 ns; 10211 tpdY_F : Time := 0 ns; 10212 strn : STRENGTH := strn_X01); 10213 port( 10214 I0 : in STD_LOGIC; 10215 I1 : in STD_LOGIC; 10216 Y : out STD_LOGIC); 10217 end component; 10218 10219 component AND2MAC 10220 generic( 10221 tpdY_R : Time := 0 ns; 10222 tpdY_F : Time := 0 ns; 10223 strn : STRENGTH := strn_X01); 10224 port( 10225 I0 : in STD_LOGIC; 10226 I1 : in STD_LOGIC; 10227 Y : out STD_LOGIC); 10228 end component; 10229 10230begin 10231 10232 -- Extrinsic delay buffers 10233 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 10234 generic map( tLH => twdi0_R, tHL => twdi0_F) 10235 port map( Input => i0, Output => connect(0)); 10236 10237 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 10238 generic map( tLH => twdi1_R, tHL => twdi1_F) 10239 port map( Input => i1, Output => connect(1)); 10240 10241 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 10242 generic map( tLH => twdi2_R, tHL => twdi2_F) 10243 port map( Input => i2, Output => connect(2)); 10244 10245 -- Intrinsic delay buffers 10246 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 10247 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 10248 port map( Input => connect(0), Output => prop_q(0)); 10249 10250 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 10251 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 10252 port map( Input => connect(1), Output => prop_q(1)); 10253 10254 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 10255 generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) 10256 port map( Input => connect(2), Output => prop_q(2)); 10257 10258 -- Netlist 10259 U7 : OR2MAC 10260 port map( I0 => n1, I1 => prop_q(2), Y => q); 10261 10262 U8 : AND2MAC 10263 port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); 10264 10265 10266end FTSM; 10267 10268configuration CFG_oa22_x2_FTSM of oa22_x2 is 10269 for FTSM 10270 end for; 10271end CFG_oa22_x2_FTSM; 10272 10273 10274----- CELL oa22_x4 ----- 10275library IEEE; 10276use IEEE.STD_LOGIC_1164.all; 10277library SYNOPSYS; 10278use SYNOPSYS.attributes.REAL_NAME; 10279 10280-- entity declaration -- 10281entity oa22_x4 is 10282 generic( 10283 Timing_mesg: Boolean := True; 10284 Timing_xgen: Boolean := False; 10285 tpdi0_q_R : Time := 0.511 ns; 10286 tpdi0_q_F : Time := 0.677 ns; 10287 tpdi1_q_R : Time := 0.615 ns; 10288 tpdi1_q_F : Time := 0.650 ns; 10289 tpdi2_q_R : Time := 0.523 ns; 10290 tpdi2_q_F : Time := 0.571 ns; 10291 twdi0_R : Time := 0.000 ns; 10292 twdi0_F : Time := 0.000 ns; 10293 twdi1_R : Time := 0.000 ns; 10294 twdi1_F : Time := 0.000 ns; 10295 twdi2_R : Time := 0.000 ns; 10296 twdi2_F : Time := 0.000 ns); 10297 10298 port( 10299 i0 : in STD_LOGIC; 10300 i1 : in STD_LOGIC; 10301 i2 : in STD_LOGIC; 10302 q : out STD_LOGIC); 10303end oa22_x4; 10304 10305-- architecture body -- 10306library IEEE_ASIC; 10307use IEEE.STD_LOGIC_MISC.all; 10308use SYNOPSYS.attributes.backplane; 10309use SYNOPSYS.attributes.PRIVATE; 10310use SYNOPSYS.attributes.ASIC_CELL; 10311use SYNOPSYS.attributes.PROPAGATE_VALUE; 10312 10313architecture FTSM of oa22_x4 is 10314 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 10315 attribute PRIVATE of FTSM : architecture is TRUE; 10316 attribute ASIC_CELL of FTSM : architecture is TRUE; 10317 10318 -- Backannotation attributes 10319 attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; 10320 attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; 10321 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; 10322 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; 10323 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; 10324 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; 10325 attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; 10326 attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; 10327 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 10328 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 10329 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 10330 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 10331 10332 signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 10333 signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); 10334 signal n1 : STD_LOGIC; 10335 10336 component OR2MAC 10337 generic( 10338 tpdY_R : Time := 0 ns; 10339 tpdY_F : Time := 0 ns; 10340 strn : STRENGTH := strn_X01); 10341 port( 10342 I0 : in STD_LOGIC; 10343 I1 : in STD_LOGIC; 10344 Y : out STD_LOGIC); 10345 end component; 10346 10347 component AND2MAC 10348 generic( 10349 tpdY_R : Time := 0 ns; 10350 tpdY_F : Time := 0 ns; 10351 strn : STRENGTH := strn_X01); 10352 port( 10353 I0 : in STD_LOGIC; 10354 I1 : in STD_LOGIC; 10355 Y : out STD_LOGIC); 10356 end component; 10357 10358begin 10359 10360 -- Extrinsic delay buffers 10361 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 10362 generic map( tLH => twdi0_R, tHL => twdi0_F) 10363 port map( Input => i0, Output => connect(0)); 10364 10365 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 10366 generic map( tLH => twdi1_R, tHL => twdi1_F) 10367 port map( Input => i1, Output => connect(1)); 10368 10369 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 10370 generic map( tLH => twdi2_R, tHL => twdi2_F) 10371 port map( Input => i2, Output => connect(2)); 10372 10373 -- Intrinsic delay buffers 10374 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 10375 generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) 10376 port map( Input => connect(0), Output => prop_q(0)); 10377 10378 U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 10379 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 10380 port map( Input => connect(1), Output => prop_q(1)); 10381 10382 U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 10383 generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) 10384 port map( Input => connect(2), Output => prop_q(2)); 10385 10386 -- Netlist 10387 U7 : OR2MAC 10388 port map( I0 => n1, I1 => prop_q(2), Y => q); 10389 10390 U8 : AND2MAC 10391 port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); 10392 10393 10394end FTSM; 10395 10396configuration CFG_oa22_x4_FTSM of oa22_x4 is 10397 for FTSM 10398 end for; 10399end CFG_oa22_x4_FTSM; 10400 10401 10402----- CELL on12_x1 ----- 10403library IEEE; 10404use IEEE.STD_LOGIC_1164.all; 10405library SYNOPSYS; 10406use SYNOPSYS.attributes.REAL_NAME; 10407 10408-- entity declaration -- 10409entity on12_x1 is 10410 generic( 10411 Timing_mesg: Boolean := True; 10412 Timing_xgen: Boolean := False; 10413 tpdi0_q_R : Time := 0.111 ns; 10414 tpdi0_q_F : Time := 0.234 ns; 10415 tpdi1_q_R : Time := 0.314 ns; 10416 tpdi1_q_F : Time := 0.291 ns; 10417 twdi0_R : Time := 0.000 ns; 10418 twdi0_F : Time := 0.000 ns; 10419 twdi1_R : Time := 0.000 ns; 10420 twdi1_F : Time := 0.000 ns); 10421 10422 port( 10423 i0 : in STD_LOGIC; 10424 i1 : in STD_LOGIC; 10425 q : out STD_LOGIC); 10426end on12_x1; 10427 10428-- architecture body -- 10429library IEEE_ASIC; 10430use IEEE.STD_LOGIC_MISC.all; 10431use SYNOPSYS.attributes.backplane; 10432use SYNOPSYS.attributes.PRIVATE; 10433use SYNOPSYS.attributes.ASIC_CELL; 10434use SYNOPSYS.attributes.PROPAGATE_VALUE; 10435 10436architecture FTSM of on12_x1 is 10437 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 10438 attribute PRIVATE of FTSM : architecture is TRUE; 10439 attribute ASIC_CELL of FTSM : architecture is TRUE; 10440 10441 -- Backannotation attributes 10442 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; 10443 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; 10444 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tLH"; 10445 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tHL"; 10446 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 10447 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 10448 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 10449 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 10450 10451 signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 10452 signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 10453 signal n1 : STD_LOGIC; 10454 10455 component NAND2MAC 10456 generic( 10457 tpdY_R : Time := 0 ns; 10458 tpdY_F : Time := 0 ns; 10459 strn : STRENGTH := strn_X01); 10460 port( 10461 I0 : in STD_LOGIC; 10462 I1 : in STD_LOGIC; 10463 Y : out STD_LOGIC); 10464 end component; 10465 10466 component INVMAC 10467 generic( 10468 tpdY_R : Time := 0 ns; 10469 tpdY_F : Time := 0 ns; 10470 strn : STRENGTH := strn_X01); 10471 port( 10472 I0 : in STD_LOGIC; 10473 Y : out STD_LOGIC); 10474 end component; 10475 10476begin 10477 10478 -- Extrinsic delay buffers 10479 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 10480 generic map( tLH => twdi0_R, tHL => twdi0_F) 10481 port map( Input => i0, Output => connect(0)); 10482 10483 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 10484 generic map( tLH => twdi1_R, tHL => twdi1_F) 10485 port map( Input => i1, Output => connect(1)); 10486 10487 -- Intrinsic delay buffers 10488 U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 10489 generic map( tLH => tpdi0_q_F, tHL => tpdi0_q_R) 10490 port map( Input => connect(0), Output => prop_q(0)); 10491 10492 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 10493 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 10494 port map( Input => connect(1), Output => prop_q(1)); 10495 10496 -- Netlist 10497 U5 : NAND2MAC 10498 port map( I0 => prop_q(0), I1 => n1, Y => q); 10499 10500 U6 : INVMAC 10501 port map( I0 => prop_q(1), Y => n1); 10502 10503 10504end FTSM; 10505 10506configuration CFG_on12_x1_FTSM of on12_x1 is 10507 for FTSM 10508 end for; 10509end CFG_on12_x1_FTSM; 10510 10511 10512----- CELL on12_x4 ----- 10513library IEEE; 10514use IEEE.STD_LOGIC_1164.all; 10515library SYNOPSYS; 10516use SYNOPSYS.attributes.REAL_NAME; 10517 10518-- entity declaration -- 10519entity on12_x4 is 10520 generic( 10521 Timing_mesg: Boolean := True; 10522 Timing_xgen: Boolean := False; 10523 tpdi0_q_R : Time := 0.474 ns; 10524 tpdi0_q_F : Time := 0.499 ns; 10525 tpdi1_q_R : Time := 0.491 ns; 10526 tpdi1_q_F : Time := 0.394 ns; 10527 twdi0_R : Time := 0.000 ns; 10528 twdi0_F : Time := 0.000 ns; 10529 twdi1_R : Time := 0.000 ns; 10530 twdi1_F : Time := 0.000 ns); 10531 10532 port( 10533 i0 : in STD_LOGIC; 10534 i1 : in STD_LOGIC; 10535 q : out STD_LOGIC); 10536end on12_x4; 10537 10538-- architecture body -- 10539library IEEE_ASIC; 10540use IEEE.STD_LOGIC_MISC.all; 10541use SYNOPSYS.attributes.backplane; 10542use SYNOPSYS.attributes.PRIVATE; 10543use SYNOPSYS.attributes.ASIC_CELL; 10544use SYNOPSYS.attributes.PROPAGATE_VALUE; 10545 10546architecture FTSM of on12_x4 is 10547 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 10548 attribute PRIVATE of FTSM : architecture is TRUE; 10549 attribute ASIC_CELL of FTSM : architecture is TRUE; 10550 10551 -- Backannotation attributes 10552 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; 10553 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; 10554 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tLH"; 10555 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tHL"; 10556 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 10557 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 10558 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 10559 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 10560 10561 signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 10562 signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 10563 signal n1 : STD_LOGIC; 10564 10565 component NAND2MAC 10566 generic( 10567 tpdY_R : Time := 0 ns; 10568 tpdY_F : Time := 0 ns; 10569 strn : STRENGTH := strn_X01); 10570 port( 10571 I0 : in STD_LOGIC; 10572 I1 : in STD_LOGIC; 10573 Y : out STD_LOGIC); 10574 end component; 10575 10576 component INVMAC 10577 generic( 10578 tpdY_R : Time := 0 ns; 10579 tpdY_F : Time := 0 ns; 10580 strn : STRENGTH := strn_X01); 10581 port( 10582 I0 : in STD_LOGIC; 10583 Y : out STD_LOGIC); 10584 end component; 10585 10586begin 10587 10588 -- Extrinsic delay buffers 10589 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 10590 generic map( tLH => twdi0_R, tHL => twdi0_F) 10591 port map( Input => i0, Output => connect(0)); 10592 10593 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 10594 generic map( tLH => twdi1_R, tHL => twdi1_F) 10595 port map( Input => i1, Output => connect(1)); 10596 10597 -- Intrinsic delay buffers 10598 U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 10599 generic map( tLH => tpdi0_q_F, tHL => tpdi0_q_R) 10600 port map( Input => connect(0), Output => prop_q(0)); 10601 10602 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 10603 generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) 10604 port map( Input => connect(1), Output => prop_q(1)); 10605 10606 -- Netlist 10607 U5 : NAND2MAC 10608 port map( I0 => prop_q(0), I1 => n1, Y => q); 10609 10610 U6 : INVMAC 10611 port map( I0 => prop_q(1), Y => n1); 10612 10613 10614end FTSM; 10615 10616configuration CFG_on12_x4_FTSM of on12_x4 is 10617 for FTSM 10618 end for; 10619end CFG_on12_x4_FTSM; 10620 10621 10622----- CELL one_x0 ----- 10623library IEEE; 10624use IEEE.STD_LOGIC_1164.all; 10625library SYNOPSYS; 10626use SYNOPSYS.attributes.REAL_NAME; 10627 10628-- entity declaration -- 10629entity one_x0 is 10630 generic( 10631 Timing_mesg: Boolean := True; 10632 Timing_xgen: Boolean := False); 10633 10634 port( 10635 q : out STD_LOGIC := '1'); 10636end one_x0; 10637 10638-- architecture body -- 10639library IEEE_ASIC; 10640use IEEE.STD_LOGIC_MISC.all; 10641use SYNOPSYS.attributes.backplane; 10642use SYNOPSYS.attributes.PRIVATE; 10643use SYNOPSYS.attributes.ASIC_CELL; 10644use SYNOPSYS.attributes.PROPAGATE_VALUE; 10645 10646architecture FTSM of one_x0 is 10647 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 10648 attribute PRIVATE of FTSM : architecture is TRUE; 10649 attribute ASIC_CELL of FTSM : architecture is TRUE; 10650 10651 -- Backannotation attributes 10652 10653 10654begin 10655 10656 -- Netlist 10657 q <= '1'; 10658 10659end FTSM; 10660 10661configuration CFG_one_x0_FTSM of one_x0 is 10662 for FTSM 10663 end for; 10664end CFG_one_x0_FTSM; 10665 10666 10667----- CELL sff1_x4 ----- 10668library IEEE; 10669use IEEE.STD_LOGIC_1164.all; 10670library SYNOPSYS; 10671use SYNOPSYS.attributes.REAL_NAME; 10672 10673-- entity declaration -- 10674entity sff1_x4 is 10675 generic( 10676 Timing_mesg: Boolean := True; 10677 Timing_xgen: Boolean := False; 10678 tpdck_q_R : Time := 0.500 ns; 10679 tpdck_q_F : Time := 0.500 ns; 10680 tsui_ck : Time := 0.585 ns; 10681 thck_i : Time := 0.000 ns; 10682 twdi_R : Time := 0.000 ns; 10683 twdi_F : Time := 0.000 ns; 10684 twdck_R : Time := 0.000 ns; 10685 twdck_F : Time := 0.000 ns); 10686 10687 port( 10688 i : in STD_LOGIC; 10689 ck : in STD_LOGIC; 10690 q : out STD_LOGIC); 10691end sff1_x4; 10692 10693-- architecture body -- 10694library IEEE_ASIC; 10695use IEEE.STD_LOGIC_MISC.all; 10696use SYNOPSYS.attributes.backplane; 10697use SYNOPSYS.attributes.PRIVATE; 10698use SYNOPSYS.attributes.ASIC_CELL; 10699use SYNOPSYS.attributes.PROPAGATE_VALUE; 10700 10701architecture FTSM of sff1_x4 is 10702 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 10703 attribute PRIVATE of FTSM : architecture is TRUE; 10704 attribute ASIC_CELL of FTSM : architecture is TRUE; 10705 10706 -- Backannotation attributes 10707 attribute PROPAGATE_VALUE of thck_i: constant is "FEC/F2/tHold"; 10708 attribute PROPAGATE_VALUE of tsui_ck: constant is "FEC/F1/tSetup"; 10709 attribute PROPAGATE_VALUE of tpdck_q_F: constant is "U3/U1/tHL"; 10710 attribute PROPAGATE_VALUE of tpdck_q_R: constant is "U3/U1/tLH"; 10711 attribute PROPAGATE_VALUE of twdck_F: constant is "U2/tHL"; 10712 attribute PROPAGATE_VALUE of twdck_R: constant is "U2/tLH"; 10713 attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; 10714 attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; 10715 10716 signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 10717 signal n1 : STD_LOGIC; 10718 10719 component DFFLMAC 10720 generic( 10721 tpdY_R : Time := 0 ns; 10722 tpdY_F : Time := 0 ns; 10723 strn : STRENGTH := strn_X01); 10724 port( 10725 D : in STD_LOGIC; 10726 CLK : in STD_LOGIC; 10727 CLR : in STD_LOGIC; 10728 Q : out STD_LOGIC); 10729 end component; 10730 10731begin 10732 10733 -- Extrinsic delay buffers 10734 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 10735 generic map( tLH => twdi_R, tHL => twdi_F) 10736 port map( Input => i, Output => connect(0)); 10737 10738 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 10739 generic map( tLH => twdck_R, tHL => twdck_F) 10740 port map( Input => ck, Output => connect(1)); 10741 10742 -- Netlist 10743 U3 : DFFLMAC 10744 generic map( tpdY_R => tpdck_q_R, tpdY_F => tpdck_q_F ) 10745 port map( D => connect(0), CLK => connect(1), CLR => n1, Q => q); 10746 10747 n1 <= '1'; 10748 10749 -- Forbidden Events 10750 FEC : if Timing_mesg generate 10751 10752 F1 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK 10753 generic map( N => 1, tSetup => tsui_ck) 10754 port map( Data(1) => connect(0), Clock => connect(1)); 10755 10756 F2 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK 10757 generic map( N => 1, tHold => thck_i) 10758 port map( Data(1) => connect(0), Clock => connect(1)); 10759 10760 end generate FEC; 10761 10762end FTSM; 10763 10764configuration CFG_sff1_x4_FTSM of sff1_x4 is 10765 for FTSM 10766 end for; 10767end CFG_sff1_x4_FTSM; 10768 10769 10770----- CELL sff2_x4 ----- 10771library IEEE; 10772use IEEE.STD_LOGIC_1164.all; 10773library SYNOPSYS; 10774use SYNOPSYS.attributes.REAL_NAME; 10775 10776-- entity declaration -- 10777entity sff2_x4 is 10778 generic( 10779 Timing_mesg: Boolean := True; 10780 Timing_xgen: Boolean := False; 10781 tpdck_q_R : Time := 0.500 ns; 10782 tpdck_q_F : Time := 0.500 ns; 10783 tsui0_ck : Time := 0.764 ns; 10784 thck_i0 : Time := 0.000 ns; 10785 tsui1_ck : Time := 0.764 ns; 10786 thck_i1 : Time := 0.000 ns; 10787 tsucmd_ck : Time := 0.833 ns; 10788 thck_cmd : Time := 0.000 ns; 10789 twdi0_R : Time := 0.000 ns; 10790 twdi0_F : Time := 0.000 ns; 10791 twdi1_R : Time := 0.000 ns; 10792 twdi1_F : Time := 0.000 ns; 10793 twdcmd_R : Time := 0.000 ns; 10794 twdcmd_F : Time := 0.000 ns; 10795 twdck_R : Time := 0.000 ns; 10796 twdck_F : Time := 0.000 ns); 10797 10798 port( 10799 i0 : in STD_LOGIC; 10800 i1 : in STD_LOGIC; 10801 cmd : in STD_LOGIC; 10802 ck : in STD_LOGIC; 10803 q : out STD_LOGIC); 10804end sff2_x4; 10805 10806-- architecture body -- 10807library IEEE_ASIC; 10808use IEEE.STD_LOGIC_MISC.all; 10809use SYNOPSYS.attributes.backplane; 10810use SYNOPSYS.attributes.PRIVATE; 10811use SYNOPSYS.attributes.ASIC_CELL; 10812use SYNOPSYS.attributes.PROPAGATE_VALUE; 10813 10814architecture FTSM of sff2_x4 is 10815 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 10816 attribute PRIVATE of FTSM : architecture is TRUE; 10817 attribute ASIC_CELL of FTSM : architecture is TRUE; 10818 10819 -- Backannotation attributes 10820 attribute PROPAGATE_VALUE of thck_cmd: constant is "FEC/F6/tHold"; 10821 attribute PROPAGATE_VALUE of tsucmd_ck: constant is "FEC/F5/tSetup"; 10822 attribute PROPAGATE_VALUE of thck_i1: constant is "FEC/F4/tHold"; 10823 attribute PROPAGATE_VALUE of tsui1_ck: constant is "FEC/F3/tSetup"; 10824 attribute PROPAGATE_VALUE of thck_i0: constant is "FEC/F2/tHold"; 10825 attribute PROPAGATE_VALUE of tsui0_ck: constant is "FEC/F1/tSetup"; 10826 attribute PROPAGATE_VALUE of tpdck_q_F: constant is "U6/U1/tHL"; 10827 attribute PROPAGATE_VALUE of tpdck_q_R: constant is "U6/U1/tLH"; 10828 attribute PROPAGATE_VALUE of twdck_F: constant is "U4/tHL"; 10829 attribute PROPAGATE_VALUE of twdck_R: constant is "U4/tLH"; 10830 attribute PROPAGATE_VALUE of twdcmd_F: constant is "U3/tHL"; 10831 attribute PROPAGATE_VALUE of twdcmd_R: constant is "U3/tLH"; 10832 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 10833 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 10834 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 10835 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 10836 10837 signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); 10838 signal n1, n2 : STD_LOGIC; 10839 10840 component MUX2MAC 10841 generic( 10842 tpdY_R : Time := 0 ns; 10843 tpdY_F : Time := 0 ns; 10844 strn : STRENGTH := strn_X01); 10845 port( 10846 I0 : in STD_LOGIC; 10847 I1 : in STD_LOGIC; 10848 S0 : in STD_LOGIC; 10849 Y : out STD_LOGIC); 10850 end component; 10851 10852 component DFFLMAC 10853 generic( 10854 tpdY_R : Time := 0 ns; 10855 tpdY_F : Time := 0 ns; 10856 strn : STRENGTH := strn_X01); 10857 port( 10858 D : in STD_LOGIC; 10859 CLK : in STD_LOGIC; 10860 CLR : in STD_LOGIC; 10861 Q : out STD_LOGIC); 10862 end component; 10863 10864begin 10865 10866 -- Extrinsic delay buffers 10867 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 10868 generic map( tLH => twdi0_R, tHL => twdi0_F) 10869 port map( Input => i0, Output => connect(0)); 10870 10871 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 10872 generic map( tLH => twdi1_R, tHL => twdi1_F) 10873 port map( Input => i1, Output => connect(1)); 10874 10875 U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 10876 generic map( tLH => twdcmd_R, tHL => twdcmd_F) 10877 port map( Input => cmd, Output => connect(2)); 10878 10879 U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 10880 generic map( tLH => twdck_R, tHL => twdck_F) 10881 port map( Input => ck, Output => connect(3)); 10882 10883 -- Netlist 10884 U5 : MUX2MAC 10885 port map( I0 => connect(0), I1 => connect(1), S0 => connect(2), Y => 10886 n1); 10887 10888 U6 : DFFLMAC 10889 generic map( tpdY_R => tpdck_q_R, tpdY_F => tpdck_q_F ) 10890 port map( D => n1, CLK => connect(3), CLR => n2, Q => q); 10891 10892 n2 <= '1'; 10893 10894 -- Forbidden Events 10895 FEC : if Timing_mesg generate 10896 10897 F1 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK 10898 generic map( N => 1, tSetup => tsui0_ck) 10899 port map( Data(1) => connect(0), Clock => connect(3)); 10900 10901 F2 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK 10902 generic map( N => 1, tHold => thck_i0) 10903 port map( Data(1) => connect(0), Clock => connect(3)); 10904 10905 F3 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK 10906 generic map( N => 1, tSetup => tsui1_ck) 10907 port map( Data(1) => connect(1), Clock => connect(3)); 10908 10909 F4 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK 10910 generic map( N => 1, tHold => thck_i1) 10911 port map( Data(1) => connect(1), Clock => connect(3)); 10912 10913 F5 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK 10914 generic map( N => 1, tSetup => tsucmd_ck) 10915 port map( Data(1) => connect(2), Clock => connect(3)); 10916 10917 F6 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK 10918 generic map( N => 1, tHold => thck_cmd) 10919 port map( Data(1) => connect(2), Clock => connect(3)); 10920 10921 end generate FEC; 10922 10923end FTSM; 10924 10925configuration CFG_sff2_x4_FTSM of sff2_x4 is 10926 for FTSM 10927 end for; 10928end CFG_sff2_x4_FTSM; 10929 10930 10931----- CELL ts_x4 ----- 10932library IEEE; 10933use IEEE.STD_LOGIC_1164.all; 10934library SYNOPSYS; 10935use SYNOPSYS.attributes.REAL_NAME; 10936 10937-- entity declaration -- 10938entity ts_x4 is 10939 generic( 10940 Timing_mesg: Boolean := True; 10941 Timing_xgen: Boolean := False; 10942 tpdcmd_q_R : Time := 0.492 ns; 10943 tpdcmd_q_F : Time := 0.409 ns; 10944 tpdcmd_q_LZ : Time := 0.492 ns; 10945 tpdcmd_q_HZ : Time := 0.409 ns; 10946 tpdi_q_R : Time := 0.475 ns; 10947 tpdi_q_F : Time := 0.444 ns; 10948 twdi_R : Time := 0.000 ns; 10949 twdi_F : Time := 0.000 ns; 10950 twdcmd_R : Time := 0.000 ns; 10951 twdcmd_F : Time := 0.000 ns); 10952 10953 port( 10954 i : in STD_LOGIC; 10955 cmd : in STD_LOGIC; 10956 q : out STD_LOGIC); 10957end ts_x4; 10958 10959-- architecture body -- 10960library IEEE_ASIC; 10961use IEEE.STD_LOGIC_MISC.all; 10962use SYNOPSYS.attributes.backplane; 10963use SYNOPSYS.attributes.PRIVATE; 10964use SYNOPSYS.attributes.ASIC_CELL; 10965use SYNOPSYS.attributes.PROPAGATE_VALUE; 10966 10967architecture FTSM of ts_x4 is 10968 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 10969 attribute PRIVATE of FTSM : architecture is TRUE; 10970 attribute ASIC_CELL of FTSM : architecture is TRUE; 10971 10972 -- Backannotation attributes 10973 attribute PROPAGATE_VALUE of tpdi_q_R: constant is "U4/tLH"; 10974 attribute PROPAGATE_VALUE of tpdi_q_F: constant is "U4/tHL"; 10975 attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is "U3/tHL, U3/tLH"; 10976 attribute PROPAGATE_VALUE of tpdcmd_q_HZ: constant is "U3/tLH, U3/tHL"; 10977 attribute PROPAGATE_VALUE of tpdcmd_q_LZ: constant is "U3/tLH, U3/tHL"; 10978 attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is "U3/tLH, U3/tHL"; 10979 attribute PROPAGATE_VALUE of twdcmd_F: constant is "U2/tHL"; 10980 attribute PROPAGATE_VALUE of twdcmd_R: constant is "U2/tLH"; 10981 attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; 10982 attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; 10983 10984 signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 10985 signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 10986 10987 component BUF3SHEMAC 10988 generic( 10989 tpdY_R : Time := 0 ns; 10990 tpdY_F : Time := 0 ns; 10991 strn : STRENGTH := strn_X01); 10992 port( 10993 I0 : in STD_LOGIC; 10994 OE : in STD_LOGIC; 10995 Y : out STD_LOGIC); 10996 end component; 10997 10998begin 10999 11000 -- Extrinsic delay buffers 11001 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 11002 generic map( tLH => twdi_R, tHL => twdi_F) 11003 port map( Input => i, Output => connect(1)); 11004 11005 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 11006 generic map( tLH => twdcmd_R, tHL => twdcmd_F) 11007 port map( Input => cmd, Output => connect(0)); 11008 11009 -- Intrinsic delay buffers 11010 U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 11011 generic map( tLH => tpdcmd_q_R, tHL => tpdcmd_q_R) 11012 port map( Input => connect(0), Output => prop_q(0)); 11013 11014 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 11015 generic map( tLH => tpdi_q_R, tHL => tpdi_q_F) 11016 port map( Input => connect(1), Output => prop_q(1)); 11017 11018 -- Netlist 11019 U5 : BUF3SHEMAC 11020 port map( I0 => prop_q(1), OE => prop_q(0), Y => q); 11021 11022 11023end FTSM; 11024 11025configuration CFG_ts_x4_FTSM of ts_x4 is 11026 for FTSM 11027 end for; 11028end CFG_ts_x4_FTSM; 11029 11030 11031----- CELL ts_x8 ----- 11032library IEEE; 11033use IEEE.STD_LOGIC_1164.all; 11034library SYNOPSYS; 11035use SYNOPSYS.attributes.REAL_NAME; 11036 11037-- entity declaration -- 11038entity ts_x8 is 11039 generic( 11040 Timing_mesg: Boolean := True; 11041 Timing_xgen: Boolean := False; 11042 tpdcmd_q_R : Time := 0.626 ns; 11043 tpdcmd_q_F : Time := 0.466 ns; 11044 tpdcmd_q_LZ : Time := 0.626 ns; 11045 tpdcmd_q_HZ : Time := 0.466 ns; 11046 tpdi_q_R : Time := 0.613 ns; 11047 tpdi_q_F : Time := 0.569 ns; 11048 twdi_R : Time := 0.000 ns; 11049 twdi_F : Time := 0.000 ns; 11050 twdcmd_R : Time := 0.000 ns; 11051 twdcmd_F : Time := 0.000 ns); 11052 11053 port( 11054 i : in STD_LOGIC; 11055 cmd : in STD_LOGIC; 11056 q : out STD_LOGIC); 11057end ts_x8; 11058 11059-- architecture body -- 11060library IEEE_ASIC; 11061use IEEE.STD_LOGIC_MISC.all; 11062use SYNOPSYS.attributes.backplane; 11063use SYNOPSYS.attributes.PRIVATE; 11064use SYNOPSYS.attributes.ASIC_CELL; 11065use SYNOPSYS.attributes.PROPAGATE_VALUE; 11066 11067architecture FTSM of ts_x8 is 11068 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 11069 attribute PRIVATE of FTSM : architecture is TRUE; 11070 attribute ASIC_CELL of FTSM : architecture is TRUE; 11071 11072 -- Backannotation attributes 11073 attribute PROPAGATE_VALUE of tpdi_q_R: constant is "U4/tLH"; 11074 attribute PROPAGATE_VALUE of tpdi_q_F: constant is "U4/tHL"; 11075 attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is "U3/tHL, U3/tLH"; 11076 attribute PROPAGATE_VALUE of tpdcmd_q_HZ: constant is "U3/tLH, U3/tHL"; 11077 attribute PROPAGATE_VALUE of tpdcmd_q_LZ: constant is "U3/tLH, U3/tHL"; 11078 attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is "U3/tLH, U3/tHL"; 11079 attribute PROPAGATE_VALUE of twdcmd_F: constant is "U2/tHL"; 11080 attribute PROPAGATE_VALUE of twdcmd_R: constant is "U2/tLH"; 11081 attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; 11082 attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; 11083 11084 signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 11085 signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 11086 11087 component BUF3SHEMAC 11088 generic( 11089 tpdY_R : Time := 0 ns; 11090 tpdY_F : Time := 0 ns; 11091 strn : STRENGTH := strn_X01); 11092 port( 11093 I0 : in STD_LOGIC; 11094 OE : in STD_LOGIC; 11095 Y : out STD_LOGIC); 11096 end component; 11097 11098begin 11099 11100 -- Extrinsic delay buffers 11101 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 11102 generic map( tLH => twdi_R, tHL => twdi_F) 11103 port map( Input => i, Output => connect(1)); 11104 11105 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 11106 generic map( tLH => twdcmd_R, tHL => twdcmd_F) 11107 port map( Input => cmd, Output => connect(0)); 11108 11109 -- Intrinsic delay buffers 11110 U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 11111 generic map( tLH => tpdcmd_q_R, tHL => tpdcmd_q_R) 11112 port map( Input => connect(0), Output => prop_q(0)); 11113 11114 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 11115 generic map( tLH => tpdi_q_R, tHL => tpdi_q_F) 11116 port map( Input => connect(1), Output => prop_q(1)); 11117 11118 -- Netlist 11119 U5 : BUF3SHEMAC 11120 port map( I0 => prop_q(1), OE => prop_q(0), Y => q); 11121 11122 11123end FTSM; 11124 11125configuration CFG_ts_x8_FTSM of ts_x8 is 11126 for FTSM 11127 end for; 11128end CFG_ts_x8_FTSM; 11129 11130 11131----- CELL xr2_x1 ----- 11132library IEEE; 11133use IEEE.STD_LOGIC_1164.all; 11134library SYNOPSYS; 11135use SYNOPSYS.attributes.REAL_NAME; 11136 11137-- entity declaration -- 11138entity xr2_x1 is 11139 generic( 11140 Timing_mesg: Boolean := True; 11141 Timing_xgen: Boolean := False; 11142 tpdi0_q_R : Time := 0.292 ns; 11143 tpdi0_q_F : Time := 0.293 ns; 11144 tpdi1_q_R : Time := 0.377 ns; 11145 tpdi1_q_F : Time := 0.261 ns; 11146 twdi0_R : Time := 0.000 ns; 11147 twdi0_F : Time := 0.000 ns; 11148 twdi1_R : Time := 0.000 ns; 11149 twdi1_F : Time := 0.000 ns); 11150 11151 port( 11152 i0 : in STD_LOGIC; 11153 i1 : in STD_LOGIC; 11154 q : out STD_LOGIC); 11155end xr2_x1; 11156 11157-- architecture body -- 11158library IEEE_ASIC; 11159use IEEE.STD_LOGIC_MISC.all; 11160use SYNOPSYS.attributes.backplane; 11161use SYNOPSYS.attributes.PRIVATE; 11162use SYNOPSYS.attributes.ASIC_CELL; 11163use SYNOPSYS.attributes.PROPAGATE_VALUE; 11164 11165architecture FTSM of xr2_x1 is 11166 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 11167 attribute PRIVATE of FTSM : architecture is TRUE; 11168 attribute ASIC_CELL of FTSM : architecture is TRUE; 11169 11170 -- Backannotation attributes 11171 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tLH"; 11172 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tHL"; 11173 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tLH"; 11174 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tHL"; 11175 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 11176 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 11177 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 11178 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 11179 11180 signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 11181 signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 11182 11183 component XOR2MAC 11184 generic( 11185 tpdY_R : Time := 0 ns; 11186 tpdY_F : Time := 0 ns; 11187 strn : STRENGTH := strn_X01); 11188 port( 11189 I0 : in STD_LOGIC; 11190 I1 : in STD_LOGIC; 11191 Y : out STD_LOGIC); 11192 end component; 11193 11194begin 11195 11196 -- Extrinsic delay buffers 11197 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 11198 generic map( tLH => twdi0_R, tHL => twdi0_F) 11199 port map( Input => i0, Output => connect(0)); 11200 11201 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 11202 generic map( tLH => twdi1_R, tHL => twdi1_F) 11203 port map( Input => i1, Output => connect(1)); 11204 11205 -- Intrinsic delay buffers 11206 U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 11207 generic map( tLH => tpdi0_q_F, tHL => tpdi0_q_R) 11208 port map( Input => connect(0), Output => prop_q(0)); 11209 11210 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 11211 generic map( tLH => tpdi1_q_F, tHL => tpdi1_q_R) 11212 port map( Input => connect(1), Output => prop_q(1)); 11213 11214 -- Netlist 11215 U5 : XOR2MAC 11216 port map( I0 => prop_q(1), I1 => prop_q(0), Y => q); 11217 11218 11219end FTSM; 11220 11221configuration CFG_xr2_x1_FTSM of xr2_x1 is 11222 for FTSM 11223 end for; 11224end CFG_xr2_x1_FTSM; 11225 11226 11227----- CELL xr2_x4 ----- 11228library IEEE; 11229use IEEE.STD_LOGIC_1164.all; 11230library SYNOPSYS; 11231use SYNOPSYS.attributes.REAL_NAME; 11232 11233-- entity declaration -- 11234entity xr2_x4 is 11235 generic( 11236 Timing_mesg: Boolean := True; 11237 Timing_xgen: Boolean := False; 11238 tpdi0_q_R : Time := 0.521 ns; 11239 tpdi0_q_F : Time := 0.560 ns; 11240 tpdi1_q_R : Time := 0.541 ns; 11241 tpdi1_q_F : Time := 0.657 ns; 11242 twdi0_R : Time := 0.000 ns; 11243 twdi0_F : Time := 0.000 ns; 11244 twdi1_R : Time := 0.000 ns; 11245 twdi1_F : Time := 0.000 ns); 11246 11247 port( 11248 i0 : in STD_LOGIC; 11249 i1 : in STD_LOGIC; 11250 q : out STD_LOGIC); 11251end xr2_x4; 11252 11253-- architecture body -- 11254library IEEE_ASIC; 11255use IEEE.STD_LOGIC_MISC.all; 11256use SYNOPSYS.attributes.backplane; 11257use SYNOPSYS.attributes.PRIVATE; 11258use SYNOPSYS.attributes.ASIC_CELL; 11259use SYNOPSYS.attributes.PROPAGATE_VALUE; 11260 11261architecture FTSM of xr2_x4 is 11262 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 11263 attribute PRIVATE of FTSM : architecture is TRUE; 11264 attribute ASIC_CELL of FTSM : architecture is TRUE; 11265 11266 -- Backannotation attributes 11267 attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tLH"; 11268 attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tHL"; 11269 attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tLH"; 11270 attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tHL"; 11271 attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; 11272 attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; 11273 attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; 11274 attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; 11275 11276 signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 11277 signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); 11278 11279 component XOR2MAC 11280 generic( 11281 tpdY_R : Time := 0 ns; 11282 tpdY_F : Time := 0 ns; 11283 strn : STRENGTH := strn_X01); 11284 port( 11285 I0 : in STD_LOGIC; 11286 I1 : in STD_LOGIC; 11287 Y : out STD_LOGIC); 11288 end component; 11289 11290begin 11291 11292 -- Extrinsic delay buffers 11293 U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 11294 generic map( tLH => twdi0_R, tHL => twdi0_F) 11295 port map( Input => i0, Output => connect(0)); 11296 11297 U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE 11298 generic map( tLH => twdi1_R, tHL => twdi1_F) 11299 port map( Input => i1, Output => connect(1)); 11300 11301 -- Intrinsic delay buffers 11302 U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 11303 generic map( tLH => tpdi0_q_F, tHL => tpdi0_q_R) 11304 port map( Input => connect(0), Output => prop_q(0)); 11305 11306 U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE 11307 generic map( tLH => tpdi1_q_F, tHL => tpdi1_q_R) 11308 port map( Input => connect(1), Output => prop_q(1)); 11309 11310 -- Netlist 11311 U5 : XOR2MAC 11312 port map( I0 => prop_q(1), I1 => prop_q(0), Y => q); 11313 11314 11315end FTSM; 11316 11317configuration CFG_xr2_x4_FTSM of xr2_x4 is 11318 for FTSM 11319 end for; 11320end CFG_xr2_x4_FTSM; 11321 11322 11323----- CELL zero_x0 ----- 11324library IEEE; 11325use IEEE.STD_LOGIC_1164.all; 11326library SYNOPSYS; 11327use SYNOPSYS.attributes.REAL_NAME; 11328 11329-- entity declaration -- 11330entity zero_x0 is 11331 generic( 11332 Timing_mesg: Boolean := True; 11333 Timing_xgen: Boolean := False); 11334 11335 port( 11336 nq : out STD_LOGIC := '0'); 11337end zero_x0; 11338 11339-- architecture body -- 11340library IEEE_ASIC; 11341use IEEE.STD_LOGIC_MISC.all; 11342use SYNOPSYS.attributes.backplane; 11343use SYNOPSYS.attributes.PRIVATE; 11344use SYNOPSYS.attributes.ASIC_CELL; 11345use SYNOPSYS.attributes.PROPAGATE_VALUE; 11346 11347architecture FTSM of zero_x0 is 11348 attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; 11349 attribute PRIVATE of FTSM : architecture is TRUE; 11350 attribute ASIC_CELL of FTSM : architecture is TRUE; 11351 11352 -- Backannotation attributes 11353 11354 11355begin 11356 11357 -- Netlist 11358 nq <= '0'; 11359 11360end FTSM; 11361 11362configuration CFG_zero_x0_FTSM of zero_x0 is 11363 for FTSM 11364 end for; 11365end CFG_zero_x0_FTSM; 11366 11367 11368---- end of library ---- 11369