1 /* ###--------------------------------------------------------------### */
2 /* */
3 /* file : mvl_drive.c */
4 /* date : Sep 24 1993 */
5 /* author : VUONG Huu Nghia, D. Hommais */
6 /* description : This file contains a MBK-->VHDL driver : */
7 /* functions : vhdlsavelofig() */
8 /* */
9 /* ###--------------------------------------------------------------### */
10 #ident "$Id: mvl_drive.c,v 1.2 2006/03/29 17:10:38 xtof Exp $"
11 #include <stdio.h>
12 #include <stdlib.h>
13 #include <string.h>
14 #include <sys/types.h>
15 #include <time.h>
16 #include <mut.h>
17 #include <mlo.h>
18 #include "gen_generic.h"
19 #include "mvl_utype.h"
20 #include "mvl_utdef.h"
21 #include "mvl_drive.h"
22
drv_genvalue(FILE * ptfile,logen_list * ptgen)23 static void drv_genvalue(FILE *ptfile, logen_list *ptgen)
24 {
25 logen_list *l;
26
27 switch (ptgen->TYPE) {
28 case GENTYPE_BIT:
29 fprintf(ptfile, "'%c'", ptgen->VALUE.CHAR);
30 break;
31 case GENTYPE_VAL:
32 fprintf(ptfile, "%ld", ptgen->VALUE.VAL);
33 break;
34 case GENTYPE_ARG:
35 fprintf(ptfile, "%ld", ptgen->VALUE.VAL);
36 break;
37 case GENTYPE_TEXT:
38 fputs(ptgen->VALUE.TEXT, ptfile);
39 break;
40 case GENTYPE_LIST:
41 fputc('(', ptfile);
42 for (l=ptgen->VALUE.LIST; l; l=l->NEXT) {
43 drv_genvalue(ptfile, l);
44 if (l->NEXT)
45 fputc(',', ptfile);
46 }
47 fputc(')', ptfile);
48 break;
49 }
50 }
51
drv_generic(FILE * ptfile,ptype_list * pttype)52 static void drv_generic(FILE *ptfile, ptype_list *pttype)
53 {
54 struct logen *ptgen;
55
56 if ( (pttype=getptype(pttype,LOGEN)) ) {
57 fprintf (ptfile," generic (\n");
58 for (ptgen=pttype->DATA;ptgen;ptgen=ptgen->NEXT) {
59 fprintf (ptfile," CONSTANT %s : ",ptgen->NAME);
60 switch(ptgen->TYPE) {
61 case GENTYPE_BIT:
62 fputs("bit := ", ptfile);
63 break;
64 case GENTYPE_VAL:
65 fputs("natural := ", ptfile);
66 break;
67 case GENTYPE_ARG:
68 fputs("arg := ", ptfile);
69 break;
70 case GENTYPE_TEXT:
71 fputs("string := ", ptfile);
72 break;
73 case GENTYPE_LIST:
74 fputs("list := ", ptfile);
75 break;
76 }
77 drv_genvalue(ptfile, ptgen);
78 if (ptgen->NEXT)
79 fputs(";\n",ptfile);
80 }
81 fputs("\n );\n",ptfile);
82 }
83 }
84
85 /* ###--------------------------------------------------------------### */
86 /* function : vhdlsavelofig */
87 /* description : print out a texte file containing a structural VHDL */
88 /* description */
89 /* called func. : mvl_vhdlname , getsigname, mvl_message, mvl_error ,*/
90 /* mvl_toolbug, getptype, reverse, mvl_abl2str */
91 /* */
92 /* ###--------------------------------------------------------------### */
xxvhdlsavelofig(ptfig)93 void xxvhdlsavelofig (ptfig)
94
95 struct lofig *ptfig;
96 {
97 extern char *getsigname ();
98 struct loins *ptins = NULL;
99 struct locon *ptcon = NULL;
100 struct locon *ptscan = NULL;
101 struct losig *ptsig = NULL;
102 struct chain *ptmodel = NULL;
103 struct chain *ptchain = NULL;
104 struct chain *sig_list = NULL;
105 FILE *ptfile ;
106 time_t clock ;
107 char *mode = NULL;
108 char *name ;
109 char *sig_name ;
110 int left ;
111 int right ;
112 int i ;
113 char new_name[200];
114 char first = 1 ;
115
116 if (ptfig == NULL)
117 mvl_toolbug (10, "mvl_decomp", NULL, 0);
118
119 /* ###------------------------------------------------------### */
120 /* Opening result file */
121 /* ###------------------------------------------------------### */
122
123 if ((ptfile = mbkfopen (ptfig->NAME, "vst", "w")) == NULL)
124 {
125 mvl_error (107, NULL);
126 exit (1);
127 }
128
129 time (&clock);
130 fprintf (ptfile,"-- VHDL structural description generated from `%s`\n",
131 ptfig->NAME);
132 fprintf (ptfile,"--\t\tdate : %s\n\n",ctime(&clock));
133
134 /* ###------------------------------------------------------### */
135 /* Entity declaration */
136 /* ###------------------------------------------------------### */
137
138 fprintf (ptfile,"-- Entity Declaration\n\n");
139 fprintf (ptfile,"ENTITY %s IS\n", mvl_vhdlname (ptfig->NAME));
140
141 /* ###------------------------------------------------------### */
142 /* Generic declaration */
143 /* ###------------------------------------------------------### */
144
145 drv_generic(ptfile, ptfig->USER);
146
147 /* ###------------------------------------------------------### */
148 /* Port declaration */
149 /* ###------------------------------------------------------### */
150
151 if (ptfig->LOCON != NULL)
152 {
153 fprintf (ptfile," PORT (\n");
154 ptfig->LOCON = (struct locon *) reverse ((chain_list *)ptfig->LOCON);
155 ptcon = ptfig->LOCON;
156 while (ptcon != NULL)
157 {
158 switch (ptcon->DIRECTION)
159 {
160 case 'I':
161 mode = namealloc ("in");
162 break;
163 case 'O':
164 mode = namealloc ("out");
165 break;
166 case 'B':
167 mode = namealloc ("inout");
168 break;
169 case 'Z':
170 case 'T':
171 case 'X':
172 mode = namealloc ("linkage");
173 break;
174 }
175 ptcon = (struct locon *) mvl_vectnam (ptcon,&left,&right,&name,1);
176 if (left != -1)
177 {
178 fprintf (ptfile," %s : %s BIT_VECTOR (%d %s %d)",
179 mvl_vhdlname (name), mode, left,
180 (left >= right)? "DOWNTO":"TO",right);
181 }
182 else
183 {
184 fprintf (ptfile," %s : %s BIT",mvl_vhdlname(name),mode);
185 }
186
187 if (ptcon->NEXT != NULL)
188 fprintf (ptfile,";\t-- %s\n",name);
189 else
190 fprintf (ptfile,"\t-- %s\n",name);
191
192 ptcon = ptcon->NEXT;
193 mbkfree (name);
194 }
195 fprintf (ptfile, " );\n");
196 }
197 fprintf (ptfile,"END %s;\n\n",mvl_vhdlname(ptfig->NAME));
198 ptfig->LOCON = (struct locon *) reverse ((chain_list *)ptfig->LOCON);
199
200 /* ###------------------------------------------------------### */
201 /* Architecture declaration */
202 /* ###------------------------------------------------------### */
203
204 fprintf (ptfile,"-- Architecture Declaration\n\n");
205 fprintf (ptfile,"ARCHITECTURE structural_view OF %s IS\n",
206 mvl_vhdlname(ptfig->NAME));
207
208 /* ###------------------------------------------------------### */
209 /* Component declaration : first make a list of models, then */
210 /* for each model print out a "component declaration" */
211 /* ###------------------------------------------------------### */
212
213 ptmodel = NULL;
214 for (ptins = ptfig->LOINS; ptins; ptins = ptins->NEXT)
215 {
216 for (ptchain = ptmodel ; ptchain ; ptchain = ptchain->NEXT)
217 {
218 if (((struct loins *)ptchain->DATA)->FIGNAME == ptins->FIGNAME)
219 break;
220 }
221 if (ptchain == NULL)
222 ptmodel = addchain(ptmodel,ptins);
223 }
224
225 for (ptchain = ptmodel ; ptchain ; ptchain = ptchain->NEXT)
226 {
227 ptins = (struct loins *)ptchain->DATA;
228 fprintf (ptfile," COMPONENT %s\n",
229 mvl_vhdlname(ptins->FIGNAME));
230
231 /* ###------------------------------------------------------------### */
232 /* For each model, I just look for an instance and write the generic */
233 /* list. So the default value for a generic of the model is the value */
234 /* of the first found instance generic. */
235 /* ###------------------------------------------------------------### */
236
237 drv_generic(ptfile, ((loins_list *)ptchain->DATA)->USER);
238
239 fputs(" port (\n",ptfile);
240
241 ptins->LOCON = (struct locon *) reverse ((chain_list *)ptins->LOCON);
242 ptcon = ptins->LOCON;
243 while (ptcon != NULL)
244 {
245 switch (ptcon->DIRECTION)
246 {
247 case 'I':
248 mode = namealloc ("in");
249 break;
250 case 'O':
251 mode = namealloc ("out");
252 break;
253 case 'B':
254 mode = namealloc ("inout");
255 break;
256 case 'Z':
257 case 'T':
258 case 'X':
259 mode = namealloc ("linkage");
260 break;
261 }
262 ptcon = (struct locon *) mvl_vectnam (ptcon,&left,&right,&name,1);
263 if (left != -1)
264 {
265 fprintf (ptfile," %s : %s BIT_VECTOR(%d %s %d)",
266 mvl_vhdlname(name), mode, left,
267 (left >= right)?"DOWNTO":"TO",right);
268 }
269 else
270 fprintf(ptfile," %s : %s BIT", mvl_vhdlname(name),mode);
271
272 if (ptcon->NEXT != NULL)
273 fprintf(ptfile, ";\t-- %s\n",name);
274 else
275 fprintf(ptfile, "\t-- %s\n",name);
276
277 ptcon = ptcon->NEXT;
278 free(name);
279 }
280 ptins->LOCON = (struct locon *) reverse ((chain_list *)ptins->LOCON);
281 fprintf (ptfile, " );\n END COMPONENT;\n\n");
282 }
283
284 freechain (ptmodel);
285
286 /* ###------------------------------------------------------### */
287 /* Signal declaration */
288 /* ###------------------------------------------------------### */
289
290 ptsig = ptfig->LOSIG;
291 while (ptsig != NULL)
292 {
293 if (ptsig->TYPE == 'I')
294 {
295 fprintf (ptfile," SIGNAL %s : BIT;\t-- %s\n",
296 mvl_vhdlname(getsigname(ptsig)),getsigname(ptsig));
297 }
298 ptsig = ptsig->NEXT;
299 }
300
301 /* ###------------------------------------------------------### */
302 /* Description block */
303 /* ###------------------------------------------------------### */
304
305 fprintf (ptfile,"\nBEGIN\n\n");
306 ptfig->LOINS = (struct loins *) reverse ((chain_list *)ptfig->LOINS);
307
308 for (ptins = ptfig->LOINS; ptins; ptins = ptins->NEXT)
309 {
310 /* ###------------------------------------------------------### */
311 /* Instantiation of a model */
312 /* ###------------------------------------------------------### */
313
314 fprintf (ptfile," %s : %s\n",
315 mvl_vhdlname(ptins->INSNAME),mvl_vhdlname(ptins->FIGNAME));
316
317 /* ###------------------------------------------------------### */
318 /* Generic map */
319 /* ###------------------------------------------------------### */
320
321 {
322 logen_list *g;
323 ptype_list *p;
324
325 p=getptype(ptins->USER,LOGEN);
326 if (p) {
327 fputs(" Generic Map (\n",ptfile);
328 for (g=p->DATA;g;g=g->NEXT) {
329 fprintf(ptfile," %s => ",g->NAME);
330 drv_genvalue(ptfile, g);
331 if (g->NEXT)
332 fputs(",\n",ptfile);
333 }
334 fputs(" )\n",ptfile);
335 }
336 }
337
338 /* ###------------------------------------------------------### */
339 /* Port map */
340 /* ###------------------------------------------------------### */
341
342 fputs(" PORT MAP (\n",ptfile);
343 ptcon = ptins->LOCON;
344 while (ptcon != NULL)
345 {
346 mvl_vectnam (ptcon,&left,&right,&name,1);
347 fprintf (ptfile," %s => ",mvl_vhdlname (name));
348
349 if (left != -1)
350 {
351 /* ###------------------------------------------------------### */
352 /* The connected signals are bused */
353 /* ###------------------------------------------------------### */
354
355 for (i=abs(left-right) ; i>=0 ; i--)
356 {
357 ptsig = ptcon->SIG;
358 if (ptsig->TYPE == 'I')
359 {
360 /* ###-------------------------------------------------### */
361 /* The signal is internal */
362 /* ###-------------------------------------------------### */
363
364 sig_name = namealloc (mvl_vhdlname(getsigname(ptsig)));
365 sig_list = addchain (sig_list, sig_name);
366 }
367 else
368 {
369 /* ###-------------------------------------------------### */
370 /* The signal is external */
371 /* ###-------------------------------------------------### */
372
373 for (ptscan = ptfig->LOCON ; ptscan ; ptscan = ptscan->NEXT)
374 {
375 if (ptscan->SIG == ptsig)
376 break;
377 }
378 if (ptscan == NULL)
379 {
380 printf ("\n*** mbk error *** no external connector \n");
381 printf (" driving vhdl file %s\n", ptfig->NAME);
382 }
383 else
384 {
385 mvl_name (ptscan->NAME,new_name);
386 sig_name = namealloc (new_name);
387 sig_list = addchain (sig_list, sig_name);
388 }
389 }
390 if (i > 0)
391 ptcon = ptcon->NEXT;
392 }
393
394 first = 1;
395 while (sig_list != NULL)
396 {
397 if (first != 1)
398 {
399 fprintf (ptfile,"& %s",(char *)(sig_list->DATA));
400 }
401 else
402 {
403 fprintf (ptfile,"%s",(char *)(sig_list->DATA));
404 first = 0;
405 }
406 sig_list = sig_list->NEXT;
407 }
408 }
409 else
410 {
411 /* ###------------------------------------------------------### */
412 /* The connected signals is simple */
413 /* ###------------------------------------------------------### */
414
415 ptsig = ptcon->SIG;
416 if (ptsig->TYPE == 'I')
417 {
418 fprintf (ptfile, "%s", mvl_vhdlname (getsigname(ptsig)));
419 }
420 else
421 {
422 for (ptscan = ptfig->LOCON ; ptscan ; ptscan = ptscan->NEXT)
423 {
424 if (ptscan->SIG == ptsig)
425 break;
426 }
427 if (ptscan == NULL)
428 {
429 printf ("\n*** mbk error *** no external connector \n");
430 printf (" driving vhdl file %s\n", ptfig->NAME);
431 }
432 else
433 {
434 mvl_name (ptscan->NAME,new_name);
435 fprintf(ptfile, "%s", new_name);
436 }
437 }
438 }
439 if (ptcon->NEXT != NULL)
440 fprintf (ptfile, ",\n");
441 ptcon = ptcon->NEXT;
442 free(name);
443 }
444 fprintf(ptfile, ");\n");
445 }
446 ptfig->LOINS = (struct loins *) reverse ((chain_list *)ptfig->LOINS);
447 fprintf (ptfile, "\nend structural_view;\n");
448 fclose (ptfile);
449 }
450