1reg pad = 0; 2wire led; 3 4module foo(x,y); 5 input wire x; 6 output wire y; 7 assign y = x; 8endmodule 9 10foo f(pad, led); 11 12always @(posedge led) begin 13 $write(led); 14 $finish; 15end 16 17initial begin 18 pad = 1; 19end 20