1reg pad = 0; 2wire led; 3 4module foo(x,y); 5 input wire x; 6 output wire y; 7 assign y = x; 8endmodule 9 10module bar(x,y); 11 input wire x; 12 output wire y; 13 wire temp; 14 foo f1(x, temp); 15 foo f2(temp, y); 16endmodule 17 18bar b(pad, led); 19 20always @(posedge led) begin 21 $write(led); 22 $finish; 23end 24 25initial begin 26 pad = 1; 27end 28