1// This used to be a standard library test. But now that we can implement 2// Memories using arrays, this has become an array test. 3 4module Mem#( 5 parameter ADDR_SIZE = 4, 6 parameter BYTE_SIZE = 8 7)( 8 input wire clock, 9 input wire wen, 10 input wire[ADDR_SIZE-1:0] raddr1, 11 output wire[BYTE_SIZE-1:0] rdata1, 12 input wire[ADDR_SIZE-1:0] waddr, 13 input wire[BYTE_SIZE-1:0] wdata 14); 15 reg[BYTE_SIZE-1:0] mem[ADDR_SIZE-1:0]; 16 assign rdata1 = mem[raddr1]; 17 always @(posedge clock) 18 if (wen) 19 mem[waddr] <= wdata; 20endmodule 21 22reg[3:0] COUNT = 0; 23wire[7:0] rd1; 24 25Mem#(2,8) mem1( 26 .clock(clock.val), 27 .wen(1), 28 .raddr1(0), 29 .rdata1(rd1), 30 .waddr(0), 31 .wdata(rd1 + 1) 32); 33 34always @(posedge clock.val) begin 35 COUNT <= COUNT + 1; 36 if (COUNT == 8) begin 37 $finish; 38 end else begin 39 $write("%h", rd1); 40 end 41end 42