1LIBRARY ieee;
2USE ieee.std_logic_1164.all;
3USE ieee.numeric_std.all;
4
5entity DIG_RAMDualAccess is
6  generic (
7    Bits : integer;       <? vhdl.registerGeneric("Bits");?>
8    AddrBits : integer ); <? vhdl.registerGeneric("AddrBits");?>
9  port (
10    n1D: out std_logic_vector ((Bits-1) downto 0);
11    n2D: out std_logic_vector ((Bits-1) downto 0);
12    str: in std_logic;
13    C: in std_logic;
14    ld: in std_logic;
15    n1A: in std_logic_vector ((AddrBits-1) downto 0);
16    n1Din: in std_logic_vector ((Bits-1) downto 0);
17    n2A: in std_logic_vector ((AddrBits-1) downto 0) );
18end DIG_RAMDualAccess;
19
20architecture Behavioral of DIG_RAMDualAccess is
21    -- CAUTION: uses distributed RAM
22    type memoryType is array(0 to (2**AddrBits)-1) of STD_LOGIC_VECTOR((Bits-1) downto 0);
23    signal memory : memoryType;
24begin
25  process ( C )
26  begin
27    if rising_edge(C) AND (str='1') then
28      memory(to_integer(unsigned(n1A))) <= n1Din;
29    end if;
30  end process;
31  n1D <= memory(to_integer(unsigned(n1A))) when ld='1' else (others => 'Z');
32  n2D <= memory(to_integer(unsigned(n2A)));
33end Behavioral;
34