1 /* 2 * Copyright (c) 2018 Helmut Neemann. 3 * Use of this source code is governed by the GPL v3 license 4 * that can be found in the LICENSE file. 5 */ 6 package de.neemann.digital.hdl.vhdl2; 7 8 import de.neemann.digital.hdl.model2.HDLCircuit; 9 import de.neemann.digital.hdl.model2.HDLModel; 10 import de.neemann.digital.hdl.model2.clock.ClockIntegratorGeneric; 11 import de.neemann.digital.hdl.model2.clock.HDLClockIntegrator; 12 import de.neemann.digital.hdl.printer.CodePrinter; 13 import de.neemann.digital.hdl.printer.CodePrinterStr; 14 import de.neemann.digital.integration.ToBreakRunner; 15 import junit.framework.TestCase; 16 17 public class ClockTest extends TestCase { 18 testGeneric()19 public void testGeneric() throws Exception { 20 String code = create(new ClockIntegratorGeneric(10)); 21 22 assertEquals("\n" + 23 "LIBRARY ieee;\n" + 24 "USE ieee.std_logic_1164.all;\n" + 25 "USE ieee.numeric_std.all;\n" + 26 "USE ieee.std_logic_unsigned.all;\n" + 27 "\n" + 28 "entity DIG_simpleClockDivider is\n" + 29 " generic (\n" + 30 " maxCounter : integer ); \n" + 31 " port (\n" + 32 " cout: out std_logic;\n" + 33 " cin: in std_logic );\n" + 34 "end DIG_simpleClockDivider;\n" + 35 "\n" + 36 "architecture Behavioral of DIG_simpleClockDivider is\n" + 37 " -- Don't use a logic signal as clock source in a real world application!\n" + 38 " -- Use the on chip clock resources instead!\n" + 39 " signal counter: integer range 0 to maxCounter := 0;\n" + 40 " signal state: std_logic;\n" + 41 "begin\n" + 42 " process (cin)\n" + 43 " begin\n" + 44 " if rising_edge(cin) then\n" + 45 " if counter = maxCounter then\n" + 46 " counter <= 0;\n" + 47 " state <= NOT (state);\n" + 48 " else\n" + 49 " counter <= counter+1;\n" + 50 " end if;\n" + 51 " end if;\n" + 52 " end process;\n" + 53 " cout <= state;\n" + 54 "end Behavioral;\n" + 55 "\n" + 56 "\n" + 57 "LIBRARY ieee;\n" + 58 "USE ieee.std_logic_1164.all;\n" + 59 "\n" + 60 "entity DIG_D_FF is\n" + 61 " generic (\n" + 62 " Default: std_logic ); \n" + 63 " port ( D : in std_logic;\n" + 64 " C : in std_logic;\n" + 65 " Q : out std_logic;\n" + 66 " notQ : out std_logic );\n" + 67 "end DIG_D_FF;\n" + 68 "\n" + 69 "architecture Behavioral of DIG_D_FF is\n" + 70 " signal state : std_logic := Default;\n" + 71 "begin\n" + 72 " Q <= state;\n" + 73 " notQ <= NOT( state );\n" + 74 "\n" + 75 " process(C)\n" + 76 " begin\n" + 77 " if rising_edge(C) then\n" + 78 " state <= D;\n" + 79 " end if;\n" + 80 " end process;\n" + 81 "end Behavioral;\n" + 82 "\n" + 83 "\n" + 84 "LIBRARY ieee;\n" + 85 "USE ieee.std_logic_1164.all;\n" + 86 "USE ieee.numeric_std.all;\n" + 87 "\n" + 88 "entity main is\n" + 89 " port (\n" + 90 " A: in std_logic;\n" + 91 " C: in std_logic;\n" + 92 " X: out std_logic);\n" + 93 "end main;\n" + 94 "\n" + 95 "architecture Behavioral of main is\n" + 96 " signal s0: std_logic;\n" + 97 "begin\n" + 98 " gate0: entity work.DIG_simpleClockDivider\n" + 99 " generic map (\n" + 100 " maxCounter => 50)\n" + 101 " port map (\n" + 102 " cin => C,\n" + 103 " cout => s0);\n" + 104 " gate1: entity work.DIG_D_FF\n" + 105 " generic map (\n" + 106 " Default => '0')\n" + 107 " port map (\n" + 108 " D => A,\n" + 109 " C => s0,\n" + 110 " Q => X);\n" + 111 "end Behavioral;\n", code); 112 } 113 create(HDLClockIntegrator ci)114 String create(HDLClockIntegrator ci) throws Exception { 115 ToBreakRunner br = new ToBreakRunner("dig/hdl/model2/clock.dig"); 116 HDLCircuit c = new HDLCircuit( 117 br.getCircuit(), "main", 118 new HDLModel(br.getLibrary()), 119 0, ci); 120 121 c.applyDefaultOptimizations(); 122 123 CodePrinter out = new CodePrinterStr(); 124 new VHDLCreator(out, br.getLibrary()).printHDLCircuit(c); 125 126 return out.toString(); 127 } 128 129 } 130