1-- -------------------------------------------------------------------- 2-- COPYRIGHT 1993-1996 BY THE INSTITUTE OF ELECTRICAL AND ELECTRONICS 3-- ENGINEERS, INC. 4-- 345 EAST 47TH STREET 5-- NEW YOPRK, NY 10017, USA 6-- ALL RIGHTS RESERVED 7-- -------------------------------------------------------------------- 8-- -------------------------------------------------------------------- 9-- 10-- Title : std_logic_1164 multi-value logic system 11-- Library : This package shall be compiled into a library 12-- : symbolically named IEEE. 13-- : 14-- Developers: IEEE model standards group (par 1164) 15-- Purpose : This packages defines a standard for designers 16-- : to use in describing the interconnection data types 17-- : used in vhdl modeling. 18-- : 19-- Limitation: The logic system defined in this package may 20-- : be insufficient for modeling switched transistors, 21-- : since such a requirement is out of the scope of this 22-- : effort. Furthermore, mathematics, primitives, 23-- : timing standards, etc. are considered orthogonal 24-- : issues as it relates to this package and are therefore 25-- : beyond the scope of this effort. 26-- : 27-- Note : No declarations or definitions shall be included in, 28-- : or excluded from this package. The "package declaration" 29-- : defines the types, subtypes and declarations of 30-- : std_logic_1164. The std_logic_1164 package body shall be 31-- : considered the formal definition of the semantics of 32-- : this package. Tool developers may choose to implement 33-- : the package body in the most efficient manner available 34-- : to them. 35-- : 36-- -------------------------------------------------------------------- 37-- modification history : 38-- -------------------------------------------------------------------- 39-- version | mod. date:| 40-- v4.200 | 01/02/92 | 41-- -------------------------------------------------------------------- 42 43PACKAGE std_logic_1164 IS 44 45 ------------------------------------------------------------------- 46 -- logic state system (unresolved) 47 ------------------------------------------------------------------- 48 TYPE std_ulogic IS ( 'U', -- Uninitialized 49 'X', -- Forcing Unknown 50 '0', -- Forcing 0 51 '1', -- Forcing 1 52 'Z', -- High Impedance 53 'W', -- Weak Unknown 54 'L', -- Weak 0 55 'H', -- Weak 1 56 '-' -- Don't care 57 ); 58 ------------------------------------------------------------------- 59 -- unconstrained array of std_ulogic for use with the resolution function 60 ------------------------------------------------------------------- 61 TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) OF std_ulogic; 62 63 ------------------------------------------------------------------- 64 -- resolution function 65 ------------------------------------------------------------------- 66 FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic; 67 68 69 ------------------------------------------------------------------- 70 -- *** industry standard logic type *** 71 ------------------------------------------------------------------- 72 SUBTYPE std_logic IS resolved std_ulogic; 73 74 ------------------------------------------------------------------- 75 -- unconstrained array of std_logic for use in declaring signal arrays 76 ------------------------------------------------------------------- 77 TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic; 78 79 ------------------------------------------------------------------- 80 -- common subtypes 81 ------------------------------------------------------------------- 82 SUBTYPE X01 IS resolved std_ulogic RANGE 'X' TO '1'; -- ('X','0','1') 83 SUBTYPE X01Z IS resolved std_ulogic RANGE 'X' TO 'Z'; -- ('X','0','1','Z') 84 SUBTYPE UX01 IS resolved std_ulogic RANGE 'U' TO '1'; -- ('U','X','0','1') 85 SUBTYPE UX01Z IS resolved std_ulogic RANGE 'U' TO 'Z'; -- ('U','X','0','1','Z') 86 87 ------------------------------------------------------------------- 88 -- overloaded logical operators 89 ------------------------------------------------------------------- 90 91 FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; 92 FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; 93 FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; 94 FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; 95 FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; 96-- function "xnor" ( l : std_ulogic; r : std_ulogic ) return ux01; 97 FUNCTION "not" ( l : std_ulogic ) RETURN UX01; 98 99 ------------------------------------------------------------------- 100 -- vectorized overloaded logical operators 101 ------------------------------------------------------------------- 102 FUNCTION "and" ( l, r : std_logic_vector ) RETURN std_logic_vector; 103 FUNCTION "and" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; 104 105 FUNCTION "nand" ( l, r : std_logic_vector ) RETURN std_logic_vector; 106 FUNCTION "nand" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; 107 108 FUNCTION "or" ( l, r : std_logic_vector ) RETURN std_logic_vector; 109 FUNCTION "or" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; 110 111 FUNCTION "nor" ( l, r : std_logic_vector ) RETURN std_logic_vector; 112 FUNCTION "nor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; 113 114 FUNCTION "xor" ( l, r : std_logic_vector ) RETURN std_logic_vector; 115 FUNCTION "xor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; 116 117-- ----------------------------------------------------------------------- 118-- Note : The declaration and implementation of the "xnor" function is 119-- specifically commented until at which time the VHDL language has been 120-- officially adopted as containing such a function. At such a point, 121-- the following comments may be removed along with this notice without 122-- further "official" ballotting of this std_logic_1164 package. It is 123-- the intent of this effort to provide such a function once it becomes 124-- available in the VHDL standard. 125-- ----------------------------------------------------------------------- 126-- function "xnor" ( l, r : std_logic_vector ) return std_logic_vector; 127-- function "xnor" ( l, r : std_ulogic_vector ) return std_ulogic_vector; 128 129 FUNCTION "not" ( l : std_logic_vector ) RETURN std_logic_vector; 130 FUNCTION "not" ( l : std_ulogic_vector ) RETURN std_ulogic_vector; 131 132 ------------------------------------------------------------------- 133 -- conversion functions 134 ------------------------------------------------------------------- 135 FUNCTION To_bit ( s : std_ulogic; xmap : BIT := '0') RETURN BIT; 136 FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0') RETURN BIT_VECTOR; 137 FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT := '0') RETURN BIT_VECTOR; 138 139 FUNCTION To_StdULogic ( b : BIT ) RETURN std_ulogic; 140 FUNCTION To_StdLogicVector ( b : BIT_VECTOR ) RETURN std_logic_vector; 141 FUNCTION To_StdLogicVector ( s : std_ulogic_vector ) RETURN std_logic_vector; 142 FUNCTION To_StdULogicVector ( b : BIT_VECTOR ) RETURN std_ulogic_vector; 143 FUNCTION To_StdULogicVector ( s : std_logic_vector ) RETURN std_ulogic_vector; 144 145 ------------------------------------------------------------------- 146 -- strength strippers and type convertors 147 ------------------------------------------------------------------- 148 149 FUNCTION To_X01 ( s : std_logic_vector ) RETURN std_logic_vector; 150 FUNCTION To_X01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector; 151 FUNCTION To_X01 ( s : std_ulogic ) RETURN X01; 152 FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_logic_vector; 153 FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector; 154 FUNCTION To_X01 ( b : BIT ) RETURN X01; 155 156 FUNCTION To_X01Z ( s : std_logic_vector ) RETURN std_logic_vector; 157 FUNCTION To_X01Z ( s : std_ulogic_vector ) RETURN std_ulogic_vector; 158 FUNCTION To_X01Z ( s : std_ulogic ) RETURN X01Z; 159 FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_logic_vector; 160 FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_ulogic_vector; 161 FUNCTION To_X01Z ( b : BIT ) RETURN X01Z; 162 163 FUNCTION To_UX01 ( s : std_logic_vector ) RETURN std_logic_vector; 164 FUNCTION To_UX01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector; 165 FUNCTION To_UX01 ( s : std_ulogic ) RETURN UX01; 166 FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_logic_vector; 167 FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector; 168 FUNCTION To_UX01 ( b : BIT ) RETURN UX01; 169 170 ------------------------------------------------------------------- 171 -- edge detection 172 ------------------------------------------------------------------- 173 FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN; 174 FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN; 175 176 ------------------------------------------------------------------- 177 -- object contains an unknown 178 ------------------------------------------------------------------- 179 FUNCTION Is_X ( s : std_ulogic_vector ) RETURN BOOLEAN; 180 FUNCTION Is_X ( s : std_logic_vector ) RETURN BOOLEAN; 181 FUNCTION Is_X ( s : std_ulogic ) RETURN BOOLEAN; 182 183END std_logic_1164; 184 185-- -------------------------------------------------------------------- 186-- 187-- Title : std_logic_1164 multi-value logic system 188-- Library : This package shall be compiled into a library 189-- : symbolically named IEEE. 190-- : 191-- Developers: IEEE model standards group (par 1164) 192-- Purpose : This packages defines a standard for designers 193-- : to use in describing the interconnection data types 194-- : used in vhdl modeling. 195-- : 196-- Limitation: The logic system defined in this package may 197-- : be insufficient for modeling switched transistors, 198-- : since such a requirement is out of the scope of this 199-- : effort. Furthermore, mathematics, primitives, 200-- : timing standards, etc. are considered orthogonal 201-- : issues as it relates to this package and are therefore 202-- : beyond the scope of this effort. 203-- : 204-- Note : No declarations or definitions shall be included in, 205-- : or excluded from this package. The "package declaration" 206-- : defines the types, subtypes and declarations of 207-- : std_logic_1164. The std_logic_1164 package body shall be 208-- : considered the formal definition of the semantics of 209-- : this package. Tool developers may choose to implement 210-- : the package body in the most efficient manner available 211-- : to them. 212-- : 213-- -------------------------------------------------------------------- 214-- modification history : 215-- -------------------------------------------------------------------- 216-- version | mod. date:| 217-- v4.200 | 01/02/91 | 218-- -------------------------------------------------------------------- 219 220PACKAGE BODY std_logic_1164 IS 221 ------------------------------------------------------------------- 222 -- local types 223 ------------------------------------------------------------------- 224 TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic; 225 TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic; 226 227 ------------------------------------------------------------------- 228 -- resolution function 229 ------------------------------------------------------------------- 230 CONSTANT resolution_table : stdlogic_table := ( 231 -- --------------------------------------------------------- 232 -- | U X 0 1 Z W L H - | | 233 -- --------------------------------------------------------- 234 ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U | 235 ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X | 236 ( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 | 237 ( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 | 238 ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z | 239 ( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W | 240 ( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L | 241 ( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H | 242 ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - | 243 ); 244 245 FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic IS 246 VARIABLE result : std_ulogic := 'Z'; -- weakest state default 247 BEGIN 248 -- the test for a single driver is essential otherwise the 249 -- loop would return 'X' for a single driver of '-' and that 250 -- would conflict with the value of a single driver unresolved 251 -- signal. 252 IF (s'LENGTH = 1) THEN RETURN s(s'LOW); 253 ELSE 254 FOR i IN s'RANGE LOOP 255 result := resolution_table(result, s(i)); 256 END LOOP; 257 END IF; 258 RETURN result; 259 END resolved; 260 261 ------------------------------------------------------------------- 262 -- tables for logical operations 263 ------------------------------------------------------------------- 264 265 -- truth table for "and" function 266 CONSTANT and_table : stdlogic_table := ( 267 -- ---------------------------------------------------- 268 -- | U X 0 1 Z W L H - | | 269 -- ---------------------------------------------------- 270 ( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U | 271 ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X | 272 ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 | 273 ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 | 274 ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z | 275 ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W | 276 ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L | 277 ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H | 278 ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | - | 279 ); 280 281 -- truth table for "or" function 282 CONSTANT or_table : stdlogic_table := ( 283 -- ---------------------------------------------------- 284 -- | U X 0 1 Z W L H - | | 285 -- ---------------------------------------------------- 286 ( 'U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U' ), -- | U | 287 ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X | 288 ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 | 289 ( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 | 290 ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | Z | 291 ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W | 292 ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L | 293 ( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H | 294 ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ) -- | - | 295 ); 296 297 -- truth table for "xor" function 298 CONSTANT xor_table : stdlogic_table := ( 299 -- ---------------------------------------------------- 300 -- | U X 0 1 Z W L H - | | 301 -- ---------------------------------------------------- 302 ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U | 303 ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X | 304 ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 | 305 ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 | 306 ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z | 307 ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W | 308 ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L | 309 ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H | 310 ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - | 311 ); 312 313 -- truth table for "not" function 314 CONSTANT not_table: stdlogic_1d := 315 -- ------------------------------------------------- 316 -- | U X 0 1 Z W L H - | 317 -- ------------------------------------------------- 318 ( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ); 319 320 ------------------------------------------------------------------- 321 -- overloaded logical operators ( with optimizing hints ) 322 ------------------------------------------------------------------- 323 324 FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS 325 BEGIN 326 RETURN (and_table(l, r)); 327 END "and"; 328 329 FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS 330 BEGIN 331 RETURN (not_table ( and_table(l, r))); 332 END "nand"; 333 334 FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS 335 BEGIN 336 RETURN (or_table(l, r)); 337 END "or"; 338 339 FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS 340 BEGIN 341 RETURN (not_table ( or_table( l, r ))); 342 END "nor"; 343 344 FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS 345 BEGIN 346 RETURN (xor_table(l, r)); 347 END "xor"; 348 349-- function "xnor" ( l : std_ulogic; r : std_ulogic ) return ux01 is 350-- begin 351-- return not_table(xor_table(l, r)); 352-- end "xnor"; 353 354 FUNCTION "not" ( l : std_ulogic ) RETURN UX01 IS 355 BEGIN 356 RETURN (not_table(l)); 357 END "not"; 358 359 ------------------------------------------------------------------- 360 -- and 361 ------------------------------------------------------------------- 362 FUNCTION "and" ( l,r : std_logic_vector ) RETURN std_logic_vector IS 363 ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l; 364 ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r; 365 VARIABLE result : std_logic_vector ( 1 TO l'LENGTH ); 366 BEGIN 367 IF ( l'LENGTH /= r'LENGTH ) THEN 368 ASSERT FALSE 369 REPORT "arguments of overloaded 'and' operator are not of the same length" 370 SEVERITY FAILURE; 371 ELSE 372 FOR i IN result'RANGE LOOP 373 result(i) := and_table (lv(i), rv(i)); 374 END LOOP; 375 END IF; 376 RETURN result; 377 END "and"; 378 --------------------------------------------------------------------- 379 FUNCTION "and" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS 380 ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l; 381 ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r; 382 VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH ); 383 BEGIN 384 IF ( l'LENGTH /= r'LENGTH ) THEN 385 ASSERT FALSE 386 REPORT "arguments of overloaded 'and' operator are not of the same length" 387 SEVERITY FAILURE; 388 ELSE 389 FOR i IN result'RANGE LOOP 390 result(i) := and_table (lv(i), rv(i)); 391 END LOOP; 392 END IF; 393 RETURN result; 394 END "and"; 395 ------------------------------------------------------------------- 396 -- nand 397 ------------------------------------------------------------------- 398 FUNCTION "nand" ( l,r : std_logic_vector ) RETURN std_logic_vector IS 399 ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l; 400 ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r; 401 VARIABLE result : std_logic_vector ( 1 TO l'LENGTH ); 402 BEGIN 403 IF ( l'LENGTH /= r'LENGTH ) THEN 404 ASSERT FALSE 405 REPORT "arguments of overloaded 'nand' operator are not of the same length" 406 SEVERITY FAILURE; 407 ELSE 408 FOR i IN result'RANGE LOOP 409 result(i) := not_table(and_table (lv(i), rv(i))); 410 END LOOP; 411 END IF; 412 RETURN result; 413 END "nand"; 414 --------------------------------------------------------------------- 415 FUNCTION "nand" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS 416 ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l; 417 ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r; 418 VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH ); 419 BEGIN 420 IF ( l'LENGTH /= r'LENGTH ) THEN 421 ASSERT FALSE 422 REPORT "arguments of overloaded 'nand' operator are not of the same length" 423 SEVERITY FAILURE; 424 ELSE 425 FOR i IN result'RANGE LOOP 426 result(i) := not_table(and_table (lv(i), rv(i))); 427 END LOOP; 428 END IF; 429 RETURN result; 430 END "nand"; 431 ------------------------------------------------------------------- 432 -- or 433 ------------------------------------------------------------------- 434 FUNCTION "or" ( l,r : std_logic_vector ) RETURN std_logic_vector IS 435 ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l; 436 ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r; 437 VARIABLE result : std_logic_vector ( 1 TO l'LENGTH ); 438 BEGIN 439 IF ( l'LENGTH /= r'LENGTH ) THEN 440 ASSERT FALSE 441 REPORT "arguments of overloaded 'or' operator are not of the same length" 442 SEVERITY FAILURE; 443 ELSE 444 FOR i IN result'RANGE LOOP 445 result(i) := or_table (lv(i), rv(i)); 446 END LOOP; 447 END IF; 448 RETURN result; 449 END "or"; 450 --------------------------------------------------------------------- 451 FUNCTION "or" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS 452 ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l; 453 ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r; 454 VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH ); 455 BEGIN 456 IF ( l'LENGTH /= r'LENGTH ) THEN 457 ASSERT FALSE 458 REPORT "arguments of overloaded 'or' operator are not of the same length" 459 SEVERITY FAILURE; 460 ELSE 461 FOR i IN result'RANGE LOOP 462 result(i) := or_table (lv(i), rv(i)); 463 END LOOP; 464 END IF; 465 RETURN result; 466 END "or"; 467 ------------------------------------------------------------------- 468 -- nor 469 ------------------------------------------------------------------- 470 FUNCTION "nor" ( l,r : std_logic_vector ) RETURN std_logic_vector IS 471 ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l; 472 ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r; 473 VARIABLE result : std_logic_vector ( 1 TO l'LENGTH ); 474 BEGIN 475 IF ( l'LENGTH /= r'LENGTH ) THEN 476 ASSERT FALSE 477 REPORT "arguments of overloaded 'nor' operator are not of the same length" 478 SEVERITY FAILURE; 479 ELSE 480 FOR i IN result'RANGE LOOP 481 result(i) := not_table(or_table (lv(i), rv(i))); 482 END LOOP; 483 END IF; 484 RETURN result; 485 END "nor"; 486 --------------------------------------------------------------------- 487 FUNCTION "nor" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS 488 ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l; 489 ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r; 490 VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH ); 491 BEGIN 492 IF ( l'LENGTH /= r'LENGTH ) THEN 493 ASSERT FALSE 494 REPORT "arguments of overloaded 'nor' operator are not of the same length" 495 SEVERITY FAILURE; 496 ELSE 497 FOR i IN result'RANGE LOOP 498 result(i) := not_table(or_table (lv(i), rv(i))); 499 END LOOP; 500 END IF; 501 RETURN result; 502 END "nor"; 503 --------------------------------------------------------------------- 504 -- xor 505 ------------------------------------------------------------------- 506 FUNCTION "xor" ( l,r : std_logic_vector ) RETURN std_logic_vector IS 507 ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l; 508 ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r; 509 VARIABLE result : std_logic_vector ( 1 TO l'LENGTH ); 510 BEGIN 511 IF ( l'LENGTH /= r'LENGTH ) THEN 512 ASSERT FALSE 513 REPORT "arguments of overloaded 'xor' operator are not of the same length" 514 SEVERITY FAILURE; 515 ELSE 516 FOR i IN result'RANGE LOOP 517 result(i) := xor_table (lv(i), rv(i)); 518 END LOOP; 519 END IF; 520 RETURN result; 521 END "xor"; 522 --------------------------------------------------------------------- 523 FUNCTION "xor" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS 524 ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l; 525 ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r; 526 VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH ); 527 BEGIN 528 IF ( l'LENGTH /= r'LENGTH ) THEN 529 ASSERT FALSE 530 REPORT "arguments of overloaded 'xor' operator are not of the same length" 531 SEVERITY FAILURE; 532 ELSE 533 FOR i IN result'RANGE LOOP 534 result(i) := xor_table (lv(i), rv(i)); 535 END LOOP; 536 END IF; 537 RETURN result; 538 END "xor"; 539-- ------------------------------------------------------------------- 540-- -- xnor 541-- ------------------------------------------------------------------- 542-- ----------------------------------------------------------------------- 543-- Note : The declaration and implementation of the "xnor" function is 544-- specifically commented until at which time the VHDL language has been 545-- officially adopted as containing such a function. At such a point, 546-- the following comments may be removed along with this notice without 547-- further "official" ballotting of this std_logic_1164 package. It is 548-- the intent of this effort to provide such a function once it becomes 549-- available in the VHDL standard. 550-- ----------------------------------------------------------------------- 551-- function "xnor" ( l,r : std_logic_vector ) return std_logic_vector is 552-- alias lv : std_logic_vector ( 1 to l'length ) is l; 553-- alias rv : std_logic_vector ( 1 to r'length ) is r; 554-- variable result : std_logic_vector ( 1 to l'length ); 555-- begin 556-- if ( l'length /= r'length ) then 557-- assert false 558-- report "arguments of overloaded 'xnor' operator are not of the same length" 559-- severity failure; 560-- else 561-- for i in result'range loop 562-- result(i) := not_table(xor_table (lv(i), rv(i))); 563-- end loop; 564-- end if; 565-- return result; 566-- end "xnor"; 567-- --------------------------------------------------------------------- 568-- function "xnor" ( l,r : std_ulogic_vector ) return std_ulogic_vector is 569-- alias lv : std_ulogic_vector ( 1 to l'length ) is l; 570-- alias rv : std_ulogic_vector ( 1 to r'length ) is r; 571-- variable result : std_ulogic_vector ( 1 to l'length ); 572-- begin 573-- if ( l'length /= r'length ) then 574-- assert false 575-- report "arguments of overloaded 'xnor' operator are not of the same length" 576-- severity failure; 577-- else 578-- for i in result'range loop 579-- result(i) := not_table(xor_table (lv(i), rv(i))); 580-- end loop; 581-- end if; 582-- return result; 583-- end "xnor"; 584 585 586 ------------------------------------------------------------------- 587 -- not 588 ------------------------------------------------------------------- 589 FUNCTION "not" ( l : std_logic_vector ) RETURN std_logic_vector IS 590 ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l; 591 VARIABLE result : std_logic_vector ( 1 TO l'LENGTH ) := (OTHERS => 'X'); 592 BEGIN 593 FOR i IN result'RANGE LOOP 594 result(i) := not_table( lv(i) ); 595 END LOOP; 596 RETURN result; 597 END; 598 --------------------------------------------------------------------- 599 FUNCTION "not" ( l : std_ulogic_vector ) RETURN std_ulogic_vector IS 600 ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l; 601 VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH ) := (OTHERS => 'X'); 602 BEGIN 603 FOR i IN result'RANGE LOOP 604 result(i) := not_table( lv(i) ); 605 END LOOP; 606 RETURN result; 607 END; 608 ------------------------------------------------------------------- 609 -- conversion tables 610 ------------------------------------------------------------------- 611 TYPE logic_x01_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF X01; 612 TYPE logic_x01z_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF X01Z; 613 TYPE logic_ux01_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF UX01; 614 ---------------------------------------------------------- 615 -- table name : cvt_to_x01 616 -- 617 -- parameters : 618 -- in : std_ulogic -- some logic value 619 -- returns : x01 -- state value of logic value 620 -- purpose : to convert state-strength to state only 621 -- 622 -- example : if (cvt_to_x01 (input_signal) = '1' ) then ... 623 -- 624 ---------------------------------------------------------- 625 CONSTANT cvt_to_x01 : logic_x01_table := ( 626 'X', -- 'U' 627 'X', -- 'X' 628 '0', -- '0' 629 '1', -- '1' 630 'X', -- 'Z' 631 'X', -- 'W' 632 '0', -- 'L' 633 '1', -- 'H' 634 'X' -- '-' 635 ); 636 637 ---------------------------------------------------------- 638 -- table name : cvt_to_x01z 639 -- 640 -- parameters : 641 -- in : std_ulogic -- some logic value 642 -- returns : x01z -- state value of logic value 643 -- purpose : to convert state-strength to state only 644 -- 645 -- example : if (cvt_to_x01z (input_signal) = '1' ) then ... 646 -- 647 ---------------------------------------------------------- 648 CONSTANT cvt_to_x01z : logic_x01z_table := ( 649 'X', -- 'U' 650 'X', -- 'X' 651 '0', -- '0' 652 '1', -- '1' 653 'Z', -- 'Z' 654 'X', -- 'W' 655 '0', -- 'L' 656 '1', -- 'H' 657 'X' -- '-' 658 ); 659 660 ---------------------------------------------------------- 661 -- table name : cvt_to_ux01 662 -- 663 -- parameters : 664 -- in : std_ulogic -- some logic value 665 -- returns : ux01 -- state value of logic value 666 -- purpose : to convert state-strength to state only 667 -- 668 -- example : if (cvt_to_ux01 (input_signal) = '1' ) then ... 669 -- 670 ---------------------------------------------------------- 671 CONSTANT cvt_to_ux01 : logic_ux01_table := ( 672 'U', -- 'U' 673 'X', -- 'X' 674 '0', -- '0' 675 '1', -- '1' 676 'X', -- 'Z' 677 'X', -- 'W' 678 '0', -- 'L' 679 '1', -- 'H' 680 'X' -- '-' 681 ); 682 683 ------------------------------------------------------------------- 684 -- conversion functions 685 ------------------------------------------------------------------- 686 FUNCTION To_bit ( s : std_ulogic; xmap : BIT := '0') RETURN BIT IS 687 BEGIN 688 CASE s IS 689 WHEN '0' | 'L' => RETURN ('0'); 690 WHEN '1' | 'H' => RETURN ('1'); 691 WHEN OTHERS => RETURN xmap; 692 END CASE; 693 END; 694 -------------------------------------------------------------------- 695 FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0') RETURN BIT_VECTOR IS 696 ALIAS sv : std_logic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s; 697 VARIABLE result : BIT_VECTOR ( s'LENGTH-1 DOWNTO 0 ); 698 BEGIN 699 FOR i IN result'RANGE LOOP 700 CASE sv(i) IS 701 WHEN '0' | 'L' => result(i) := '0'; 702 WHEN '1' | 'H' => result(i) := '1'; 703 WHEN OTHERS => result(i) := xmap; 704 END CASE; 705 END LOOP; 706 RETURN result; 707 END; 708 -------------------------------------------------------------------- 709 FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT := '0') RETURN BIT_VECTOR IS 710 ALIAS sv : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s; 711 VARIABLE result : BIT_VECTOR ( s'LENGTH-1 DOWNTO 0 ); 712 BEGIN 713 FOR i IN result'RANGE LOOP 714 CASE sv(i) IS 715 WHEN '0' | 'L' => result(i) := '0'; 716 WHEN '1' | 'H' => result(i) := '1'; 717 WHEN OTHERS => result(i) := xmap; 718 END CASE; 719 END LOOP; 720 RETURN result; 721 END; 722 -------------------------------------------------------------------- 723 FUNCTION To_StdULogic ( b : BIT ) RETURN std_ulogic IS 724 BEGIN 725 CASE b IS 726 WHEN '0' => RETURN '0'; 727 WHEN '1' => RETURN '1'; 728 END CASE; 729 END; 730 -------------------------------------------------------------------- 731 FUNCTION To_StdLogicVector ( b : BIT_VECTOR ) RETURN std_logic_vector IS 732 ALIAS bv : BIT_VECTOR ( b'LENGTH-1 DOWNTO 0 ) IS b; 733 VARIABLE result : std_logic_vector ( b'LENGTH-1 DOWNTO 0 ); 734 BEGIN 735 FOR i IN result'RANGE LOOP 736 CASE bv(i) IS 737 WHEN '0' => result(i) := '0'; 738 WHEN '1' => result(i) := '1'; 739 END CASE; 740 END LOOP; 741 RETURN result; 742 END; 743 -------------------------------------------------------------------- 744 FUNCTION To_StdLogicVector ( s : std_ulogic_vector ) RETURN std_logic_vector IS 745 ALIAS sv : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s; 746 VARIABLE result : std_logic_vector ( s'LENGTH-1 DOWNTO 0 ); 747 BEGIN 748 FOR i IN result'RANGE LOOP 749 result(i) := sv(i); 750 END LOOP; 751 RETURN result; 752 END; 753 -------------------------------------------------------------------- 754 FUNCTION To_StdULogicVector ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS 755 ALIAS bv : BIT_VECTOR ( b'LENGTH-1 DOWNTO 0 ) IS b; 756 VARIABLE result : std_ulogic_vector ( b'LENGTH-1 DOWNTO 0 ); 757 BEGIN 758 FOR i IN result'RANGE LOOP 759 CASE bv(i) IS 760 WHEN '0' => result(i) := '0'; 761 WHEN '1' => result(i) := '1'; 762 END CASE; 763 END LOOP; 764 RETURN result; 765 END; 766 -------------------------------------------------------------------- 767 FUNCTION To_StdULogicVector ( s : std_logic_vector ) RETURN std_ulogic_vector IS 768 ALIAS sv : std_logic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s; 769 VARIABLE result : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 ); 770 BEGIN 771 FOR i IN result'RANGE LOOP 772 result(i) := sv(i); 773 END LOOP; 774 RETURN result; 775 END; 776 777 ------------------------------------------------------------------- 778 -- strength strippers and type convertors 779 ------------------------------------------------------------------- 780 -- to_x01 781 ------------------------------------------------------------------- 782 FUNCTION To_X01 ( s : std_logic_vector ) RETURN std_logic_vector IS 783 ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s; 784 VARIABLE result : std_logic_vector ( 1 TO s'LENGTH ); 785 BEGIN 786 FOR i IN result'RANGE LOOP 787 result(i) := cvt_to_x01 (sv(i)); 788 END LOOP; 789 RETURN result; 790 END; 791 -------------------------------------------------------------------- 792 FUNCTION To_X01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS 793 ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s; 794 VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH ); 795 BEGIN 796 FOR i IN result'RANGE LOOP 797 result(i) := cvt_to_x01 (sv(i)); 798 END LOOP; 799 RETURN result; 800 END; 801 -------------------------------------------------------------------- 802 FUNCTION To_X01 ( s : std_ulogic ) RETURN X01 IS 803 BEGIN 804 RETURN (cvt_to_x01(s)); 805 END; 806 -------------------------------------------------------------------- 807 FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_logic_vector IS 808 ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b; 809 VARIABLE result : std_logic_vector ( 1 TO b'LENGTH ); 810 BEGIN 811 FOR i IN result'RANGE LOOP 812 CASE bv(i) IS 813 WHEN '0' => result(i) := '0'; 814 WHEN '1' => result(i) := '1'; 815 END CASE; 816 END LOOP; 817 RETURN result; 818 END; 819 -------------------------------------------------------------------- 820 FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS 821 ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b; 822 VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH ); 823 BEGIN 824 FOR i IN result'RANGE LOOP 825 CASE bv(i) IS 826 WHEN '0' => result(i) := '0'; 827 WHEN '1' => result(i) := '1'; 828 END CASE; 829 END LOOP; 830 RETURN result; 831 END; 832 -------------------------------------------------------------------- 833 FUNCTION To_X01 ( b : BIT ) RETURN X01 IS 834 BEGIN 835 CASE b IS 836 WHEN '0' => RETURN('0'); 837 WHEN '1' => RETURN('1'); 838 END CASE; 839 END; 840 -------------------------------------------------------------------- 841 -- to_x01z 842 ------------------------------------------------------------------- 843 FUNCTION To_X01Z ( s : std_logic_vector ) RETURN std_logic_vector IS 844 ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s; 845 VARIABLE result : std_logic_vector ( 1 TO s'LENGTH ); 846 BEGIN 847 FOR i IN result'RANGE LOOP 848 result(i) := cvt_to_x01z (sv(i)); 849 END LOOP; 850 RETURN result; 851 END; 852 -------------------------------------------------------------------- 853 FUNCTION To_X01Z ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS 854 ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s; 855 VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH ); 856 BEGIN 857 FOR i IN result'RANGE LOOP 858 result(i) := cvt_to_x01z (sv(i)); 859 END LOOP; 860 RETURN result; 861 END; 862 -------------------------------------------------------------------- 863 FUNCTION To_X01Z ( s : std_ulogic ) RETURN X01Z IS 864 BEGIN 865 RETURN (cvt_to_x01z(s)); 866 END; 867 -------------------------------------------------------------------- 868 FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_logic_vector IS 869 ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b; 870 VARIABLE result : std_logic_vector ( 1 TO b'LENGTH ); 871 BEGIN 872 FOR i IN result'RANGE LOOP 873 CASE bv(i) IS 874 WHEN '0' => result(i) := '0'; 875 WHEN '1' => result(i) := '1'; 876 END CASE; 877 END LOOP; 878 RETURN result; 879 END; 880 -------------------------------------------------------------------- 881 FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS 882 ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b; 883 VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH ); 884 BEGIN 885 FOR i IN result'RANGE LOOP 886 CASE bv(i) IS 887 WHEN '0' => result(i) := '0'; 888 WHEN '1' => result(i) := '1'; 889 END CASE; 890 END LOOP; 891 RETURN result; 892 END; 893 -------------------------------------------------------------------- 894 FUNCTION To_X01Z ( b : BIT ) RETURN X01Z IS 895 BEGIN 896 CASE b IS 897 WHEN '0' => RETURN('0'); 898 WHEN '1' => RETURN('1'); 899 END CASE; 900 END; 901 -------------------------------------------------------------------- 902 -- to_ux01 903 ------------------------------------------------------------------- 904 FUNCTION To_UX01 ( s : std_logic_vector ) RETURN std_logic_vector IS 905 ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s; 906 VARIABLE result : std_logic_vector ( 1 TO s'LENGTH ); 907 BEGIN 908 FOR i IN result'RANGE LOOP 909 result(i) := cvt_to_ux01 (sv(i)); 910 END LOOP; 911 RETURN result; 912 END; 913 -------------------------------------------------------------------- 914 FUNCTION To_UX01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS 915 ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s; 916 VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH ); 917 BEGIN 918 FOR i IN result'RANGE LOOP 919 result(i) := cvt_to_ux01 (sv(i)); 920 END LOOP; 921 RETURN result; 922 END; 923 -------------------------------------------------------------------- 924 FUNCTION To_UX01 ( s : std_ulogic ) RETURN UX01 IS 925 BEGIN 926 RETURN (cvt_to_ux01(s)); 927 END; 928 -------------------------------------------------------------------- 929 FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_logic_vector IS 930 ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b; 931 VARIABLE result : std_logic_vector ( 1 TO b'LENGTH ); 932 BEGIN 933 FOR i IN result'RANGE LOOP 934 CASE bv(i) IS 935 WHEN '0' => result(i) := '0'; 936 WHEN '1' => result(i) := '1'; 937 END CASE; 938 END LOOP; 939 RETURN result; 940 END; 941 -------------------------------------------------------------------- 942 FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS 943 ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b; 944 VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH ); 945 BEGIN 946 FOR i IN result'RANGE LOOP 947 CASE bv(i) IS 948 WHEN '0' => result(i) := '0'; 949 WHEN '1' => result(i) := '1'; 950 END CASE; 951 END LOOP; 952 RETURN result; 953 END; 954 -------------------------------------------------------------------- 955 FUNCTION To_UX01 ( b : BIT ) RETURN UX01 IS 956 BEGIN 957 CASE b IS 958 WHEN '0' => RETURN('0'); 959 WHEN '1' => RETURN('1'); 960 END CASE; 961 END; 962 963 ------------------------------------------------------------------- 964 -- edge detection 965 ------------------------------------------------------------------- 966 FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS 967 BEGIN 968 RETURN (s'EVENT AND (To_X01(s) = '1') AND 969 (To_X01(s'LAST_VALUE) = '0')); 970 END; 971 972 FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS 973 BEGIN 974 RETURN (s'EVENT AND (To_X01(s) = '0') AND 975 (To_X01(s'LAST_VALUE) = '1')); 976 END; 977 978 ------------------------------------------------------------------- 979 -- object contains an unknown 980 ------------------------------------------------------------------- 981 FUNCTION Is_X ( s : std_ulogic_vector ) RETURN BOOLEAN IS 982 BEGIN 983 FOR i IN s'RANGE LOOP 984 CASE s(i) IS 985 WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE; 986 WHEN OTHERS => NULL; 987 END CASE; 988 END LOOP; 989 RETURN FALSE; 990 END; 991 -------------------------------------------------------------------- 992 FUNCTION Is_X ( s : std_logic_vector ) RETURN BOOLEAN IS 993 BEGIN 994 FOR i IN s'RANGE LOOP 995 CASE s(i) IS 996 WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE; 997 WHEN OTHERS => NULL; 998 END CASE; 999 END LOOP; 1000 RETURN FALSE; 1001 END; 1002 -------------------------------------------------------------------- 1003 FUNCTION Is_X ( s : std_ulogic ) RETURN BOOLEAN IS 1004 BEGIN 1005 CASE s IS 1006 WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE; 1007 WHEN OTHERS => NULL; 1008 END CASE; 1009 RETURN FALSE; 1010 END; 1011 1012END std_logic_1164; 1013