1library ieee;
2use ieee.std_logic_1164.all;
3
4entity bug is
5  port (clk : in std_logic;
6        rst : in std_logic);
7end entity bug;
8
9architecture Behavioral of bug is
10
11  type rc_params is array (natural range <>) of std_logic_vector(7 downto 0);
12  type rc_params_array is array (natural range <>) of rc_params;
13
14  type rc_peripheral_1 is record
15    clk    : std_logic;
16    params : rc_params;
17    enable : std_logic;
18    rd     : std_logic;
19    data   : std_logic_vector(7 downto 0);
20    empty  : std_logic;
21  end record rc_peripheral_1;
22
23  type rc_peripheral_2 is record
24    clk    : std_logic;
25    params : rc_params_array;
26    enable : std_logic;
27    rd     : std_logic;
28    data   : std_logic_vector(7 downto 0);
29    empty  : std_logic;
30  end record rc_peripheral_2;
31
32  signal mysig_ok : rc_params_array(0 to 4)(0 to 4);  -- This is accepted by ghdl
33
34  signal mysig_ok_2 : rc_peripheral_1(params(0 to 4));  -- This is accepted by ghdl
35
36  signal mysig_wrong : rc_peripheral_2(params(0 to 4)(0 to 4));  -- This is not accepted
37
38begin
39
40end architecture Behavioral;
41