1library ieee; 2use ieee.std_logic_1164.all; 3 4entity e is 5end entity; 6 7architecture a of e is 8 type t_rec is record 9 addr : std_logic_vector; 10 end record; 11 12 function init_signals(bits : natural) return t_rec is 13 variable result : t_rec(addr(bits - 1 downto 0)); 14 begin 15 result.addr := (others => '0'); 16 -- result.addr := (result.addr'range => '0'); -- this works 17 return result; 18 end function; 19begin 20end architecture; 21