1library IEEE;
2use IEEE.STD_LOGIC_1164.ALL;
3use ieee.numeric_std.all;
4
5entity Bar is
6  port (
7    a : std_logic
8  );
9end entity Bar;
10
11architecture RTL of Bar is
12
13  signal s_test : std_logic_vector(3 downto 0) := "1111";
14
15begin
16
17end architecture;
18