1library IEEE;
2use IEEE.STD_LOGIC_1164.ALL;
3use ieee.numeric_std.all;
4
5entity foo is
6  port (
7    a : std_logic;
8    b : std_logic_vector(7 downto 0)
9  );
10end entity foo;
11
12architecture RTL of foo is
13
14  signal s_test : std_logic_vector(3 downto 0) := "1111";
15
16begin
17
18  cmp_bar: entity work.bar
19    port map(
20      a => a
21    );
22
23  gen_bars: for i in 0 to 1 generate
24    cmp_generated_bar: entity work.bar
25      port map(
26        a => a
27      );
28  end generate gen_bars;
29
30end architecture;
31