1library ieee; 2use ieee.std_logic_1164.all; 3 4package basicblocks_definitions is 5constant period: time := 10 ns; 6constant half_period: time := period / 2; 7constant reset_time: time := 11 ns; 8end; 9 10library ieee; 11use ieee.std_logic_1164.all; 12 13library work; 14use work.basicblocks_definitions.all; 15 16-- FOR SIMULATION ONLY. NOT FOR PRODUCTION. 17 18entity clkgen is 19port( 20 clk_out: out std_logic; 21 resetn: out std_logic := '0' 22); 23end; 24 25-- Tested 2016/01/19 with ghdl. works. 26 27architecture struct_clkgen of clkgen is 28 29begin 30 process begin 31 32 resetn <= '1' after reset_time; 33 34 clk_out <= '1'; 35 wait for half_period; 36 37 clk_out <= '0'; 38 wait for half_period; 39 end process; 40end; 41 42library ieee; 43use ieee.std_logic_1164.all; 44 45entity incrementer is 46port( 47 input: in std_logic; 48 carry_in: in std_logic; 49 sum: out std_logic; 50 carry_out: out std_logic 51); 52end; 53 54-- tested with ghdl for N = 16 starting 2016/01/22, finished ?, works. 55 56architecture struct_incrementer of incrementer is 57begin 58 sum <= input xor carry_in; 59 carry_out <= input and carry_in; 60end; 61 62library ieee; 63use ieee.std_logic_1164.all; 64 65entity andNbit is 66generic( 67 N: positive 68); 69port( 70 input: in std_logic_vector((N-1) downto 0); 71 y: out std_logic 72); 73end; 74 75-- Tested as part of counter testing. Works. 76 77architecture struct_andNbit of andNbit is 78 79signal and_vector: std_logic_vector(N downto 0); 80 81begin 82 and_vector(0) <= '1'; 83 84 and_generator: 85 for i in 1 to N generate 86 and_vector(i) <= and_vector(i-1) and input(i-1); 87 end generate and_generator; 88 89 y <= and_vector(N); 90 91end; 92 93library ieee; 94use ieee.std_logic_1164.all; 95 96entity orNbit is 97generic( 98 N: positive 99); 100port( 101 input: in std_logic_vector((N-1) downto 0); 102 y: out std_logic 103); 104end; 105 106architecture struct_orNbit of orNbit is 107 108signal or_vector: std_logic_vector(N downto 0); 109 110begin 111 or_vector(0) <= '0'; 112 113 or_generator: 114 for i in 1 to N generate 115 or_vector(i) <= or_vector(i-1) or input(i-1); 116 end generate or_generator; 117 118 y <= or_vector(N); 119 120end; 121 122library ieee; 123use ieee.std_logic_1164.all; 124 125entity incrementerN is 126generic( 127 N: positive 128); 129port( 130 input: in std_logic_vector((N-1) downto 0); 131 carry_in: in std_logic; 132 sum: out std_logic_vector((N-1) downto 0); 133 carry_out: out std_logic 134); 135end; 136 137-- tested with ghdl at N = 16 starting 2016/01/22, finished ?, works. 138 139architecture struct_incrementerN of incrementerN is 140component incrementer is 141port( 142 input: in std_logic; 143 carry_in: in std_logic; 144 sum: out std_logic; 145 carry_out: out std_logic 146); 147end component; 148 149signal carry: std_logic_vector(N downto 0); 150signal result: std_logic_vector((N-1) downto 0); 151 152begin 153 carry(0) <= carry_in; 154 155 u1: for i in (N-1) downto 0 generate 156 u: incrementer port map( 157 input => input(i), 158 carry_in => carry(i), 159 sum => result(i), 160 carry_out => carry(i + 1) 161 ); 162 end generate; 163 164 carry_out <= carry(N); 165 sum <= result; 166end; 167 168library ieee; 169use ieee.std_logic_1164.all; 170 171entity decoder1x16 is 172port( 173 data: in std_logic; 174 y0: out std_logic; 175 y1: out std_logic; 176 y2: out std_logic; 177 y3: out std_logic; 178 y4: out std_logic; 179 y5: out std_logic; 180 y6: out std_logic; 181 y7: out std_logic; 182 y8: out std_logic; 183 y9: out std_logic; 184 y10: out std_logic; 185 y11: out std_logic; 186 y12: out std_logic; 187 y13: out std_logic; 188 y14: out std_logic; 189 y15: out std_logic; 190 address: in std_logic_vector(3 downto 0) 191); 192end; 193 194architecture struct_decoder1x16 of decoder1x16 is 195begin 196 with address select y0 <= data when x"0", '0' when others; 197 with address select y1 <= data when x"1", '0' when others; 198 with address select y2 <= data when x"2", '0' when others; 199 with address select y3 <= data when x"3", '0' when others; 200 with address select y4 <= data when x"4", '0' when others; 201 with address select y5 <= data when x"5", '0' when others; 202 with address select y6 <= data when x"6", '0' when others; 203 with address select y7 <= data when x"7", '0' when others; 204 with address select y8 <= data when x"8", '0' when others; 205 with address select y9 <= data when x"9", '0' when others; 206 with address select y10 <= data when x"a", '0' when others; 207 with address select y11 <= data when x"b", '0' when others; 208 with address select y12 <= data when x"c", '0' when others; 209 with address select y13 <= data when x"d", '0' when others; 210 with address select y14 <= data when x"e", '0' when others; 211 with address select y15 <= data when x"f", '0' when others; 212end; 213 214-- For reasons unknown, ghdl appears to ignore the generic definition of N in this and only 215-- this architecture. Error messages are generated at line 129 onwards. No unusual characters 216-- found in the file where the first error message is generated. 217 218library ieee; 219use ieee.std_logic_1164.all; 220 221entity decoderNx16 is 222generic( 223 N: positive 224); 225port( 226 data: in std_logic_vector((N-1) downto 0); 227 y0: out std_logic_vector((N-1) downto 0); 228 y1: out std_logic_vector((N-1) downto 0); 229 y2: out std_logic_vector((N-1) downto 0); 230 y3: out std_logic_vector((N-1) downto 0); 231 y4: out std_logic_vector((N-1) downto 0); 232 y5: out std_logic_vector((N-1) downto 0); 233 y6: out std_logic_vector((N-1) downto 0); 234 y7: out std_logic_vector((N-1) downto 0); 235 y8: out std_logic_vector((N-1) downto 0); 236 y9: out std_logic_vector((N-1) downto 0); 237 y10: out std_logic_vector((N-1) downto 0); 238 y11: out std_logic_vector((N-1) downto 0); 239 y12: out std_logic_vector((N-1) downto 0); 240 y13: out std_logic_vector((N-1) downto 0); 241 y14: out std_logic_vector((N-1) downto 0); 242 y15: out std_logic_vector((N-1) downto 0); 243 address: in std_logic_vector(3 downto 0) 244); 245end; 246 247architecture struct_decoderNx16 of decoderNx16 is 248component decoder1x16 is 249port( 250 data: in std_logic; 251 y0: out std_logic; 252 y1: out std_logic; 253 y2: out std_logic; 254 y3: out std_logic; 255 y4: out std_logic; 256 y5: out std_logic; 257 y6: out std_logic; 258 y7: out std_logic; 259 y8: out std_logic; 260 y9: out std_logic; 261 y10: out std_logic; 262 y11: out std_logic; 263 y12: out std_logic; 264 y13: out std_logic; 265 y14: out std_logic; 266 y15: out std_logic; 267 address: in std_logic_vector(3 downto 0) 268); 269end component; 270 271begin 272 u1: for i in (N-1) downto 0 generate 273 u: decoder1x16 port map( 274 data => data(i), 275 y0 => y0(i), 276 y1 => y1(i), 277 y2 => y2(i), 278 y3 => y3(i), 279 y4 => y4(i), 280 y5 => y5(i), 281 y6 => y6(i), 282 y7 => y7(i), 283 y8 => y8(i), 284 y9 => y9(i), 285 y10 => y10(i), 286 y11 => y11(i), 287 y12 => y12(i), 288 y13 => y13(i), 289 y14 => y14(i), 290 y15 => y15(i), 291 address => address 292 ); 293 end generate u1; 294end; 295 296library ieee; 297use ieee.std_logic_1164.all; 298 299entity decoder1x2 is 300port( 301 data: in std_logic; 302 selector: in std_logic; 303 y0: out std_logic; 304 y1: out std_logic 305); 306end; 307 308-- Tested 2015/12/04 with Modelsim. Works. 309 310architecture struct_decoder1x2 of decoder1x2 is 311begin 312 with selector select y0 <= data when '0', '0' when others; 313 with selector select y1 <= data when '1', '0' when others; 314end; 315 316library ieee; 317use ieee.std_logic_1164.all; 318 319entity decoderNx2 is 320generic( 321 N: positive 322); 323port( 324 data: in std_logic_vector((N-1) downto 0); 325 selector: in std_logic; 326 y0: out std_logic_vector((N-1) downto 0); 327 y1: out std_logic_vector((N-1) downto 0) 328); 329end; 330 331-- tested 2015/12/27 at N = 8 with modelsim. works. 332-- tested 2016/01/23 at N = 8 with ghdl. works. 333 334architecture struct_decoderNx2 of decoderNx2 is 335component decoder1x2 is 336port( 337 data: in std_logic; 338 selector: in std_logic; 339 y0: out std_logic; 340 y1: out std_logic 341); 342end component; 343 344begin 345 u1: for i in (N-1) downto 0 generate 346 u: decoder1x2 port map( 347 data => data(i), 348 selector => selector, 349 y0 => y0(i), 350 y1 => y1(i) 351 ); 352 end generate u1; 353end; 354 355library ieee; 356use ieee.std_logic_1164.all; 357 358entity encoder2x1oe is 359port( 360 data0, data1: in std_logic; 361 selector: in std_logic; 362 enable: in std_logic; 363 output: out std_logic 364); 365end; 366 367-- tested during testing of encoder2xNoe, works. 368 369architecture struct_encoder2x1oe of encoder2x1oe is 370begin 371 with selector select 372 output <= (data0 and enable) when '0', 373 (data1 and enable) when '1', 374 '0' when others; 375end; 376 377library ieee; 378use ieee.std_logic_1164.all; 379 380entity encoder2xN_oe is 381generic( 382 N: positive 383); 384port( 385 data0: in std_logic_vector((N-1) downto 0); 386 data1: in std_logic_vector((N-1) downto 0); 387 selector: in std_logic; 388 enable: in std_logic; 389 output: out std_logic_vector((N-1) downto 0) 390); 391end; 392 393architecture struct_encoder2xN_oe of encoder2xN_oe is 394component encoder2x1oe is 395port( 396 data0: in std_logic; 397 data1: in std_logic; 398 selector: in std_logic; 399 enable: in std_logic; 400 output: out std_logic 401); 402end component; 403 404begin 405 u1: for i in (N-1) downto 0 generate 406 u: encoder2x1oe port map( 407 data0 => data0(i), 408 data1 => data1(i), 409 selector => selector, 410 enable => enable, 411 output => output(i) 412 ); 413 end generate u1; 414end; 415 416library ieee; 417use ieee.std_logic_1164.all; 418 419entity encoder2x1 is 420port( 421 data0: in std_logic; 422 data1: in std_logic; 423 selector: in std_logic; 424 output: out std_logic 425); 426end; 427 428-- tested during double register pair testing 2015/12/03. Works. 429 430architecture struct_encoder2x1 of encoder2x1 is 431begin 432 with selector select 433 output <= data0 when '0', 434 data1 when '1', 435 '0' when others; 436end; 437 438library ieee; 439use ieee.std_logic_1164.all; 440 441entity encoder2xN is 442generic( 443 N: positive 444); 445port( 446 data0: in std_logic_vector((N-1) downto 0); 447 data1: in std_logic_vector((N-1) downto 0); 448 selector: in std_logic; 449 output: out std_logic_vector((N-1) downto 0) 450); 451end; 452 453-- tested during double register pair testing 2015/12/03. Works for N = 8. 454-- also tested during alu testing. works there too. 455 456architecture struct_encoder2xN of encoder2xN is 457component encoder2x1 is 458port( 459 data0: in std_logic; 460 data1: in std_logic; 461 selector: in std_logic; 462 output: out std_logic 463); 464end component; 465 466begin 467 u1: for i in (N-1) downto 0 generate 468 u: encoder2x1 port map( 469 data0 => data0(i), 470 data1 => data1(i), 471 selector => selector, 472 output => output(i) 473 ); 474 end generate u1; 475end; 476 477library ieee; 478use ieee.std_logic_1164.all; 479 480entity synchronous_latch is 481port( 482 rstn: in std_logic; 483 clock: in std_logic; 484 clock_enable: in std_logic; 485 d: in std_logic; 486 q: out std_logic 487); 488end; 489 490-- Tested 2016/11/21, works on Modelsim simulator. 491 492architecture struct_synchronous_latch of synchronous_latch is 493begin 494 process(rstn, clock, clock_enable) 495 variable datum: std_logic; 496 begin 497 if rstn = '0' then 498 datum := '0'; 499 elsif rising_edge(clock) then 500 if clock_enable = '1' then 501 datum := d; 502 end if; 503 end if; 504 505 q <= datum; 506 end process; 507end; 508 509library ieee; 510use ieee.std_logic_1164.all; 511 512-- library altera; 513-- use altera.altera_primitives_components.all; 514 515entity synchronous_latchN is 516generic( 517 N: positive 518); 519port( 520 rstn: in std_logic; 521 clock: in std_logic; 522 clock_enable: in std_logic; 523 d: in std_logic_vector((N-1) downto 0); 524 q: out std_logic_vector((N-1) downto 0) 525); 526end; 527 528-- Tested 2016/11/21, works on Modelsim simulator. 529 530architecture struct_synchronous_latchN of synchronous_latchN is 531component synchronous_latch is 532port( 533 rstn: in std_logic; 534 clock: in std_logic; 535 clock_enable: in std_logic; 536 d: in std_logic; 537 q: out std_logic 538); 539end component; 540 541begin 542 u1: for i in 0 to (N-1) generate 543 u: synchronous_latch port map( 544 rstn => rstn, 545 clock => clock, 546 clock_enable => clock_enable, 547 d => d(i), 548 q => q(i) 549 ); 550 end generate u1; 551end; 552 553library ieee; 554use ieee.std_logic_1164.all; 555 556entity synchronous_latch_oe is 557port( 558 rstn: in std_logic; 559 clock: in std_logic; 560 clock_enable: in std_logic; 561 oe: in std_logic; 562 d: in std_logic; 563 q: out std_logic 564); 565end; 566 567-- tested 2015/12/27 as part of testing synchronous_latchN_oe. works. 568 569architecture struct_synchronous_latch_oe of synchronous_latch_oe is 570begin 571 process(rstn, clock, clock_enable, oe) 572 variable datum: std_logic; 573 begin 574 if rstn = '0' then 575 datum := '0'; 576 elsif rising_edge(clock) then 577 if clock_enable = '1' then 578 datum := d; 579 end if; 580 end if; 581 582 if oe = '1' then 583 q <= datum; 584 else 585 q <= 'Z'; 586 end if; 587 end process; 588end; 589 590library ieee; 591use ieee.std_logic_1164.all; 592 593entity synchronous_latchN_oe is 594generic( 595 N: positive 596); 597port( 598 rstn: in std_logic; 599 clock: in std_logic; 600 clock_enable: in std_logic; 601 oe: in std_logic; 602 d: in std_logic_vector((N-1) downto 0); 603 q: out std_logic_vector((N-1) downto 0) 604); 605end; 606 607-- tested 2015/12/27, N = 8 with modelsim. works. 608 609architecture struct_synchronous_latchN_oe of synchronous_latchN_oe is 610component synchronous_latch_oe is 611port( 612 rstn: in std_logic; 613 clock: in std_logic; 614 clock_enable: in std_logic; 615 oe: in std_logic; 616 d: in std_logic; 617 q: out std_logic 618); 619end component; 620 621begin 622 u1: for i in (N-1) downto 0 generate 623 u: synchronous_latch_oe port map( 624 rstn => rstn, 625 clock => clock, 626 clock_enable => clock_enable, 627 oe => oe, 628 d => d(i), 629 q => q(i) 630 ); 631 end generate u1; 632end; 633 634library ieee; 635use ieee.std_logic_1164.all; 636 637entity synchronous_latch_autoclear is 638port( 639 rstn: in std_logic; 640 clock: in std_logic; 641 clock_enable: in std_logic; 642 d: in std_logic; 643 q: out std_logic 644); 645end; 646 647-- Tested 2016/11/21, works on Modelsim simulator. 648 649architecture struct_synchronous_latch_autoclear of synchronous_latch_autoclear is 650begin 651 process(rstn, clock) 652 variable datum: std_logic; 653 begin 654 if rstn = '0' then 655 datum := '0'; 656 elsif rising_edge(clock) then 657 if clock_enable = '1' then 658 if datum = '1' then 659 datum := '0'; 660 else 661 datum := d; 662 end if; 663 else 664 datum := '0'; 665 end if; 666 end if; 667 668 q <= datum; 669 end process; 670end; 671 672library ieee; 673use ieee.std_logic_1164.all; 674 675entity encoder4x1 is 676port( 677 data0: in std_logic; 678 data1: in std_logic; 679 data2: in std_logic; 680 data3: in std_logic; 681 address: in std_logic_vector(1 downto 0); 682 output: out std_logic 683 ); 684end; 685 686-- tested 2015/12/26 with modelsim as part of encoder4xN, works. 687 688architecture struct_encoder4x1 of encoder4x1 is 689begin 690 with address select 691 output <= data0 when "00", 692 data1 when "01", 693 data2 when "10", 694 data3 when "11", 695 '0' when others; 696end; 697 698library ieee; 699use ieee.std_logic_1164.all; 700 701entity encoder4xN is 702generic( 703 N: positive 704); 705port( 706 data0: in std_logic_vector((N-1) downto 0); 707 data1: in std_logic_vector((N-1) downto 0); 708 data2: in std_logic_vector((N-1) downto 0); 709 data3: in std_logic_vector((N-1) downto 0); 710 address: in std_logic_vector(1 downto 0); 711 output: out std_logic_vector((N-1) downto 0) 712 ); 713end; 714 715-- tested 2015/12/26 with modelsim at N = 16, works. 716 717architecture struct_encoder4xN of encoder4xN is 718component encoder4x1 is 719port( 720 data0: in std_logic; 721 data1: in std_logic; 722 data2: in std_logic; 723 data3: in std_logic; 724 address: in std_logic_vector(1 downto 0); 725 output: out std_logic 726 ); 727end component; 728 729begin 730 u1: for i in (N-1) downto 0 generate 731 u: encoder4x1 port map( 732 data0 => data0(i), 733 data1 => data1(i), 734 data2 => data2(i), 735 data3 => data3(i), 736 address => address, 737 output => output(i) 738 ); 739 end generate u1; 740end; 741 742library ieee; 743use ieee.std_logic_1164.all; 744 745entity encoder8x1 is 746port( 747 data0: in std_logic; 748 data1: in std_logic; 749 data2: in std_logic; 750 data3: in std_logic; 751 data4: in std_logic; 752 data5: in std_logic; 753 data6: in std_logic; 754 data7: in std_logic; 755 address: in std_logic_vector(2 downto 0); 756 output: out std_logic 757); 758end; 759 760-- tested 2015/12/26 as part of encoder8xN with modelsim, works. 761 762architecture struct_encoder8x1 of encoder8x1 is 763begin 764 with address select 765 output <= data0 when "000", 766 data1 when "001", 767 data2 when "010", 768 data3 when "011", 769 data4 when "100", 770 data5 when "101", 771 data6 when "110", 772 data7 when "111", 773 '0' when others; 774end; 775 776library ieee; 777use ieee.std_logic_1164.all; 778 779entity encoder8xN is 780generic( 781 N: positive 782); 783port( 784 data0: in std_logic_vector((N-1) downto 0); 785 data1: in std_logic_vector((N-1) downto 0); 786 data2: in std_logic_vector((N-1) downto 0); 787 data3: in std_logic_vector((N-1) downto 0); 788 data4: in std_logic_vector((N-1) downto 0); 789 data5: in std_logic_vector((N-1) downto 0); 790 data6: in std_logic_vector((N-1) downto 0); 791 data7: in std_logic_vector((N-1) downto 0); 792 address: in std_logic_vector(2 downto 0); 793 output: out std_logic_vector((N-1) downto 0) 794); 795end; 796 797-- tested 2015/12/26 for N = 8 with modelsim, works. 798 799architecture struct_encoder8xN of encoder8xN is 800component encoder8x1 is 801port( 802 data0: in std_logic; 803 data1: in std_logic; 804 data2: in std_logic; 805 data3: in std_logic; 806 data4: in std_logic; 807 data5: in std_logic; 808 data6: in std_logic; 809 data7: in std_logic; 810 address: in std_logic_vector(2 downto 0); 811 output: out std_logic 812); 813end component; 814 815begin 816 u1: for i in (N-1) downto 0 generate 817 u: encoder8x1 port map( 818 data0 => data0(i), 819 data1 => data1(i), 820 data2 => data2(i), 821 data3 => data3(i), 822 data4 => data4(i), 823 data5 => data5(i), 824 data6 => data6(i), 825 data7 => data7(i), 826 address => address, 827 output => output(i) 828 ); 829 end generate u1; 830end; 831 832library ieee; 833use ieee.std_logic_1164.all; 834 835entity decoder1x8 is 836port( 837 data: in std_logic; 838 y0: out std_logic; 839 y1: out std_logic; 840 y2: out std_logic; 841 y3: out std_logic; 842 y4: out std_logic; 843 y5: out std_logic; 844 y6: out std_logic; 845 y7: out std_logic; 846 address: in std_logic_vector(2 downto 0) 847); 848end; 849 850-- tested 2015/12/30 with modelsim as part of decoderNx8, works. 851 852architecture struct_decoder1x8 of decoder1x8 is 853begin 854 with address select y0 <= data when "000", '0' when others; 855 with address select y1 <= data when "001", '0' when others; 856 with address select y2 <= data when "010", '0' when others; 857 with address select y3 <= data when "011", '0' when others; 858 with address select y4 <= data when "100", '0' when others; 859 with address select y5 <= data when "101", '0' when others; 860 with address select y6 <= data when "110", '0' when others; 861 with address select y7 <= data when "111", '0' when others; 862end; 863 864library ieee; 865use ieee.std_logic_1164.all; 866 867entity decoderNx8 is 868generic( 869 N: positive 870); 871port( 872 data: in std_logic_vector((N-1) downto 0); 873 y0: out std_logic_vector((N-1) downto 0); 874 y1: out std_logic_vector((N-1) downto 0); 875 y2: out std_logic_vector((N-1) downto 0); 876 y3: out std_logic_vector((N-1) downto 0); 877 y4: out std_logic_vector((N-1) downto 0); 878 y5: out std_logic_vector((N-1) downto 0); 879 y6: out std_logic_vector((N-1) downto 0); 880 y7: out std_logic_vector((N-1) downto 0); 881 address: in std_logic_vector(2 downto 0) 882); 883end; 884 885-- tested 2015/12/30 with modelsim, works. 886 887architecture struct_decoderNx8 of decoderNx8 is 888component decoder1x8 is 889port( 890 data: in std_logic; 891 y0: out std_logic; 892 y1: out std_logic; 893 y2: out std_logic; 894 y3: out std_logic; 895 y4: out std_logic; 896 y5: out std_logic; 897 y6: out std_logic; 898 y7: out std_logic; 899 address: in std_logic_vector(2 downto 0) 900); 901end component; 902 903begin 904 u1: for i in (N-1) downto 0 generate 905 u: decoder1x8 port map( 906 data => data(i), 907 y0 => y0(i), 908 y1 => y1(i), 909 y2 => y2(i), 910 y3 => y3(i), 911 y4 => y4(i), 912 y5 => y5(i), 913 y6 => y6(i), 914 y7 => y7(i), 915 address=> address 916 ); 917 end generate u1; 918end; 919 920library ieee; 921use ieee.std_logic_1164.all; 922 923entity encoder16x1 is 924port( 925 data0: in std_logic; 926 data1: in std_logic; 927 data2: in std_logic; 928 data3: in std_logic; 929 data4: in std_logic; 930 data5: in std_logic; 931 data6: in std_logic; 932 data7: in std_logic; 933 data8: in std_logic; 934 data9: in std_logic; 935 data10: in std_logic; 936 data11: in std_logic; 937 data12: in std_logic; 938 data13: in std_logic; 939 data14: in std_logic; 940 data15: in std_logic; 941 address: in std_logic_vector(3 downto 0); 942 output: out std_logic 943); 944end; 945 946-- tested with Modelsim 2015/12/24 as part of encoder16xN, works with N = 8. 947 948architecture struct_encoder16x1 of encoder16x1 is 949begin 950 with address select 951 output <= data0 when "0000", 952 data1 when "0001", 953 data2 when "0010", 954 data3 when "0011", 955 data4 when "0100", 956 data5 when "0101", 957 data6 when "0110", 958 data7 when "0111", 959 data8 when "1000", 960 data9 when "1001", 961 data10 when "1010", 962 data11 when "1011", 963 data12 when "1100", 964 data13 when "1101", 965 data14 when "1110", 966 data15 when "1111", 967 '0' when others; 968end; 969 970library ieee; 971use ieee.std_logic_1164.all; 972 973entity encoder16xN is 974generic( 975 N: positive 976); 977port( 978 data0: in std_logic_vector((N-1) downto 0); 979 data1: in std_logic_vector((N-1) downto 0); 980 data2: in std_logic_vector((N-1) downto 0); 981 data3: in std_logic_vector((N-1) downto 0); 982 data4: in std_logic_vector((N-1) downto 0); 983 data5: in std_logic_vector((N-1) downto 0); 984 data6: in std_logic_vector((N-1) downto 0); 985 data7: in std_logic_vector((N-1) downto 0); 986 data8: in std_logic_vector((N-1) downto 0); 987 data9: in std_logic_vector((N-1) downto 0); 988 data10: in std_logic_vector((N-1) downto 0); 989 data11: in std_logic_vector((N-1) downto 0); 990 data12: in std_logic_vector((N-1) downto 0); 991 data13: in std_logic_vector((N-1) downto 0); 992 data14: in std_logic_vector((N-1) downto 0); 993 data15: in std_logic_vector((N-1) downto 0); 994 address: in std_logic_vector(3 downto 0); 995 output: out std_logic_vector((N-1) downto 0) 996); 997end; 998 999-- tested with Modelsim 2015/12/24, works with N = 8. 1000 1001architecture struct_encoder16xN of encoder16xN is 1002component encoder16x1 is 1003port( 1004 data0: in std_logic; 1005 data1: in std_logic; 1006 data2: in std_logic; 1007 data3: in std_logic; 1008 data4: in std_logic; 1009 data5: in std_logic; 1010 data6: in std_logic; 1011 data7: in std_logic; 1012 data8: in std_logic; 1013 data9: in std_logic; 1014 data10: in std_logic; 1015 data11: in std_logic; 1016 data12: in std_logic; 1017 data13: in std_logic; 1018 data14: in std_logic; 1019 data15: in std_logic; 1020 address: in std_logic_vector(3 downto 0); 1021 output: out std_logic 1022); 1023end component; 1024 1025begin 1026 u1: for i in (N-1) downto 0 generate 1027 u: encoder16x1 port map( 1028 data0 => data0(i), 1029 data1 => data1(i), 1030 data2 => data2(i), 1031 data3 => data3(i), 1032 data4 => data4(i), 1033 data5 => data5(i), 1034 data6 => data6(i), 1035 data7 => data7(i), 1036 data8 => data8(i), 1037 data9 => data9(i), 1038 data10 => data10(i), 1039 data11 => data11(i), 1040 data12 => data12(i), 1041 data13 => data13(i), 1042 data14 => data14(i), 1043 data15 => data15(i), 1044 address => address, 1045 output => output(i) 1046 ); 1047 end generate u1; 1048end; 1049 1050library ieee; 1051use ieee.std_logic_1164.all; 1052 1053entity encoder32x1 is 1054port( 1055 data0: in std_logic; 1056 data1: in std_logic; 1057 data2: in std_logic; 1058 data3: in std_logic; 1059 data4: in std_logic; 1060 data5: in std_logic; 1061 data6: in std_logic; 1062 data7: in std_logic; 1063 data8: in std_logic; 1064 data9: in std_logic; 1065 data10: in std_logic; 1066 data11: in std_logic; 1067 data12: in std_logic; 1068 data13: in std_logic; 1069 data14: in std_logic; 1070 data15: in std_logic; 1071 data16: in std_logic; 1072 data17: in std_logic; 1073 data18: in std_logic; 1074 data19: in std_logic; 1075 data20: in std_logic; 1076 data21: in std_logic; 1077 data22: in std_logic; 1078 data23: in std_logic; 1079 data24: in std_logic; 1080 data25: in std_logic; 1081 data26: in std_logic; 1082 data27: in std_logic; 1083 data28: in std_logic; 1084 data29: in std_logic; 1085 data30: in std_logic; 1086 data31: in std_logic; 1087 address: in std_logic_vector(4 downto 0); 1088 output: out std_logic 1089); 1090end; 1091 1092-- tested 2015/12/24 as part of testing encoder32xN. Works. 1093 1094architecture struct_encoder32x1 of encoder32x1 is 1095begin 1096 with address select 1097 output <= data0 when "00000", 1098 data1 when "00001", 1099 data2 when "00010", 1100 data3 when "00011", 1101 data4 when "00100", 1102 data5 when "00101", 1103 data6 when "00110", 1104 data7 when "00111", 1105 data8 when "01000", 1106 data9 when "01001", 1107 data10 when "01010", 1108 data11 when "01011", 1109 data12 when "01100", 1110 data13 when "01101", 1111 data14 when "01110", 1112 data15 when "01111", 1113 data16 when "10000", 1114 data17 when "10001", 1115 data18 when "10010", 1116 data19 when "10011", 1117 data20 when "10100", 1118 data21 when "10101", 1119 data22 when "10110", 1120 data23 when "10111", 1121 data24 when "11000", 1122 data25 when "11001", 1123 data26 when "11010", 1124 data27 when "11011", 1125 data28 when "11100", 1126 data29 when "11101", 1127 data30 when "11110", 1128 data31 when "11111", 1129 '0' when others; 1130end; 1131 1132 1133library ieee; 1134use ieee.std_logic_1164.all; 1135 1136entity encoder32xN is 1137generic( 1138 N: positive 1139); 1140port( 1141 data0: in std_logic_vector((N-1) downto 0); 1142 data1: in std_logic_vector((N-1) downto 0); 1143 data2: in std_logic_vector((N-1) downto 0); 1144 data3: in std_logic_vector((N-1) downto 0); 1145 data4: in std_logic_vector((N-1) downto 0); 1146 data5: in std_logic_vector((N-1) downto 0); 1147 data6: in std_logic_vector((N-1) downto 0); 1148 data7: in std_logic_vector((N-1) downto 0); 1149 data8: in std_logic_vector((N-1) downto 0); 1150 data9: in std_logic_vector((N-1) downto 0); 1151 data10: in std_logic_vector((N-1) downto 0); 1152 data11: in std_logic_vector((N-1) downto 0); 1153 data12: in std_logic_vector((N-1) downto 0); 1154 data13: in std_logic_vector((N-1) downto 0); 1155 data14: in std_logic_vector((N-1) downto 0); 1156 data15: in std_logic_vector((N-1) downto 0); 1157 data16: in std_logic_vector((N-1) downto 0); 1158 data17: in std_logic_vector((N-1) downto 0); 1159 data18: in std_logic_vector((N-1) downto 0); 1160 data19: in std_logic_vector((N-1) downto 0); 1161 data20: in std_logic_vector((N-1) downto 0); 1162 data21: in std_logic_vector((N-1) downto 0); 1163 data22: in std_logic_vector((N-1) downto 0); 1164 data23: in std_logic_vector((N-1) downto 0); 1165 data24: in std_logic_vector((N-1) downto 0); 1166 data25: in std_logic_vector((N-1) downto 0); 1167 data26: in std_logic_vector((N-1) downto 0); 1168 data27: in std_logic_vector((N-1) downto 0); 1169 data28: in std_logic_vector((N-1) downto 0); 1170 data29: in std_logic_vector((N-1) downto 0); 1171 data30: in std_logic_vector((N-1) downto 0); 1172 data31: in std_logic_vector((N-1) downto 0); 1173 address: in std_logic_vector(4 downto 0); 1174 output: out std_logic_vector((N-1) downto 0) 1175); 1176end; 1177 1178-- tested 2015/12/24 with N = 8. Works. 1179 1180architecture struct_encoder32xN of encoder32xN is 1181component encoder32x1 is 1182port( 1183 data0: in std_logic; 1184 data1: in std_logic; 1185 data2: in std_logic; 1186 data3: in std_logic; 1187 data4: in std_logic; 1188 data5: in std_logic; 1189 data6: in std_logic; 1190 data7: in std_logic; 1191 data8: in std_logic; 1192 data9: in std_logic; 1193 data10: in std_logic; 1194 data11: in std_logic; 1195 data12: in std_logic; 1196 data13: in std_logic; 1197 data14: in std_logic; 1198 data15: in std_logic; 1199 data16: in std_logic; 1200 data17: in std_logic; 1201 data18: in std_logic; 1202 data19: in std_logic; 1203 data20: in std_logic; 1204 data21: in std_logic; 1205 data22: in std_logic; 1206 data23: in std_logic; 1207 data24: in std_logic; 1208 data25: in std_logic; 1209 data26: in std_logic; 1210 data27: in std_logic; 1211 data28: in std_logic; 1212 data29: in std_logic; 1213 data30: in std_logic; 1214 data31: in std_logic; 1215 address: in std_logic_vector(4 downto 0); 1216 output: out std_logic 1217); 1218end component; 1219 1220begin 1221 u1: for i in (N-1) downto 0 generate 1222 u: encoder32x1 port map( 1223 data0 => data0(i), 1224 data1 => data1(i), 1225 data2 => data2(i), 1226 data3 => data3(i), 1227 data4 => data4(i), 1228 data5 => data5(i), 1229 data6 => data6(i), 1230 data7 => data7(i), 1231 data8 => data8(i), 1232 data9 => data9(i), 1233 data10 => data10(i), 1234 data11 => data11(i), 1235 data12 => data12(i), 1236 data13 => data13(i), 1237 data14 => data14(i), 1238 data15 => data15(i), 1239 data16 => data16(i), 1240 data17 => data17(i), 1241 data18 => data18(i), 1242 data19 => data19(i), 1243 data20 => data20(i), 1244 data21 => data21(i), 1245 data22 => data22(i), 1246 data23 => data23(i), 1247 data24 => data24(i), 1248 data25 => data25(i), 1249 data26 => data26(i), 1250 data27 => data27(i), 1251 data28 => data28(i), 1252 data29 => data29(i), 1253 data30 => data30(i), 1254 data31 => data31(i), 1255 address => address, 1256 output => output(i) 1257 ); 1258 end generate u1; 1259end; 1260 1261library ieee; 1262use ieee.std_logic_1164.all; 1263 1264entity tristate is 1265port( 1266 a: in std_logic; 1267 enable: in std_logic; 1268 y: out std_logic 1269); 1270end; 1271 1272-- tested 2015/12/27 with modelsim as part of tristateN testing. works. 1273-- tested 2016/01/23 with ghdl as part of tristateN testing. works. 1274 1275architecture struct_tristate of tristate is 1276begin 1277 y <= a when enable = '1' else 'Z'; 1278end; 1279 1280library ieee; 1281use ieee.std_logic_1164.all; 1282 1283entity tristateN is 1284generic( 1285 N: positive 1286); 1287port( 1288 a: in std_logic_vector((N-1) downto 0); 1289 enable: in std_logic; 1290 y: out std_logic_vector((N-1) downto 0) 1291); 1292end; 1293 1294-- tested 2015/12/27 at N = 16 with modelsim. works. 1295-- tested 2016/01/23 at N = 16 with ghdl. works. 1296 1297architecture struct_tristateN of tristateN is 1298component tristate is 1299port( 1300 a: in std_logic; 1301 enable: in std_logic; 1302 y: out std_logic 1303); 1304end component; 1305 1306begin 1307 u1: for i in 0 to (N-1) generate 1308 u: tristate port map( 1309 a => a(i), 1310 enable => enable, 1311 y => y(i) 1312 ); 1313 end generate; 1314end; 1315 1316library ieee; 1317use ieee.std_logic_1164.all; 1318 1319entity toggle_ff is 1320port( 1321 clk: in std_logic; 1322 clock_enable: in std_logic; 1323 resetn: in std_logic; 1324 q: out std_logic 1325); 1326end; 1327 1328-- tested 2015/12/26 with modelsim, works. 1329 1330architecture struct_toggle_ff of toggle_ff is 1331component synchronous_latch is 1332port( 1333 rstn: in std_logic; 1334 clock: in std_logic; 1335 clock_enable: in std_logic; 1336 d: in std_logic; 1337 q: out std_logic 1338); 1339end component; 1340 1341component synchronous_latch_autoclear is 1342port( 1343 rstn: in std_logic; 1344 clock: in std_logic; 1345 clock_enable: in std_logic; 1346 d: in std_logic; 1347 q: out std_logic 1348); 1349end component; 1350 1351component encoder2x1 is 1352port( 1353 data0: in std_logic; 1354 data1: in std_logic; 1355 selector: in std_logic; 1356 output: out std_logic 1357); 1358end component; 1359 1360signal toggle_output: std_logic; 1361signal toggle_clock: std_logic; 1362signal flipflop_data: std_logic; 1363signal not_toggle_output: std_logic; 1364signal notclock: std_logic; 1365 1366begin 1367 u1: synchronous_latch port map( 1368 rstn => resetn, 1369 clock => clk, 1370 clock_enable => toggle_clock, 1371 d => flipflop_data, 1372 q => toggle_output 1373 ); 1374 1375 u2: encoder2x1 port map( 1376 data0 => toggle_output, 1377 data1 => not_toggle_output, 1378 selector => toggle_clock, 1379 output => flipflop_data 1380 ); 1381 1382 u3: synchronous_latch_autoclear port map( 1383 rstn => resetn, 1384 clock => notclock, 1385 clock_enable => clock_enable, 1386 d => clock_enable, 1387 q => toggle_clock 1388 ); 1389 1390 not_toggle_output <= not toggle_output; 1391 notclock <= not clk; 1392 q <= toggle_output; 1393end; 1394 1395library ieee; 1396use ieee.std_logic_1164.all; 1397 1398entity magnitude is 1399port( 1400 a, b: in std_logic; 1401 equal: out std_logic; 1402 lt: out std_logic; -- '1' if a < b 1403 gt: out std_logic -- '1' if a > b 1404); 1405end; 1406 1407-- tested 2015/12/26 with modelsim, works. 1408 1409architecture struct_magnitude of magnitude is 1410 1411signal equals: std_logic; 1412signal less: std_logic; 1413 1414begin 1415 equals <= not (a xor b); 1416 less <= (not a) and b; 1417 gt <= equals nor less; 1418 equal <= equals; 1419 lt <= less; 1420end; 1421 1422library ieee; 1423use ieee.std_logic_1164.all; 1424 1425entity magnitudeN is 1426generic( 1427 N: positive 1428); 1429port( 1430 a, b: in std_logic_vector((N-1) downto 0); 1431 equal: out std_logic; 1432 lt: out std_logic; -- '1' if a < b 1433 gt: out std_logic -- '1' if a > b 1434); 1435end; 1436 1437--tested with ghdl 2016/01/26, works. 1438 1439architecture struct_magnitudeN of magnitudeN is 1440 1441signal equals: std_logic_vector((N-1) downto 0); 1442signal less: std_logic_vector((N-1) downto 0); 1443 1444begin 1445 equals(N-1) <= not (a(N-1) xor b(N-1)); 1446 less (N-1) <= (not a(N-1)) and b(N-1); 1447 1448 u1: for i in (N-1) downto 1 generate 1449 equals(i-1) <= equals(i) and (not (a(i-1) xor b(i-1))); 1450 less(i-1) <= less(i) or (((not a(i-1)) and b(i-1)) and equals(i)); 1451 end generate u1; 1452 1453 equal <= equals(0); 1454 lt <= less(0); 1455 gt <= equals(0) nor less(0); 1456end; 1457 1458 1459--library ieee; 1460--use ieee.std_logic_1164.all; 1461-- 1462--entity magnitude2 is 1463--port( 1464-- a, b: in std_logic_vector(1 downto 0); 1465-- equal: out std_logic; 1466-- lt: out std_logic; -- '1' if a < b 1467-- gt: out std_logic -- '1' if a > b 1468--); 1469--end; 1470-- 1471---- tested 2015/12/26 with modelsim, works. 1472-- 1473--architecture struct_magnitude2 of magnitude2 is 1474--component magnitude is 1475--port( 1476-- a, b: in std_logic; 1477-- equal: out std_logic; 1478-- lt: out std_logic; -- '1' if a < b 1479-- gt: out std_logic -- '1' if a > b 1480--); 1481--end component; 1482-- 1483--signal high_equals: std_logic; 1484--signal high_lt: std_logic; 1485--signal high_gt: std_logic; 1486-- 1487--signal low_equals: std_logic; 1488--signal low_lt: std_logic; 1489--signal low_gt: std_logic; 1490-- 1491--signal equals: std_logic; 1492--signal less: std_logic; 1493-- 1494--begin 1495-- u1: magnitude port map( 1496-- a => a(1), 1497-- b => b(1), 1498-- equal => high_equals, 1499-- lt => high_lt, 1500-- gt => high_gt 1501-- ); 1502-- 1503-- u2: magnitude port map( 1504-- a => a(0), 1505-- b => b(0), 1506-- equal => low_equals, 1507-- lt => low_lt, 1508-- gt => low_gt 1509-- ); 1510-- 1511-- equals <= high_equals and low_equals; 1512-- less <= high_lt or (high_equals and low_lt); 1513-- gt <= equals nor less; 1514-- equal <= equals; 1515-- lt <= less; 1516--end; 1517-- 1518--library ieee; 1519--use ieee.std_logic_1164.all; 1520-- 1521--entity magnitude3 is 1522--port( 1523-- a, b: in std_logic_vector(2 downto 0); 1524-- equal: out std_logic; 1525-- lt: out std_logic; -- '1' if a < b 1526-- gt: out std_logic -- '1' if a > b 1527--); 1528--end; 1529-- 1530---- tested 2015/12/26 with modelsim, works. 1531-- 1532--architecture struct_magnitude3 of magnitude3 is 1533--component magnitude2 is 1534--port( 1535-- a, b: in std_logic_vector(1 downto 0); 1536-- equal: out std_logic; 1537-- lt: out std_logic; -- '1' if a < b 1538-- gt: out std_logic -- '1' if a > b 1539--); 1540--end component; 1541-- 1542--component magnitude is 1543--port( 1544-- a, b: in std_logic; 1545-- equal: out std_logic; 1546-- lt: out std_logic; -- '1' if a < b 1547-- gt: out std_logic -- '1' if a > b 1548--); 1549--end component; 1550-- 1551--signal high_equals: std_logic; 1552--signal high_lt: std_logic; 1553--signal high_gt: std_logic; 1554-- 1555--signal low_equals: std_logic; 1556--signal low_lt: std_logic; 1557--signal low_gt: std_logic; 1558-- 1559--signal equals: std_logic; 1560--signal less: std_logic; 1561-- 1562--begin 1563-- u1: magnitude port map( 1564-- a => a(2), 1565-- b => b(2), 1566-- equal => high_equals, 1567-- lt => high_lt, 1568-- gt => high_gt 1569-- ); 1570-- 1571-- u2: magnitude2 port map( 1572-- a => a(1 downto 0), 1573-- b => b(1 downto 0), 1574-- equal => low_equals, 1575-- lt => low_lt, 1576-- gt => low_gt 1577-- ); 1578-- 1579-- equals <= high_equals and low_equals; 1580-- less <= high_lt or (high_equals and low_lt); 1581-- gt <= equals nor less; 1582-- equal <= equals; 1583-- lt <= less; 1584--end; 1585-- 1586--library ieee; 1587--use ieee.std_logic_1164.all; 1588-- 1589--entity magnitude4 is 1590--port( 1591-- a, b: in std_logic_vector(3 downto 0); 1592-- equal: out std_logic; 1593-- lt: out std_logic; -- '1' if a < b 1594-- gt: out std_logic -- '1' if a > b 1595--); 1596--end; 1597-- 1598---- tested 2015/12/26 with modelsim, works. 1599-- 1600--architecture struct_magnitude4 of magnitude4 is 1601--component magnitude3 is 1602--port( 1603-- a, b: in std_logic_vector(2 downto 0); 1604-- equal: out std_logic; 1605-- lt: out std_logic; -- '1' if a < b 1606-- gt: out std_logic -- '1' if a > b 1607--); 1608--end component; 1609-- 1610--component magnitude is 1611--port( 1612-- a, b: in std_logic; 1613-- equal: out std_logic; 1614-- lt: out std_logic; -- '1' if a < b 1615-- gt: out std_logic -- '1' if a > b 1616--); 1617--end component; 1618-- 1619--signal high_equals: std_logic; 1620--signal high_lt: std_logic; 1621--signal high_gt: std_logic; 1622-- 1623--signal low_equals: std_logic; 1624--signal low_lt: std_logic; 1625--signal low_gt: std_logic; 1626-- 1627--signal equals: std_logic; 1628--signal less: std_logic; 1629-- 1630--begin 1631-- u1: magnitude port map( 1632-- a => a(3), 1633-- b => b(3), 1634-- equal => high_equals, 1635-- lt => high_lt, 1636-- gt => high_gt 1637-- ); 1638-- 1639-- u2: magnitude3 port map( 1640-- a => a(2 downto 0), 1641-- b => b(2 downto 0), 1642-- equal => low_equals, 1643-- lt => low_lt, 1644-- gt => low_gt 1645-- ); 1646-- 1647-- equals <= high_equals and low_equals; 1648-- less <= high_lt or (high_equals and low_lt); 1649-- gt <= equals nor less; 1650-- equal <= equals; 1651-- lt <= less; 1652--end; 1653-- 1654--library ieee; 1655--use ieee.std_logic_1164.all; 1656-- 1657--entity magnitude5 is 1658--port( 1659-- a, b: in std_logic_vector(4 downto 0); 1660-- equal: out std_logic; 1661-- lt: out std_logic; -- '1' if a < b 1662-- gt: out std_logic -- '1' if a > b 1663--); 1664--end; 1665-- 1666---- tested 2015/12/26 with modelsim, works. 1667-- 1668--architecture struct_magnitude5 of magnitude5 is 1669--component magnitude4 is 1670--port( 1671-- a, b: in std_logic_vector(3 downto 0); 1672-- equal: out std_logic; 1673-- lt: out std_logic; -- '1' if a < b 1674-- gt: out std_logic -- '1' if a > b 1675--); 1676--end component; 1677-- 1678--component magnitude is 1679--port( 1680-- a, b: in std_logic; 1681-- equal: out std_logic; 1682-- lt: out std_logic; -- '1' if a < b 1683-- gt: out std_logic -- '1' if a > b 1684--); 1685--end component; 1686-- 1687--signal high_equals: std_logic; 1688--signal high_lt: std_logic; 1689--signal high_gt: std_logic; 1690-- 1691--signal low_equals: std_logic; 1692--signal low_lt: std_logic; 1693--signal low_gt: std_logic; 1694-- 1695--signal equals: std_logic; 1696--signal less: std_logic; 1697-- 1698--begin 1699-- u1: magnitude port map( 1700-- a => a(4), 1701-- b => b(4), 1702-- equal => high_equals, 1703-- lt => high_lt, 1704-- gt => high_gt 1705-- ); 1706-- 1707-- u2: magnitude4 port map( 1708-- a => a(3 downto 0), 1709-- b => b(3 downto 0), 1710-- equal => low_equals, 1711-- lt => low_lt, 1712-- gt => low_gt 1713-- ); 1714-- 1715-- equals <= high_equals and low_equals; 1716-- less <= high_lt or (high_equals and low_lt); 1717-- gt <= equals nor less; 1718-- equal <= equals; 1719-- lt <= less; 1720--end; 1721-- 1722--library ieee; 1723--use ieee.std_logic_1164.all; 1724-- 1725--entity magnitude6 is 1726--port( 1727-- a, b: in std_logic_vector(5 downto 0); 1728-- equal: out std_logic; 1729-- lt: out std_logic; -- '1' if a < b 1730-- gt: out std_logic -- '1' if a > b 1731--); 1732--end; 1733-- 1734---- tested 2015/12/26 with modelsim, works. 1735-- 1736--architecture struct_magnitude6 of magnitude6 is 1737--component magnitude5 is 1738--port( 1739-- a, b: in std_logic_vector(4 downto 0); 1740-- equal: out std_logic; 1741-- lt: out std_logic; -- '1' if a < b 1742-- gt: out std_logic -- '1' if a > b 1743--); 1744--end component; 1745-- 1746--component magnitude is 1747--port( 1748-- a, b: in std_logic; 1749-- equal: out std_logic; 1750-- lt: out std_logic; -- '1' if a < b 1751-- gt: out std_logic -- '1' if a > b 1752--); 1753--end component; 1754-- 1755--signal high_equals: std_logic; 1756--signal high_lt: std_logic; 1757--signal high_gt: std_logic; 1758-- 1759--signal low_equals: std_logic; 1760--signal low_lt: std_logic; 1761--signal low_gt: std_logic; 1762-- 1763--signal equals: std_logic; 1764--signal less: std_logic; 1765-- 1766--begin 1767-- u1: magnitude port map( 1768-- a => a(5), 1769-- b => b(5), 1770-- equal => high_equals, 1771-- lt => high_lt, 1772-- gt => high_gt 1773-- ); 1774-- 1775-- u2: magnitude5 port map( 1776-- a => a(4 downto 0), 1777-- b => b(4 downto 0), 1778-- equal => low_equals, 1779-- lt => low_lt, 1780-- gt => low_gt 1781-- ); 1782-- 1783-- equals <= high_equals and low_equals; 1784-- less <= high_lt or (high_equals and low_lt); 1785-- gt <= equals nor less; 1786-- equal <= equals; 1787-- lt <= less; 1788--end; 1789-- 1790--library ieee; 1791--use ieee.std_logic_1164.all; 1792-- 1793--entity magnitude7 is 1794--port( 1795-- a, b: in std_logic_vector(6 downto 0); 1796-- equal: out std_logic; 1797-- lt: out std_logic; -- '1' if a < b 1798-- gt: out std_logic -- '1' if a > b 1799--); 1800--end; 1801-- 1802---- tested 2015/12/26 with modelsim, works. 1803-- 1804--architecture struct_magnitude7 of magnitude7 is 1805--component magnitude6 is 1806--port( 1807-- a, b: in std_logic_vector(5 downto 0); 1808-- equal: out std_logic; 1809-- lt: out std_logic; -- '1' if a < b 1810-- gt: out std_logic -- '1' if a > b 1811--); 1812--end component; 1813-- 1814--component magnitude is 1815--port( 1816-- a, b: in std_logic; 1817-- equal: out std_logic; 1818-- lt: out std_logic; -- '1' if a < b 1819-- gt: out std_logic -- '1' if a > b 1820--); 1821--end component; 1822-- 1823--signal high_equals: std_logic; 1824--signal high_lt: std_logic; 1825--signal high_gt: std_logic; 1826-- 1827--signal low_equals: std_logic; 1828--signal low_lt: std_logic; 1829--signal low_gt: std_logic; 1830-- 1831--signal equals: std_logic; 1832--signal less: std_logic; 1833-- 1834--begin 1835-- u1: magnitude port map( 1836-- a => a(6), 1837-- b => b(6), 1838-- equal => high_equals, 1839-- lt => high_lt, 1840-- gt => high_gt 1841-- ); 1842-- 1843-- u2: magnitude6 port map( 1844-- a => a(5 downto 0), 1845-- b => b(5 downto 0), 1846-- equal => low_equals, 1847-- lt => low_lt, 1848-- gt => low_gt 1849-- ); 1850-- 1851-- equals <= high_equals and low_equals; 1852-- less <= high_lt or (high_equals and low_lt); 1853-- gt <= equals nor less; 1854-- equal <= equals; 1855-- lt <= less; 1856--end; 1857-- 1858--library ieee; 1859--use ieee.std_logic_1164.all; 1860-- 1861--entity magnitude8 is 1862--port( 1863-- a, b: in std_logic_vector(7 downto 0); 1864-- equal: out std_logic; 1865-- lt: out std_logic; -- '1' if a < b 1866-- gt: out std_logic -- '1' if a > b 1867--); 1868--end; 1869-- 1870---- tested 2015/12/26 with modelsim, works. 1871--architecture struct_magnitude8 of magnitude8 is 1872--component magnitude7 is 1873--port( 1874-- a, b: in std_logic_vector(6 downto 0); 1875-- equal: out std_logic; 1876-- lt: out std_logic; -- '1' if a < b 1877-- gt: out std_logic -- '1' if a > b 1878--); 1879--end component; 1880-- 1881--component magnitude is 1882--port( 1883-- a, b: in std_logic; 1884-- equal: out std_logic; 1885-- lt: out std_logic; -- '1' if a < b 1886-- gt: out std_logic -- '1' if a > b 1887--); 1888--end component; 1889-- 1890--signal high_equals: std_logic; 1891--signal high_lt: std_logic; 1892--signal high_gt: std_logic; 1893-- 1894--signal low_equals: std_logic; 1895--signal low_lt: std_logic; 1896--signal low_gt: std_logic; 1897-- 1898--signal equals: std_logic; 1899--signal less: std_logic; 1900-- 1901--begin 1902-- u1: magnitude port map( 1903-- a => a(7), 1904-- b => b(7), 1905-- equal => high_equals, 1906-- lt => high_lt, 1907-- gt => high_gt 1908-- ); 1909-- 1910-- u2: magnitude7 port map( 1911-- a => a(6 downto 0), 1912-- b => b(6 downto 0), 1913-- equal => low_equals, 1914-- lt => low_lt, 1915-- gt => low_gt 1916-- ); 1917-- 1918-- equals <= high_equals and low_equals; 1919-- less <= high_lt or (high_equals and low_lt); 1920-- gt <= equals nor less; 1921-- equal <= equals; 1922-- lt <= less; 1923--end; 1924 1925library ieee; 1926use ieee.std_logic_1164.all; 1927 1928entity encoder64x1 is 1929port( 1930 data0: in std_logic; 1931 data1: in std_logic; 1932 data2: in std_logic; 1933 data3: in std_logic; 1934 data4: in std_logic; 1935 data5: in std_logic; 1936 data6: in std_logic; 1937 data7: in std_logic; 1938 data8: in std_logic; 1939 data9: in std_logic; 1940 data10: in std_logic; 1941 data11: in std_logic; 1942 data12: in std_logic; 1943 data13: in std_logic; 1944 data14: in std_logic; 1945 data15: in std_logic; 1946 data16: in std_logic; 1947 data17: in std_logic; 1948 data18: in std_logic; 1949 data19: in std_logic; 1950 data20: in std_logic; 1951 data21: in std_logic; 1952 data22: in std_logic; 1953 data23: in std_logic; 1954 data24: in std_logic; 1955 data25: in std_logic; 1956 data26: in std_logic; 1957 data27: in std_logic; 1958 data28: in std_logic; 1959 data29: in std_logic; 1960 data30: in std_logic; 1961 data31: in std_logic; 1962 data32: in std_logic; 1963 data33: in std_logic; 1964 data34: in std_logic; 1965 data35: in std_logic; 1966 data36: in std_logic; 1967 data37: in std_logic; 1968 data38: in std_logic; 1969 data39: in std_logic; 1970 data40: in std_logic; 1971 data41: in std_logic; 1972 data42: in std_logic; 1973 data43: in std_logic; 1974 data44: in std_logic; 1975 data45: in std_logic; 1976 data46: in std_logic; 1977 data47: in std_logic; 1978 data48: in std_logic; 1979 data49: in std_logic; 1980 data50: in std_logic; 1981 data51: in std_logic; 1982 data52: in std_logic; 1983 data53: in std_logic; 1984 data54: in std_logic; 1985 data55: in std_logic; 1986 data56: in std_logic; 1987 data57: in std_logic; 1988 data58: in std_logic; 1989 data59: in std_logic; 1990 data60: in std_logic; 1991 data61: in std_logic; 1992 data62: in std_logic; 1993 data63: in std_logic; 1994 address: in std_logic_vector(5 downto 0); 1995 output: out std_logic 1996); 1997end; 1998 1999-- tested 2015/12/24 with modelsim as part of encoder64xN. works. 2000 2001architecture struct_encoder64x1 of encoder64x1 is 2002begin 2003 with address select 2004 output <= 2005 data0 when "000000", 2006 data1 when "000001", 2007 data2 when "000010", 2008 data3 when "000011", 2009 data4 when "000100", 2010 data5 when "000101", 2011 data6 when "000110", 2012 data7 when "000111", 2013 data8 when "001000", 2014 data9 when "001001", 2015 data10 when "001010", 2016 data11 when "001011", 2017 data12 when "001100", 2018 data13 when "001101", 2019 data14 when "001110", 2020 data15 when "001111", 2021 data16 when "010000", 2022 data17 when "010001", 2023 data18 when "010010", 2024 data19 when "010011", 2025 data20 when "010100", 2026 data21 when "010101", 2027 data22 when "010110", 2028 data23 when "010111", 2029 data24 when "011000", 2030 data25 when "011001", 2031 data26 when "011010", 2032 data27 when "011011", 2033 data28 when "011100", 2034 data29 when "011101", 2035 data30 when "011110", 2036 data31 when "011111", 2037 data32 when "100000", 2038 data33 when "100001", 2039 data34 when "100010", 2040 data35 when "100011", 2041 data36 when "100100", 2042 data37 when "100101", 2043 data38 when "100110", 2044 data39 when "100111", 2045 data40 when "101000", 2046 data41 when "101001", 2047 data42 when "101010", 2048 data43 when "101011", 2049 data44 when "101100", 2050 data45 when "101101", 2051 data46 when "101110", 2052 data47 when "101111", 2053 data48 when "110000", 2054 data49 when "110001", 2055 data50 when "110010", 2056 data51 when "110011", 2057 data52 when "110100", 2058 data53 when "110101", 2059 data54 when "110110", 2060 data55 when "110111", 2061 data56 when "111000", 2062 data57 when "111001", 2063 data58 when "111010", 2064 data59 when "111011", 2065 data60 when "111100", 2066 data61 when "111101", 2067 data62 when "111110", 2068 data63 when "111111", 2069 '0' when others; 2070end; 2071 2072 2073library ieee; 2074use ieee.std_logic_1164.all; 2075 2076entity encoder64xN is 2077generic( 2078 N: positive 2079); 2080port( 2081 data0: in std_logic_vector((N-1) downto 0); 2082 data1: in std_logic_vector((N-1) downto 0); 2083 data2: in std_logic_vector((N-1) downto 0); 2084 data3: in std_logic_vector((N-1) downto 0); 2085 data4: in std_logic_vector((N-1) downto 0); 2086 data5: in std_logic_vector((N-1) downto 0); 2087 data6: in std_logic_vector((N-1) downto 0); 2088 data7: in std_logic_vector((N-1) downto 0); 2089 data8: in std_logic_vector((N-1) downto 0); 2090 data9: in std_logic_vector((N-1) downto 0); 2091 data10: in std_logic_vector((N-1) downto 0); 2092 data11: in std_logic_vector((N-1) downto 0); 2093 data12: in std_logic_vector((N-1) downto 0); 2094 data13: in std_logic_vector((N-1) downto 0); 2095 data14: in std_logic_vector((N-1) downto 0); 2096 data15: in std_logic_vector((N-1) downto 0); 2097 data16: in std_logic_vector((N-1) downto 0); 2098 data17: in std_logic_vector((N-1) downto 0); 2099 data18: in std_logic_vector((N-1) downto 0); 2100 data19: in std_logic_vector((N-1) downto 0); 2101 data20: in std_logic_vector((N-1) downto 0); 2102 data21: in std_logic_vector((N-1) downto 0); 2103 data22: in std_logic_vector((N-1) downto 0); 2104 data23: in std_logic_vector((N-1) downto 0); 2105 data24: in std_logic_vector((N-1) downto 0); 2106 data25: in std_logic_vector((N-1) downto 0); 2107 data26: in std_logic_vector((N-1) downto 0); 2108 data27: in std_logic_vector((N-1) downto 0); 2109 data28: in std_logic_vector((N-1) downto 0); 2110 data29: in std_logic_vector((N-1) downto 0); 2111 data30: in std_logic_vector((N-1) downto 0); 2112 data31: in std_logic_vector((N-1) downto 0); 2113 data32: in std_logic_vector((N-1) downto 0); 2114 data33: in std_logic_vector((N-1) downto 0); 2115 data34: in std_logic_vector((N-1) downto 0); 2116 data35: in std_logic_vector((N-1) downto 0); 2117 data36: in std_logic_vector((N-1) downto 0); 2118 data37: in std_logic_vector((N-1) downto 0); 2119 data38: in std_logic_vector((N-1) downto 0); 2120 data39: in std_logic_vector((N-1) downto 0); 2121 data40: in std_logic_vector((N-1) downto 0); 2122 data41: in std_logic_vector((N-1) downto 0); 2123 data42: in std_logic_vector((N-1) downto 0); 2124 data43: in std_logic_vector((N-1) downto 0); 2125 data44: in std_logic_vector((N-1) downto 0); 2126 data45: in std_logic_vector((N-1) downto 0); 2127 data46: in std_logic_vector((N-1) downto 0); 2128 data47: in std_logic_vector((N-1) downto 0); 2129 data48: in std_logic_vector((N-1) downto 0); 2130 data49: in std_logic_vector((N-1) downto 0); 2131 data50: in std_logic_vector((N-1) downto 0); 2132 data51: in std_logic_vector((N-1) downto 0); 2133 data52: in std_logic_vector((N-1) downto 0); 2134 data53: in std_logic_vector((N-1) downto 0); 2135 data54: in std_logic_vector((N-1) downto 0); 2136 data55: in std_logic_vector((N-1) downto 0); 2137 data56: in std_logic_vector((N-1) downto 0); 2138 data57: in std_logic_vector((N-1) downto 0); 2139 data58: in std_logic_vector((N-1) downto 0); 2140 data59: in std_logic_vector((N-1) downto 0); 2141 data60: in std_logic_vector((N-1) downto 0); 2142 data61: in std_logic_vector((N-1) downto 0); 2143 data62: in std_logic_vector((N-1) downto 0); 2144 data63: in std_logic_vector((N-1) downto 0); 2145 address: in std_logic_vector(5 downto 0); 2146 output: out std_logic_vector((N-1) downto 0) 2147); 2148end; 2149 2150-- tested 2015/12/24 with modelsim and N = 8. works. 2151 2152architecture struct_encoder64xN of encoder64xN is 2153component encoder64x1 is 2154port( 2155 data0: in std_logic; 2156 data1: in std_logic; 2157 data2: in std_logic; 2158 data3: in std_logic; 2159 data4: in std_logic; 2160 data5: in std_logic; 2161 data6: in std_logic; 2162 data7: in std_logic; 2163 data8: in std_logic; 2164 data9: in std_logic; 2165 data10: in std_logic; 2166 data11: in std_logic; 2167 data12: in std_logic; 2168 data13: in std_logic; 2169 data14: in std_logic; 2170 data15: in std_logic; 2171 data16: in std_logic; 2172 data17: in std_logic; 2173 data18: in std_logic; 2174 data19: in std_logic; 2175 data20: in std_logic; 2176 data21: in std_logic; 2177 data22: in std_logic; 2178 data23: in std_logic; 2179 data24: in std_logic; 2180 data25: in std_logic; 2181 data26: in std_logic; 2182 data27: in std_logic; 2183 data28: in std_logic; 2184 data29: in std_logic; 2185 data30: in std_logic; 2186 data31: in std_logic; 2187 data32: in std_logic; 2188 data33: in std_logic; 2189 data34: in std_logic; 2190 data35: in std_logic; 2191 data36: in std_logic; 2192 data37: in std_logic; 2193 data38: in std_logic; 2194 data39: in std_logic; 2195 data40: in std_logic; 2196 data41: in std_logic; 2197 data42: in std_logic; 2198 data43: in std_logic; 2199 data44: in std_logic; 2200 data45: in std_logic; 2201 data46: in std_logic; 2202 data47: in std_logic; 2203 data48: in std_logic; 2204 data49: in std_logic; 2205 data50: in std_logic; 2206 data51: in std_logic; 2207 data52: in std_logic; 2208 data53: in std_logic; 2209 data54: in std_logic; 2210 data55: in std_logic; 2211 data56: in std_logic; 2212 data57: in std_logic; 2213 data58: in std_logic; 2214 data59: in std_logic; 2215 data60: in std_logic; 2216 data61: in std_logic; 2217 data62: in std_logic; 2218 data63: in std_logic; 2219 address: in std_logic_vector(5 downto 0); 2220 output: out std_logic 2221); 2222end component; 2223 2224begin 2225 u1: for i in 0 to (N-1) generate 2226 u: encoder64x1 port map( 2227 data0 => data0(i), 2228 data1 => data1(i), 2229 data2 => data2(i), 2230 data3 => data3(i), 2231 data4 => data4(i), 2232 data5 => data5(i), 2233 data6 => data6(i), 2234 data7 => data7(i), 2235 data8 => data8(i), 2236 data9 => data9(i), 2237 data10 => data10(i), 2238 data11 => data11(i), 2239 data12 => data12(i), 2240 data13 => data13(i), 2241 data14 => data14(i), 2242 data15 => data15(i), 2243 data16 => data16(i), 2244 data17 => data17(i), 2245 data18 => data18(i), 2246 data19 => data19(i), 2247 data20 => data20(i), 2248 data21 => data21(i), 2249 data22 => data22(i), 2250 data23 => data23(i), 2251 data24 => data24(i), 2252 data25 => data25(i), 2253 data26 => data26(i), 2254 data27 => data27(i), 2255 data28 => data28(i), 2256 data29 => data29(i), 2257 data30 => data30(i), 2258 data31 => data31(i), 2259 data32 => data32(i), 2260 data33 => data33(i), 2261 data34 => data34(i), 2262 data35 => data35(i), 2263 data36 => data36(i), 2264 data37 => data37(i), 2265 data38 => data38(i), 2266 data39 => data39(i), 2267 data40 => data40(i), 2268 data41 => data41(i), 2269 data42 => data42(i), 2270 data43 => data43(i), 2271 data44 => data44(i), 2272 data45 => data45(i), 2273 data46 => data46(i), 2274 data47 => data47(i), 2275 data48 => data48(i), 2276 data49 => data49(i), 2277 data50 => data50(i), 2278 data51 => data51(i), 2279 data52 => data52(i), 2280 data53 => data53(i), 2281 data54 => data54(i), 2282 data55 => data55(i), 2283 data56 => data56(i), 2284 data57 => data57(i), 2285 data58 => data58(i), 2286 data59 => data59(i), 2287 data60 => data60(i), 2288 data61 => data61(i), 2289 data62 => data62(i), 2290 data63 => data63(i), 2291 address => address, 2292 output => output(i) 2293 ); 2294 end generate u1; 2295end; 2296 2297library ieee; 2298use ieee.std_logic_1164.all; 2299 2300entity decoder1x64 is 2301port( 2302 data: in std_logic; 2303 y0: out std_logic; 2304 y1: out std_logic; 2305 y2: out std_logic; 2306 y3: out std_logic; 2307 y4: out std_logic; 2308 y5: out std_logic; 2309 y6: out std_logic; 2310 y7: out std_logic; 2311 y8: out std_logic; 2312 y9: out std_logic; 2313 y10: out std_logic; 2314 y11: out std_logic; 2315 y12: out std_logic; 2316 y13: out std_logic; 2317 y14: out std_logic; 2318 y15: out std_logic; 2319 y16: out std_logic; 2320 y17: out std_logic; 2321 y18: out std_logic; 2322 y19: out std_logic; 2323 y20: out std_logic; 2324 y21: out std_logic; 2325 y22: out std_logic; 2326 y23: out std_logic; 2327 y24: out std_logic; 2328 y25: out std_logic; 2329 y26: out std_logic; 2330 y27: out std_logic; 2331 y28: out std_logic; 2332 y29: out std_logic; 2333 y30: out std_logic; 2334 y31: out std_logic; 2335 y32: out std_logic; 2336 y33: out std_logic; 2337 y34: out std_logic; 2338 y35: out std_logic; 2339 y36: out std_logic; 2340 y37: out std_logic; 2341 y38: out std_logic; 2342 y39: out std_logic; 2343 y40: out std_logic; 2344 y41: out std_logic; 2345 y42: out std_logic; 2346 y43: out std_logic; 2347 y44: out std_logic; 2348 y45: out std_logic; 2349 y46: out std_logic; 2350 y47: out std_logic; 2351 y48: out std_logic; 2352 y49: out std_logic; 2353 y50: out std_logic; 2354 y51: out std_logic; 2355 y52: out std_logic; 2356 y53: out std_logic; 2357 y54: out std_logic; 2358 y55: out std_logic; 2359 y56: out std_logic; 2360 y57: out std_logic; 2361 y58: out std_logic; 2362 y59: out std_logic; 2363 y60: out std_logic; 2364 y61: out std_logic; 2365 y62: out std_logic; 2366 y63: out std_logic; 2367 address: in std_logic_vector(5 downto 0) 2368); 2369end; 2370 2371-- tested 2015/12/26 as part of decoderNx64 using modelsim. works. 2372 2373architecture struct_decoder1x64 of decoder1x64 is 2374begin 2375 with address select y0 <= data when "000000", '0' when others; 2376 with address select y1 <= data when "000001", '0' when others; 2377 with address select y2 <= data when "000010", '0' when others; 2378 with address select y3 <= data when "000011", '0' when others; 2379 with address select y4 <= data when "000100", '0' when others; 2380 with address select y5 <= data when "000101", '0' when others; 2381 with address select y6 <= data when "000110", '0' when others; 2382 with address select y7 <= data when "000111", '0' when others; 2383 with address select y8 <= data when "001000", '0' when others; 2384 with address select y9 <= data when "001001", '0' when others; 2385 with address select y10 <= data when "001010", '0' when others; 2386 with address select y11 <= data when "001011", '0' when others; 2387 with address select y12 <= data when "001100", '0' when others; 2388 with address select y13 <= data when "001101", '0' when others; 2389 with address select y14 <= data when "001110", '0' when others; 2390 with address select y15 <= data when "001111", '0' when others; 2391 with address select y16 <= data when "010000", '0' when others; 2392 with address select y17 <= data when "010001", '0' when others; 2393 with address select y18 <= data when "010010", '0' when others; 2394 with address select y19 <= data when "010011", '0' when others; 2395 with address select y20 <= data when "010100", '0' when others; 2396 with address select y21 <= data when "010101", '0' when others; 2397 with address select y22 <= data when "010110", '0' when others; 2398 with address select y23 <= data when "010111", '0' when others; 2399 with address select y24 <= data when "011000", '0' when others; 2400 with address select y25 <= data when "011001", '0' when others; 2401 with address select y26 <= data when "011010", '0' when others; 2402 with address select y27 <= data when "011011", '0' when others; 2403 with address select y28 <= data when "011100", '0' when others; 2404 with address select y29 <= data when "011101", '0' when others; 2405 with address select y30 <= data when "011110", '0' when others; 2406 with address select y31 <= data when "011111", '0' when others; 2407 with address select y32 <= data when "100000", '0' when others; 2408 with address select y33 <= data when "100001", '0' when others; 2409 with address select y34 <= data when "100010", '0' when others; 2410 with address select y35 <= data when "100011", '0' when others; 2411 with address select y36 <= data when "100100", '0' when others; 2412 with address select y37 <= data when "100101", '0' when others; 2413 with address select y38 <= data when "100110", '0' when others; 2414 with address select y39 <= data when "100111", '0' when others; 2415 with address select y40 <= data when "101000", '0' when others; 2416 with address select y41 <= data when "101001", '0' when others; 2417 with address select y42 <= data when "101010", '0' when others; 2418 with address select y43 <= data when "101011", '0' when others; 2419 with address select y44 <= data when "101100", '0' when others; 2420 with address select y45 <= data when "101101", '0' when others; 2421 with address select y46 <= data when "101110", '0' when others; 2422 with address select y47 <= data when "101111", '0' when others; 2423 with address select y48 <= data when "110000", '0' when others; 2424 with address select y49 <= data when "110001", '0' when others; 2425 with address select y50 <= data when "110010", '0' when others; 2426 with address select y51 <= data when "110011", '0' when others; 2427 with address select y52 <= data when "110100", '0' when others; 2428 with address select y53 <= data when "110101", '0' when others; 2429 with address select y54 <= data when "110110", '0' when others; 2430 with address select y55 <= data when "110111", '0' when others; 2431 with address select y56 <= data when "111000", '0' when others; 2432 with address select y57 <= data when "111001", '0' when others; 2433 with address select y58 <= data when "111010", '0' when others; 2434 with address select y59 <= data when "111011", '0' when others; 2435 with address select y60 <= data when "111100", '0' when others; 2436 with address select y61 <= data when "111101", '0' when others; 2437 with address select y62 <= data when "111110", '0' when others; 2438 with address select y63 <= data when "111111", '0' when others; 2439end; 2440 2441library ieee; 2442use ieee.std_logic_1164.all; 2443 2444entity decoderNx64 is 2445generic( 2446 N: positive 2447); 2448port( 2449 data: in std_logic_vector((N-1) downto 0); 2450 y0: out std_logic_vector((N-1) downto 0); 2451 y1: out std_logic_vector((N-1) downto 0); 2452 y2: out std_logic_vector((N-1) downto 0); 2453 y3: out std_logic_vector((N-1) downto 0); 2454 y4: out std_logic_vector((N-1) downto 0); 2455 y5: out std_logic_vector((N-1) downto 0); 2456 y6: out std_logic_vector((N-1) downto 0); 2457 y7: out std_logic_vector((N-1) downto 0); 2458 y8: out std_logic_vector((N-1) downto 0); 2459 y9: out std_logic_vector((N-1) downto 0); 2460 y10: out std_logic_vector((N-1) downto 0); 2461 y11: out std_logic_vector((N-1) downto 0); 2462 y12: out std_logic_vector((N-1) downto 0); 2463 y13: out std_logic_vector((N-1) downto 0); 2464 y14: out std_logic_vector((N-1) downto 0); 2465 y15: out std_logic_vector((N-1) downto 0); 2466 y16: out std_logic_vector((N-1) downto 0); 2467 y17: out std_logic_vector((N-1) downto 0); 2468 y18: out std_logic_vector((N-1) downto 0); 2469 y19: out std_logic_vector((N-1) downto 0); 2470 y20: out std_logic_vector((N-1) downto 0); 2471 y21: out std_logic_vector((N-1) downto 0); 2472 y22: out std_logic_vector((N-1) downto 0); 2473 y23: out std_logic_vector((N-1) downto 0); 2474 y24: out std_logic_vector((N-1) downto 0); 2475 y25: out std_logic_vector((N-1) downto 0); 2476 y26: out std_logic_vector((N-1) downto 0); 2477 y27: out std_logic_vector((N-1) downto 0); 2478 y28: out std_logic_vector((N-1) downto 0); 2479 y29: out std_logic_vector((N-1) downto 0); 2480 y30: out std_logic_vector((N-1) downto 0); 2481 y31: out std_logic_vector((N-1) downto 0); 2482 y32: out std_logic_vector((N-1) downto 0); 2483 y33: out std_logic_vector((N-1) downto 0); 2484 y34: out std_logic_vector((N-1) downto 0); 2485 y35: out std_logic_vector((N-1) downto 0); 2486 y36: out std_logic_vector((N-1) downto 0); 2487 y37: out std_logic_vector((N-1) downto 0); 2488 y38: out std_logic_vector((N-1) downto 0); 2489 y39: out std_logic_vector((N-1) downto 0); 2490 y40: out std_logic_vector((N-1) downto 0); 2491 y41: out std_logic_vector((N-1) downto 0); 2492 y42: out std_logic_vector((N-1) downto 0); 2493 y43: out std_logic_vector((N-1) downto 0); 2494 y44: out std_logic_vector((N-1) downto 0); 2495 y45: out std_logic_vector((N-1) downto 0); 2496 y46: out std_logic_vector((N-1) downto 0); 2497 y47: out std_logic_vector((N-1) downto 0); 2498 y48: out std_logic_vector((N-1) downto 0); 2499 y49: out std_logic_vector((N-1) downto 0); 2500 y50: out std_logic_vector((N-1) downto 0); 2501 y51: out std_logic_vector((N-1) downto 0); 2502 y52: out std_logic_vector((N-1) downto 0); 2503 y53: out std_logic_vector((N-1) downto 0); 2504 y54: out std_logic_vector((N-1) downto 0); 2505 y55: out std_logic_vector((N-1) downto 0); 2506 y56: out std_logic_vector((N-1) downto 0); 2507 y57: out std_logic_vector((N-1) downto 0); 2508 y58: out std_logic_vector((N-1) downto 0); 2509 y59: out std_logic_vector((N-1) downto 0); 2510 y60: out std_logic_vector((N-1) downto 0); 2511 y61: out std_logic_vector((N-1) downto 0); 2512 y62: out std_logic_vector((N-1) downto 0); 2513 y63: out std_logic_vector((N-1) downto 0); 2514 address: in std_logic_vector(5 downto 0) 2515); 2516end; 2517 2518-- tested 2015/12/26 with N = 8 using modelsim. works. 2519 2520architecture struct_decoderNx64 of decoderNx64 is 2521component decoder1x64 is 2522port( 2523 data: in std_logic; 2524 y0: out std_logic; 2525 y1: out std_logic; 2526 y2: out std_logic; 2527 y3: out std_logic; 2528 y4: out std_logic; 2529 y5: out std_logic; 2530 y6: out std_logic; 2531 y7: out std_logic; 2532 y8: out std_logic; 2533 y9: out std_logic; 2534 y10: out std_logic; 2535 y11: out std_logic; 2536 y12: out std_logic; 2537 y13: out std_logic; 2538 y14: out std_logic; 2539 y15: out std_logic; 2540 y16: out std_logic; 2541 y17: out std_logic; 2542 y18: out std_logic; 2543 y19: out std_logic; 2544 y20: out std_logic; 2545 y21: out std_logic; 2546 y22: out std_logic; 2547 y23: out std_logic; 2548 y24: out std_logic; 2549 y25: out std_logic; 2550 y26: out std_logic; 2551 y27: out std_logic; 2552 y28: out std_logic; 2553 y29: out std_logic; 2554 y30: out std_logic; 2555 y31: out std_logic; 2556 y32: out std_logic; 2557 y33: out std_logic; 2558 y34: out std_logic; 2559 y35: out std_logic; 2560 y36: out std_logic; 2561 y37: out std_logic; 2562 y38: out std_logic; 2563 y39: out std_logic; 2564 y40: out std_logic; 2565 y41: out std_logic; 2566 y42: out std_logic; 2567 y43: out std_logic; 2568 y44: out std_logic; 2569 y45: out std_logic; 2570 y46: out std_logic; 2571 y47: out std_logic; 2572 y48: out std_logic; 2573 y49: out std_logic; 2574 y50: out std_logic; 2575 y51: out std_logic; 2576 y52: out std_logic; 2577 y53: out std_logic; 2578 y54: out std_logic; 2579 y55: out std_logic; 2580 y56: out std_logic; 2581 y57: out std_logic; 2582 y58: out std_logic; 2583 y59: out std_logic; 2584 y60: out std_logic; 2585 y61: out std_logic; 2586 y62: out std_logic; 2587 y63: out std_logic; 2588 address: in std_logic_vector(5 downto 0) 2589); 2590end component; 2591 2592begin 2593 u1: for i in 0 to (N-1) generate 2594 u: decoder1x64 port map( 2595 data => data(i), 2596 y0 => y0(i), 2597 y1 => y1(i), 2598 y2 => y2(i), 2599 y3 => y3(i), 2600 y4 => y4(i), 2601 y5 => y5(i), 2602 y6 => y6(i), 2603 y7 => y7(i), 2604 y8 => y8(i), 2605 y9 => y9(i), 2606 y10 => y10(i), 2607 y11 => y11(i), 2608 y12 => y12(i), 2609 y13 => y13(i), 2610 y14 => y14(i), 2611 y15 => y15(i), 2612 y16 => y16(i), 2613 y17 => y17(i), 2614 y18 => y18(i), 2615 y19 => y19(i), 2616 y20 => y20(i), 2617 y21 => y21(i), 2618 y22 => y22(i), 2619 y23 => y23(i), 2620 y24 => y24(i), 2621 y25 => y25(i), 2622 y26 => y26(i), 2623 y27 => y27(i), 2624 y28 => y28(i), 2625 y29 => y29(i), 2626 y30 => y30(i), 2627 y31 => y31(i), 2628 y32 => y32(i), 2629 y33 => y33(i), 2630 y34 => y34(i), 2631 y35 => y35(i), 2632 y36 => y36(i), 2633 y37 => y37(i), 2634 y38 => y38(i), 2635 y39 => y39(i), 2636 y40 => y40(i), 2637 y41 => y41(i), 2638 y42 => y42(i), 2639 y43 => y43(i), 2640 y44 => y44(i), 2641 y45 => y45(i), 2642 y46 => y46(i), 2643 y47 => y47(i), 2644 y48 => y48(i), 2645 y49 => y49(i), 2646 y50 => y50(i), 2647 y51 => y51(i), 2648 y52 => y52(i), 2649 y53 => y53(i), 2650 y54 => y54(i), 2651 y55 => y55(i), 2652 y56 => y56(i), 2653 y57 => y57(i), 2654 y58 => y58(i), 2655 y59 => y59(i), 2656 y60 => y60(i), 2657 y61 => y61(i), 2658 y62 => y62(i), 2659 y63 => y63(i), 2660 address => address 2661 ); 2662 end generate; 2663end; 2664 2665library ieee; 2666use ieee.std_logic_1164.all; 2667 2668entity decoder1x32 is 2669port( 2670 data: in std_logic; 2671 y0: out std_logic; 2672 y1: out std_logic; 2673 y2: out std_logic; 2674 y3: out std_logic; 2675 y4: out std_logic; 2676 y5: out std_logic; 2677 y6: out std_logic; 2678 y7: out std_logic; 2679 y8: out std_logic; 2680 y9: out std_logic; 2681 y10: out std_logic; 2682 y11: out std_logic; 2683 y12: out std_logic; 2684 y13: out std_logic; 2685 y14: out std_logic; 2686 y15: out std_logic; 2687 y16: out std_logic; 2688 y17: out std_logic; 2689 y18: out std_logic; 2690 y19: out std_logic; 2691 y20: out std_logic; 2692 y21: out std_logic; 2693 y22: out std_logic; 2694 y23: out std_logic; 2695 y24: out std_logic; 2696 y25: out std_logic; 2697 y26: out std_logic; 2698 y27: out std_logic; 2699 y28: out std_logic; 2700 y29: out std_logic; 2701 y30: out std_logic; 2702 y31: out std_logic; 2703 address: in std_logic_vector(4 downto 0) 2704); 2705end; 2706 2707-- tested 2015/12/25 as part of decoderNx32 with modelsim, works. 2708 2709architecture struct_decoder1x32 of decoder1x32 is 2710begin 2711 with address select y0 <= data when "00000", '0' when others; 2712 with address select y1 <= data when "00001", '0' when others; 2713 with address select y2 <= data when "00010", '0' when others; 2714 with address select y3 <= data when "00011", '0' when others; 2715 with address select y4 <= data when "00100", '0' when others; 2716 with address select y5 <= data when "00101", '0' when others; 2717 with address select y6 <= data when "00110", '0' when others; 2718 with address select y7 <= data when "00111", '0' when others; 2719 with address select y8 <= data when "01000", '0' when others; 2720 with address select y9 <= data when "01001", '0' when others; 2721 with address select y10 <= data when "01010", '0' when others; 2722 with address select y11 <= data when "01011", '0' when others; 2723 with address select y12 <= data when "01100", '0' when others; 2724 with address select y13 <= data when "01101", '0' when others; 2725 with address select y14 <= data when "01110", '0' when others; 2726 with address select y15 <= data when "01111", '0' when others; 2727 with address select y16 <= data when "10000", '0' when others; 2728 with address select y17 <= data when "10001", '0' when others; 2729 with address select y18 <= data when "10010", '0' when others; 2730 with address select y19 <= data when "10011", '0' when others; 2731 with address select y20 <= data when "10100", '0' when others; 2732 with address select y21 <= data when "10101", '0' when others; 2733 with address select y22 <= data when "10110", '0' when others; 2734 with address select y23 <= data when "10111", '0' when others; 2735 with address select y24 <= data when "11000", '0' when others; 2736 with address select y25 <= data when "11001", '0' when others; 2737 with address select y26 <= data when "11010", '0' when others; 2738 with address select y27 <= data when "11011", '0' when others; 2739 with address select y28 <= data when "11100", '0' when others; 2740 with address select y29 <= data when "11101", '0' when others; 2741 with address select y30 <= data when "11110", '0' when others; 2742 with address select y31 <= data when "11111", '0' when others; 2743end; 2744 2745library ieee; 2746use ieee.std_logic_1164.all; 2747 2748entity decoderNx32 is 2749generic( 2750 N: positive 2751); 2752port( 2753 data: in std_logic_vector((N-1) downto 0); 2754 y0: out std_logic_vector((N-1) downto 0); 2755 y1: out std_logic_vector((N-1) downto 0); 2756 y2: out std_logic_vector((N-1) downto 0); 2757 y3: out std_logic_vector((N-1) downto 0); 2758 y4: out std_logic_vector((N-1) downto 0); 2759 y5: out std_logic_vector((N-1) downto 0); 2760 y6: out std_logic_vector((N-1) downto 0); 2761 y7: out std_logic_vector((N-1) downto 0); 2762 y8: out std_logic_vector((N-1) downto 0); 2763 y9: out std_logic_vector((N-1) downto 0); 2764 y10: out std_logic_vector((N-1) downto 0); 2765 y11: out std_logic_vector((N-1) downto 0); 2766 y12: out std_logic_vector((N-1) downto 0); 2767 y13: out std_logic_vector((N-1) downto 0); 2768 y14: out std_logic_vector((N-1) downto 0); 2769 y15: out std_logic_vector((N-1) downto 0); 2770 y16: out std_logic_vector((N-1) downto 0); 2771 y17: out std_logic_vector((N-1) downto 0); 2772 y18: out std_logic_vector((N-1) downto 0); 2773 y19: out std_logic_vector((N-1) downto 0); 2774 y20: out std_logic_vector((N-1) downto 0); 2775 y21: out std_logic_vector((N-1) downto 0); 2776 y22: out std_logic_vector((N-1) downto 0); 2777 y23: out std_logic_vector((N-1) downto 0); 2778 y24: out std_logic_vector((N-1) downto 0); 2779 y25: out std_logic_vector((N-1) downto 0); 2780 y26: out std_logic_vector((N-1) downto 0); 2781 y27: out std_logic_vector((N-1) downto 0); 2782 y28: out std_logic_vector((N-1) downto 0); 2783 y29: out std_logic_vector((N-1) downto 0); 2784 y30: out std_logic_vector((N-1) downto 0); 2785 y31: out std_logic_vector((N-1) downto 0); 2786 address: in std_logic_vector(4 downto 0) 2787); 2788end; 2789 2790-- tested 2015/12/25 with modelsim and N = 8, works. 2791-- reverified with correct report statements 2015/12/26, works. 2792 2793architecture struct_decoderNx32 of decoderNx32 is 2794component decoder1x32 is 2795port( 2796 data: in std_logic; 2797 y0: out std_logic; 2798 y1: out std_logic; 2799 y2: out std_logic; 2800 y3: out std_logic; 2801 y4: out std_logic; 2802 y5: out std_logic; 2803 y6: out std_logic; 2804 y7: out std_logic; 2805 y8: out std_logic; 2806 y9: out std_logic; 2807 y10: out std_logic; 2808 y11: out std_logic; 2809 y12: out std_logic; 2810 y13: out std_logic; 2811 y14: out std_logic; 2812 y15: out std_logic; 2813 y16: out std_logic; 2814 y17: out std_logic; 2815 y18: out std_logic; 2816 y19: out std_logic; 2817 y20: out std_logic; 2818 y21: out std_logic; 2819 y22: out std_logic; 2820 y23: out std_logic; 2821 y24: out std_logic; 2822 y25: out std_logic; 2823 y26: out std_logic; 2824 y27: out std_logic; 2825 y28: out std_logic; 2826 y29: out std_logic; 2827 y30: out std_logic; 2828 y31: out std_logic; 2829 address: in std_logic_vector(4 downto 0) 2830); 2831end component; 2832 2833begin 2834 u1: for i in 0 to (N-1) generate 2835 u: decoder1x32 port map( 2836 data => data(i), 2837 y0 => y0(i), 2838 y1 => y1(i), 2839 y2 => y2(i), 2840 y3 => y3(i), 2841 y4 => y4(i), 2842 y5 => y5(i), 2843 y6 => y6(i), 2844 y7 => y7(i), 2845 y8 => y8(i), 2846 y9 => y9(i), 2847 y10 => y10(i), 2848 y11 => y11(i), 2849 y12 => y12(i), 2850 y13 => y13(i), 2851 y14 => y14(i), 2852 y15 => y15(i), 2853 y16 => y16(i), 2854 y17 => y17(i), 2855 y18 => y18(i), 2856 y19 => y19(i), 2857 y20 => y20(i), 2858 y21 => y21(i), 2859 y22 => y22(i), 2860 y23 => y23(i), 2861 y24 => y24(i), 2862 y25 => y25(i), 2863 y26 => y26(i), 2864 y27 => y27(i), 2865 y28 => y28(i), 2866 y29 => y29(i), 2867 y30 => y30(i), 2868 y31 => y31(i), 2869 address => address 2870 ); 2871 end generate u1; 2872end; 2873 2874library ieee; 2875use ieee.std_logic_1164.all; 2876 2877entity encoder128x1 is 2878port( 2879 data0: in std_logic; 2880 data1: in std_logic; 2881 data2: in std_logic; 2882 data3: in std_logic; 2883 data4: in std_logic; 2884 data5: in std_logic; 2885 data6: in std_logic; 2886 data7: in std_logic; 2887 data8: in std_logic; 2888 data9: in std_logic; 2889 data10: in std_logic; 2890 data11: in std_logic; 2891 data12: in std_logic; 2892 data13: in std_logic; 2893 data14: in std_logic; 2894 data15: in std_logic; 2895 data16: in std_logic; 2896 data17: in std_logic; 2897 data18: in std_logic; 2898 data19: in std_logic; 2899 data20: in std_logic; 2900 data21: in std_logic; 2901 data22: in std_logic; 2902 data23: in std_logic; 2903 data24: in std_logic; 2904 data25: in std_logic; 2905 data26: in std_logic; 2906 data27: in std_logic; 2907 data28: in std_logic; 2908 data29: in std_logic; 2909 data30: in std_logic; 2910 data31: in std_logic; 2911 data32: in std_logic; 2912 data33: in std_logic; 2913 data34: in std_logic; 2914 data35: in std_logic; 2915 data36: in std_logic; 2916 data37: in std_logic; 2917 data38: in std_logic; 2918 data39: in std_logic; 2919 data40: in std_logic; 2920 data41: in std_logic; 2921 data42: in std_logic; 2922 data43: in std_logic; 2923 data44: in std_logic; 2924 data45: in std_logic; 2925 data46: in std_logic; 2926 data47: in std_logic; 2927 data48: in std_logic; 2928 data49: in std_logic; 2929 data50: in std_logic; 2930 data51: in std_logic; 2931 data52: in std_logic; 2932 data53: in std_logic; 2933 data54: in std_logic; 2934 data55: in std_logic; 2935 data56: in std_logic; 2936 data57: in std_logic; 2937 data58: in std_logic; 2938 data59: in std_logic; 2939 data60: in std_logic; 2940 data61: in std_logic; 2941 data62: in std_logic; 2942 data63: in std_logic; 2943 data64: in std_logic; 2944 data65: in std_logic; 2945 data66: in std_logic; 2946 data67: in std_logic; 2947 data68: in std_logic; 2948 data69: in std_logic; 2949 data70: in std_logic; 2950 data71: in std_logic; 2951 data72: in std_logic; 2952 data73: in std_logic; 2953 data74: in std_logic; 2954 data75: in std_logic; 2955 data76: in std_logic; 2956 data77: in std_logic; 2957 data78: in std_logic; 2958 data79: in std_logic; 2959 data80: in std_logic; 2960 data81: in std_logic; 2961 data82: in std_logic; 2962 data83: in std_logic; 2963 data84: in std_logic; 2964 data85: in std_logic; 2965 data86: in std_logic; 2966 data87: in std_logic; 2967 data88: in std_logic; 2968 data89: in std_logic; 2969 data90: in std_logic; 2970 data91: in std_logic; 2971 data92: in std_logic; 2972 data93: in std_logic; 2973 data94: in std_logic; 2974 data95: in std_logic; 2975 data96: in std_logic; 2976 data97: in std_logic; 2977 data98: in std_logic; 2978 data99: in std_logic; 2979 data100: in std_logic; 2980 data101: in std_logic; 2981 data102: in std_logic; 2982 data103: in std_logic; 2983 data104: in std_logic; 2984 data105: in std_logic; 2985 data106: in std_logic; 2986 data107: in std_logic; 2987 data108: in std_logic; 2988 data109: in std_logic; 2989 data110: in std_logic; 2990 data111: in std_logic; 2991 data112: in std_logic; 2992 data113: in std_logic; 2993 data114: in std_logic; 2994 data115: in std_logic; 2995 data116: in std_logic; 2996 data117: in std_logic; 2997 data118: in std_logic; 2998 data119: in std_logic; 2999 data120: in std_logic; 3000 data121: in std_logic; 3001 data122: in std_logic; 3002 data123: in std_logic; 3003 data124: in std_logic; 3004 data125: in std_logic; 3005 data126: in std_logic; 3006 data127: in std_logic; 3007 address: in std_logic_vector(6 downto 0); 3008 output: out std_logic 3009); 3010end; 3011 3012architecture struct_encoder128x1 of encoder128x1 is 3013begin 3014 with address select 3015 output <= 3016 data0 when "0000000", 3017 data1 when "0000001", 3018 data2 when "0000010", 3019 data3 when "0000011", 3020 data4 when "0000100", 3021 data5 when "0000101", 3022 data6 when "0000110", 3023 data7 when "0000111", 3024 data8 when "0001000", 3025 data9 when "0001001", 3026 data10 when "0001010", 3027 data11 when "0001011", 3028 data12 when "0001100", 3029 data13 when "0001101", 3030 data14 when "0001110", 3031 data15 when "0001111", 3032 data16 when "0010000", 3033 data17 when "0010001", 3034 data18 when "0010010", 3035 data19 when "0010011", 3036 data20 when "0010100", 3037 data21 when "0010101", 3038 data22 when "0010110", 3039 data23 when "0010111", 3040 data24 when "0011000", 3041 data25 when "0011001", 3042 data26 when "0011010", 3043 data27 when "0011011", 3044 data28 when "0011100", 3045 data29 when "0011101", 3046 data30 when "0011110", 3047 data31 when "0011111", 3048 data32 when "0100000", 3049 data33 when "0100001", 3050 data34 when "0100010", 3051 data35 when "0100011", 3052 data36 when "0100100", 3053 data37 when "0100101", 3054 data38 when "0100110", 3055 data39 when "0100111", 3056 data40 when "0101000", 3057 data41 when "0101001", 3058 data42 when "0101010", 3059 data43 when "0101011", 3060 data44 when "0101100", 3061 data45 when "0101101", 3062 data46 when "0101110", 3063 data47 when "0101111", 3064 data48 when "0110000", 3065 data49 when "0110001", 3066 data50 when "0110010", 3067 data51 when "0110011", 3068 data52 when "0110100", 3069 data53 when "0110101", 3070 data54 when "0110110", 3071 data55 when "0110111", 3072 data56 when "0111000", 3073 data57 when "0111001", 3074 data58 when "0111010", 3075 data59 when "0111011", 3076 data60 when "0111100", 3077 data61 when "0111101", 3078 data62 when "0111110", 3079 data63 when "0111111", 3080 data64 when "1000000", 3081 data65 when "1000001", 3082 data66 when "1000010", 3083 data67 when "1000011", 3084 data68 when "1000100", 3085 data69 when "1000101", 3086 data70 when "1000110", 3087 data71 when "1000111", 3088 data72 when "1001000", 3089 data73 when "1001001", 3090 data74 when "1001010", 3091 data75 when "1001011", 3092 data76 when "1001100", 3093 data77 when "1001101", 3094 data78 when "1001110", 3095 data79 when "1001111", 3096 data80 when "1010000", 3097 data81 when "1010001", 3098 data82 when "1010010", 3099 data83 when "1010011", 3100 data84 when "1010100", 3101 data85 when "1010101", 3102 data86 when "1010110", 3103 data87 when "1010111", 3104 data88 when "1011000", 3105 data89 when "1011001", 3106 data90 when "1011010", 3107 data91 when "1011011", 3108 data92 when "1011100", 3109 data93 when "1011101", 3110 data94 when "1011110", 3111 data95 when "1011111", 3112 data96 when "1100000", 3113 data97 when "1100001", 3114 data98 when "1100010", 3115 data99 when "1100011", 3116 data100 when "1100100", 3117 data101 when "1100101", 3118 data102 when "1100110", 3119 data103 when "1100111", 3120 data104 when "1101000", 3121 data105 when "1101001", 3122 data106 when "1101010", 3123 data107 when "1101011", 3124 data108 when "1101100", 3125 data109 when "1101101", 3126 data110 when "1101110", 3127 data111 when "1101111", 3128 data112 when "1110000", 3129 data113 when "1110001", 3130 data114 when "1110010", 3131 data115 when "1110011", 3132 data116 when "1110100", 3133 data117 when "1110101", 3134 data118 when "1110110", 3135 data119 when "1110111", 3136 data120 when "1111000", 3137 data121 when "1111001", 3138 data122 when "1111010", 3139 data123 when "1111011", 3140 data124 when "1111100", 3141 data125 when "1111101", 3142 data126 when "1111110", 3143 data127 when "1111111", 3144 '0' when others; 3145end; 3146 3147library ieee; 3148use ieee.std_logic_1164.all; 3149 3150entity encoder128xN is 3151generic( 3152 N: positive 3153); 3154port( 3155 data0: in std_logic_vector((N-1) downto 0); 3156 data1: in std_logic_vector((N-1) downto 0); 3157 data2: in std_logic_vector((N-1) downto 0); 3158 data3: in std_logic_vector((N-1) downto 0); 3159 data4: in std_logic_vector((N-1) downto 0); 3160 data5: in std_logic_vector((N-1) downto 0); 3161 data6: in std_logic_vector((N-1) downto 0); 3162 data7: in std_logic_vector((N-1) downto 0); 3163 data8: in std_logic_vector((N-1) downto 0); 3164 data9: in std_logic_vector((N-1) downto 0); 3165 data10: in std_logic_vector((N-1) downto 0); 3166 data11: in std_logic_vector((N-1) downto 0); 3167 data12: in std_logic_vector((N-1) downto 0); 3168 data13: in std_logic_vector((N-1) downto 0); 3169 data14: in std_logic_vector((N-1) downto 0); 3170 data15: in std_logic_vector((N-1) downto 0); 3171 data16: in std_logic_vector((N-1) downto 0); 3172 data17: in std_logic_vector((N-1) downto 0); 3173 data18: in std_logic_vector((N-1) downto 0); 3174 data19: in std_logic_vector((N-1) downto 0); 3175 data20: in std_logic_vector((N-1) downto 0); 3176 data21: in std_logic_vector((N-1) downto 0); 3177 data22: in std_logic_vector((N-1) downto 0); 3178 data23: in std_logic_vector((N-1) downto 0); 3179 data24: in std_logic_vector((N-1) downto 0); 3180 data25: in std_logic_vector((N-1) downto 0); 3181 data26: in std_logic_vector((N-1) downto 0); 3182 data27: in std_logic_vector((N-1) downto 0); 3183 data28: in std_logic_vector((N-1) downto 0); 3184 data29: in std_logic_vector((N-1) downto 0); 3185 data30: in std_logic_vector((N-1) downto 0); 3186 data31: in std_logic_vector((N-1) downto 0); 3187 data32: in std_logic_vector((N-1) downto 0); 3188 data33: in std_logic_vector((N-1) downto 0); 3189 data34: in std_logic_vector((N-1) downto 0); 3190 data35: in std_logic_vector((N-1) downto 0); 3191 data36: in std_logic_vector((N-1) downto 0); 3192 data37: in std_logic_vector((N-1) downto 0); 3193 data38: in std_logic_vector((N-1) downto 0); 3194 data39: in std_logic_vector((N-1) downto 0); 3195 data40: in std_logic_vector((N-1) downto 0); 3196 data41: in std_logic_vector((N-1) downto 0); 3197 data42: in std_logic_vector((N-1) downto 0); 3198 data43: in std_logic_vector((N-1) downto 0); 3199 data44: in std_logic_vector((N-1) downto 0); 3200 data45: in std_logic_vector((N-1) downto 0); 3201 data46: in std_logic_vector((N-1) downto 0); 3202 data47: in std_logic_vector((N-1) downto 0); 3203 data48: in std_logic_vector((N-1) downto 0); 3204 data49: in std_logic_vector((N-1) downto 0); 3205 data50: in std_logic_vector((N-1) downto 0); 3206 data51: in std_logic_vector((N-1) downto 0); 3207 data52: in std_logic_vector((N-1) downto 0); 3208 data53: in std_logic_vector((N-1) downto 0); 3209 data54: in std_logic_vector((N-1) downto 0); 3210 data55: in std_logic_vector((N-1) downto 0); 3211 data56: in std_logic_vector((N-1) downto 0); 3212 data57: in std_logic_vector((N-1) downto 0); 3213 data58: in std_logic_vector((N-1) downto 0); 3214 data59: in std_logic_vector((N-1) downto 0); 3215 data60: in std_logic_vector((N-1) downto 0); 3216 data61: in std_logic_vector((N-1) downto 0); 3217 data62: in std_logic_vector((N-1) downto 0); 3218 data63: in std_logic_vector((N-1) downto 0); 3219 data64: in std_logic_vector((N-1) downto 0); 3220 data65: in std_logic_vector((N-1) downto 0); 3221 data66: in std_logic_vector((N-1) downto 0); 3222 data67: in std_logic_vector((N-1) downto 0); 3223 data68: in std_logic_vector((N-1) downto 0); 3224 data69: in std_logic_vector((N-1) downto 0); 3225 data70: in std_logic_vector((N-1) downto 0); 3226 data71: in std_logic_vector((N-1) downto 0); 3227 data72: in std_logic_vector((N-1) downto 0); 3228 data73: in std_logic_vector((N-1) downto 0); 3229 data74: in std_logic_vector((N-1) downto 0); 3230 data75: in std_logic_vector((N-1) downto 0); 3231 data76: in std_logic_vector((N-1) downto 0); 3232 data77: in std_logic_vector((N-1) downto 0); 3233 data78: in std_logic_vector((N-1) downto 0); 3234 data79: in std_logic_vector((N-1) downto 0); 3235 data80: in std_logic_vector((N-1) downto 0); 3236 data81: in std_logic_vector((N-1) downto 0); 3237 data82: in std_logic_vector((N-1) downto 0); 3238 data83: in std_logic_vector((N-1) downto 0); 3239 data84: in std_logic_vector((N-1) downto 0); 3240 data85: in std_logic_vector((N-1) downto 0); 3241 data86: in std_logic_vector((N-1) downto 0); 3242 data87: in std_logic_vector((N-1) downto 0); 3243 data88: in std_logic_vector((N-1) downto 0); 3244 data89: in std_logic_vector((N-1) downto 0); 3245 data90: in std_logic_vector((N-1) downto 0); 3246 data91: in std_logic_vector((N-1) downto 0); 3247 data92: in std_logic_vector((N-1) downto 0); 3248 data93: in std_logic_vector((N-1) downto 0); 3249 data94: in std_logic_vector((N-1) downto 0); 3250 data95: in std_logic_vector((N-1) downto 0); 3251 data96: in std_logic_vector((N-1) downto 0); 3252 data97: in std_logic_vector((N-1) downto 0); 3253 data98: in std_logic_vector((N-1) downto 0); 3254 data99: in std_logic_vector((N-1) downto 0); 3255 data100: in std_logic_vector((N-1) downto 0); 3256 data101: in std_logic_vector((N-1) downto 0); 3257 data102: in std_logic_vector((N-1) downto 0); 3258 data103: in std_logic_vector((N-1) downto 0); 3259 data104: in std_logic_vector((N-1) downto 0); 3260 data105: in std_logic_vector((N-1) downto 0); 3261 data106: in std_logic_vector((N-1) downto 0); 3262 data107: in std_logic_vector((N-1) downto 0); 3263 data108: in std_logic_vector((N-1) downto 0); 3264 data109: in std_logic_vector((N-1) downto 0); 3265 data110: in std_logic_vector((N-1) downto 0); 3266 data111: in std_logic_vector((N-1) downto 0); 3267 data112: in std_logic_vector((N-1) downto 0); 3268 data113: in std_logic_vector((N-1) downto 0); 3269 data114: in std_logic_vector((N-1) downto 0); 3270 data115: in std_logic_vector((N-1) downto 0); 3271 data116: in std_logic_vector((N-1) downto 0); 3272 data117: in std_logic_vector((N-1) downto 0); 3273 data118: in std_logic_vector((N-1) downto 0); 3274 data119: in std_logic_vector((N-1) downto 0); 3275 data120: in std_logic_vector((N-1) downto 0); 3276 data121: in std_logic_vector((N-1) downto 0); 3277 data122: in std_logic_vector((N-1) downto 0); 3278 data123: in std_logic_vector((N-1) downto 0); 3279 data124: in std_logic_vector((N-1) downto 0); 3280 data125: in std_logic_vector((N-1) downto 0); 3281 data126: in std_logic_vector((N-1) downto 0); 3282 data127: in std_logic_vector((N-1) downto 0); 3283 address: in std_logic_vector(6 downto 0); 3284 output: out std_logic_vector((N-1) downto 0) 3285); 3286end; 3287 3288architecture struct_encoder128xN of encoder128xN is 3289component encoder128x1 is 3290port( 3291 data0: in std_logic; 3292 data1: in std_logic; 3293 data2: in std_logic; 3294 data3: in std_logic; 3295 data4: in std_logic; 3296 data5: in std_logic; 3297 data6: in std_logic; 3298 data7: in std_logic; 3299 data8: in std_logic; 3300 data9: in std_logic; 3301 data10: in std_logic; 3302 data11: in std_logic; 3303 data12: in std_logic; 3304 data13: in std_logic; 3305 data14: in std_logic; 3306 data15: in std_logic; 3307 data16: in std_logic; 3308 data17: in std_logic; 3309 data18: in std_logic; 3310 data19: in std_logic; 3311 data20: in std_logic; 3312 data21: in std_logic; 3313 data22: in std_logic; 3314 data23: in std_logic; 3315 data24: in std_logic; 3316 data25: in std_logic; 3317 data26: in std_logic; 3318 data27: in std_logic; 3319 data28: in std_logic; 3320 data29: in std_logic; 3321 data30: in std_logic; 3322 data31: in std_logic; 3323 data32: in std_logic; 3324 data33: in std_logic; 3325 data34: in std_logic; 3326 data35: in std_logic; 3327 data36: in std_logic; 3328 data37: in std_logic; 3329 data38: in std_logic; 3330 data39: in std_logic; 3331 data40: in std_logic; 3332 data41: in std_logic; 3333 data42: in std_logic; 3334 data43: in std_logic; 3335 data44: in std_logic; 3336 data45: in std_logic; 3337 data46: in std_logic; 3338 data47: in std_logic; 3339 data48: in std_logic; 3340 data49: in std_logic; 3341 data50: in std_logic; 3342 data51: in std_logic; 3343 data52: in std_logic; 3344 data53: in std_logic; 3345 data54: in std_logic; 3346 data55: in std_logic; 3347 data56: in std_logic; 3348 data57: in std_logic; 3349 data58: in std_logic; 3350 data59: in std_logic; 3351 data60: in std_logic; 3352 data61: in std_logic; 3353 data62: in std_logic; 3354 data63: in std_logic; 3355 data64: in std_logic; 3356 data65: in std_logic; 3357 data66: in std_logic; 3358 data67: in std_logic; 3359 data68: in std_logic; 3360 data69: in std_logic; 3361 data70: in std_logic; 3362 data71: in std_logic; 3363 data72: in std_logic; 3364 data73: in std_logic; 3365 data74: in std_logic; 3366 data75: in std_logic; 3367 data76: in std_logic; 3368 data77: in std_logic; 3369 data78: in std_logic; 3370 data79: in std_logic; 3371 data80: in std_logic; 3372 data81: in std_logic; 3373 data82: in std_logic; 3374 data83: in std_logic; 3375 data84: in std_logic; 3376 data85: in std_logic; 3377 data86: in std_logic; 3378 data87: in std_logic; 3379 data88: in std_logic; 3380 data89: in std_logic; 3381 data90: in std_logic; 3382 data91: in std_logic; 3383 data92: in std_logic; 3384 data93: in std_logic; 3385 data94: in std_logic; 3386 data95: in std_logic; 3387 data96: in std_logic; 3388 data97: in std_logic; 3389 data98: in std_logic; 3390 data99: in std_logic; 3391 data100: in std_logic; 3392 data101: in std_logic; 3393 data102: in std_logic; 3394 data103: in std_logic; 3395 data104: in std_logic; 3396 data105: in std_logic; 3397 data106: in std_logic; 3398 data107: in std_logic; 3399 data108: in std_logic; 3400 data109: in std_logic; 3401 data110: in std_logic; 3402 data111: in std_logic; 3403 data112: in std_logic; 3404 data113: in std_logic; 3405 data114: in std_logic; 3406 data115: in std_logic; 3407 data116: in std_logic; 3408 data117: in std_logic; 3409 data118: in std_logic; 3410 data119: in std_logic; 3411 data120: in std_logic; 3412 data121: in std_logic; 3413 data122: in std_logic; 3414 data123: in std_logic; 3415 data124: in std_logic; 3416 data125: in std_logic; 3417 data126: in std_logic; 3418 data127: in std_logic; 3419 address: in std_logic_vector(6 downto 0); 3420 output: out std_logic 3421); 3422end component; 3423 3424begin 3425 u1: for i in (N-1) downto 0 generate 3426 u: encoder128x1 port map( 3427 data0 => data0(i), 3428 data1 => data1(i), 3429 data2 => data2(i), 3430 data3 => data3(i), 3431 data4 => data4(i), 3432 data5 => data5(i), 3433 data6 => data6(i), 3434 data7 => data7(i), 3435 data8 => data8(i), 3436 data9 => data9(i), 3437 data10 => data10(i), 3438 data11 => data11(i), 3439 data12 => data12(i), 3440 data13 => data13(i), 3441 data14 => data14(i), 3442 data15 => data15(i), 3443 data16 => data16(i), 3444 data17 => data17(i), 3445 data18 => data18(i), 3446 data19 => data19(i), 3447 data20 => data20(i), 3448 data21 => data21(i), 3449 data22 => data22(i), 3450 data23 => data23(i), 3451 data24 => data24(i), 3452 data25 => data25(i), 3453 data26 => data26(i), 3454 data27 => data27(i), 3455 data28 => data28(i), 3456 data29 => data29(i), 3457 data30 => data30(i), 3458 data31 => data31(i), 3459 data32 => data32(i), 3460 data33 => data33(i), 3461 data34 => data34(i), 3462 data35 => data35(i), 3463 data36 => data36(i), 3464 data37 => data37(i), 3465 data38 => data38(i), 3466 data39 => data39(i), 3467 data40 => data40(i), 3468 data41 => data41(i), 3469 data42 => data42(i), 3470 data43 => data43(i), 3471 data44 => data44(i), 3472 data45 => data45(i), 3473 data46 => data46(i), 3474 data47 => data47(i), 3475 data48 => data48(i), 3476 data49 => data49(i), 3477 data50 => data50(i), 3478 data51 => data51(i), 3479 data52 => data52(i), 3480 data53 => data53(i), 3481 data54 => data54(i), 3482 data55 => data55(i), 3483 data56 => data56(i), 3484 data57 => data57(i), 3485 data58 => data58(i), 3486 data59 => data59(i), 3487 data60 => data60(i), 3488 data61 => data61(i), 3489 data62 => data62(i), 3490 data63 => data63(i), 3491 data64 => data64(i), 3492 data65 => data65(i), 3493 data66 => data66(i), 3494 data67 => data67(i), 3495 data68 => data68(i), 3496 data69 => data69(i), 3497 data70 => data70(i), 3498 data71 => data71(i), 3499 data72 => data72(i), 3500 data73 => data73(i), 3501 data74 => data74(i), 3502 data75 => data75(i), 3503 data76 => data76(i), 3504 data77 => data77(i), 3505 data78 => data78(i), 3506 data79 => data79(i), 3507 data80 => data80(i), 3508 data81 => data81(i), 3509 data82 => data82(i), 3510 data83 => data83(i), 3511 data84 => data84(i), 3512 data85 => data85(i), 3513 data86 => data86(i), 3514 data87 => data87(i), 3515 data88 => data88(i), 3516 data89 => data89(i), 3517 data90 => data90(i), 3518 data91 => data91(i), 3519 data92 => data92(i), 3520 data93 => data93(i), 3521 data94 => data94(i), 3522 data95 => data95(i), 3523 data96 => data96(i), 3524 data97 => data97(i), 3525 data98 => data98(i), 3526 data99 => data99(i), 3527 data100 => data100(i), 3528 data101 => data101(i), 3529 data102 => data102(i), 3530 data103 => data103(i), 3531 data104 => data104(i), 3532 data105 => data105(i), 3533 data106 => data106(i), 3534 data107 => data107(i), 3535 data108 => data108(i), 3536 data109 => data109(i), 3537 data110 => data110(i), 3538 data111 => data111(i), 3539 data112 => data112(i), 3540 data113 => data113(i), 3541 data114 => data114(i), 3542 data115 => data115(i), 3543 data116 => data116(i), 3544 data117 => data117(i), 3545 data118 => data118(i), 3546 data119 => data119(i), 3547 data120 => data120(i), 3548 data121 => data121(i), 3549 data122 => data122(i), 3550 data123 => data123(i), 3551 data124 => data124(i), 3552 data125 => data125(i), 3553 data126 => data126(i), 3554 data127 => data127(i), 3555 address => address, 3556 output => output(i) 3557 ); 3558 end generate u1; 3559end; 3560 3561library ieee; 3562use ieee.std_logic_1164.all; 3563 3564entity decoder1x128 is 3565port( 3566 data: in std_logic; 3567 y0: out std_logic; 3568 y1: out std_logic; 3569 y2: out std_logic; 3570 y3: out std_logic; 3571 y4: out std_logic; 3572 y5: out std_logic; 3573 y6: out std_logic; 3574 y7: out std_logic; 3575 y8: out std_logic; 3576 y9: out std_logic; 3577 y10: out std_logic; 3578 y11: out std_logic; 3579 y12: out std_logic; 3580 y13: out std_logic; 3581 y14: out std_logic; 3582 y15: out std_logic; 3583 y16: out std_logic; 3584 y17: out std_logic; 3585 y18: out std_logic; 3586 y19: out std_logic; 3587 y20: out std_logic; 3588 y21: out std_logic; 3589 y22: out std_logic; 3590 y23: out std_logic; 3591 y24: out std_logic; 3592 y25: out std_logic; 3593 y26: out std_logic; 3594 y27: out std_logic; 3595 y28: out std_logic; 3596 y29: out std_logic; 3597 y30: out std_logic; 3598 y31: out std_logic; 3599 y32: out std_logic; 3600 y33: out std_logic; 3601 y34: out std_logic; 3602 y35: out std_logic; 3603 y36: out std_logic; 3604 y37: out std_logic; 3605 y38: out std_logic; 3606 y39: out std_logic; 3607 y40: out std_logic; 3608 y41: out std_logic; 3609 y42: out std_logic; 3610 y43: out std_logic; 3611 y44: out std_logic; 3612 y45: out std_logic; 3613 y46: out std_logic; 3614 y47: out std_logic; 3615 y48: out std_logic; 3616 y49: out std_logic; 3617 y50: out std_logic; 3618 y51: out std_logic; 3619 y52: out std_logic; 3620 y53: out std_logic; 3621 y54: out std_logic; 3622 y55: out std_logic; 3623 y56: out std_logic; 3624 y57: out std_logic; 3625 y58: out std_logic; 3626 y59: out std_logic; 3627 y60: out std_logic; 3628 y61: out std_logic; 3629 y62: out std_logic; 3630 y63: out std_logic; 3631 y64: out std_logic; 3632 y65: out std_logic; 3633 y66: out std_logic; 3634 y67: out std_logic; 3635 y68: out std_logic; 3636 y69: out std_logic; 3637 y70: out std_logic; 3638 y71: out std_logic; 3639 y72: out std_logic; 3640 y73: out std_logic; 3641 y74: out std_logic; 3642 y75: out std_logic; 3643 y76: out std_logic; 3644 y77: out std_logic; 3645 y78: out std_logic; 3646 y79: out std_logic; 3647 y80: out std_logic; 3648 y81: out std_logic; 3649 y82: out std_logic; 3650 y83: out std_logic; 3651 y84: out std_logic; 3652 y85: out std_logic; 3653 y86: out std_logic; 3654 y87: out std_logic; 3655 y88: out std_logic; 3656 y89: out std_logic; 3657 y90: out std_logic; 3658 y91: out std_logic; 3659 y92: out std_logic; 3660 y93: out std_logic; 3661 y94: out std_logic; 3662 y95: out std_logic; 3663 y96: out std_logic; 3664 y97: out std_logic; 3665 y98: out std_logic; 3666 y99: out std_logic; 3667 y100: out std_logic; 3668 y101: out std_logic; 3669 y102: out std_logic; 3670 y103: out std_logic; 3671 y104: out std_logic; 3672 y105: out std_logic; 3673 y106: out std_logic; 3674 y107: out std_logic; 3675 y108: out std_logic; 3676 y109: out std_logic; 3677 y110: out std_logic; 3678 y111: out std_logic; 3679 y112: out std_logic; 3680 y113: out std_logic; 3681 y114: out std_logic; 3682 y115: out std_logic; 3683 y116: out std_logic; 3684 y117: out std_logic; 3685 y118: out std_logic; 3686 y119: out std_logic; 3687 y120: out std_logic; 3688 y121: out std_logic; 3689 y122: out std_logic; 3690 y123: out std_logic; 3691 y124: out std_logic; 3692 y125: out std_logic; 3693 y126: out std_logic; 3694 y127: out std_logic; 3695 address: in std_logic_vector(6 downto 0) 3696); 3697end; 3698 3699architecture struct_decoder1x128 of decoder1x128 is 3700begin 3701 y0 <= data when address = "0000000" else '0'; 3702 y1 <= data when address = "0000001" else '0'; 3703 y2 <= data when address = "0000010" else '0'; 3704 y3 <= data when address = "0000011" else '0'; 3705 y4 <= data when address = "0000100" else '0'; 3706 y5 <= data when address = "0000101" else '0'; 3707 y6 <= data when address = "0000110" else '0'; 3708 y7 <= data when address = "0000111" else '0'; 3709 y8 <= data when address = "0001000" else '0'; 3710 y9 <= data when address = "0001001" else '0'; 3711 y10 <= data when address = "0001010" else '0'; 3712 y11 <= data when address = "0001011" else '0'; 3713 y12 <= data when address = "0001100" else '0'; 3714 y13 <= data when address = "0001101" else '0'; 3715 y14 <= data when address = "0001110" else '0'; 3716 y15 <= data when address = "0001111" else '0'; 3717 y16 <= data when address = "0010000" else '0'; 3718 y17 <= data when address = "0010001" else '0'; 3719 y18 <= data when address = "0010010" else '0'; 3720 y19 <= data when address = "0010011" else '0'; 3721 y20 <= data when address = "0010100" else '0'; 3722 y21 <= data when address = "0010101" else '0'; 3723 y22 <= data when address = "0010110" else '0'; 3724 y23 <= data when address = "0010111" else '0'; 3725 y24 <= data when address = "0011000" else '0'; 3726 y25 <= data when address = "0011001" else '0'; 3727 y26 <= data when address = "0011010" else '0'; 3728 y27 <= data when address = "0011011" else '0'; 3729 y28 <= data when address = "0011100" else '0'; 3730 y29 <= data when address = "0011101" else '0'; 3731 y30 <= data when address = "0011110" else '0'; 3732 y31 <= data when address = "0011111" else '0'; 3733 y32 <= data when address = "0100000" else '0'; 3734 y33 <= data when address = "0100001" else '0'; 3735 y34 <= data when address = "0100010" else '0'; 3736 y35 <= data when address = "0100011" else '0'; 3737 y36 <= data when address = "0100100" else '0'; 3738 y37 <= data when address = "0100101" else '0'; 3739 y38 <= data when address = "0100110" else '0'; 3740 y39 <= data when address = "0100111" else '0'; 3741 y40 <= data when address = "0101000" else '0'; 3742 y41 <= data when address = "0101001" else '0'; 3743 y42 <= data when address = "0101010" else '0'; 3744 y43 <= data when address = "0101011" else '0'; 3745 y44 <= data when address = "0101100" else '0'; 3746 y45 <= data when address = "0101101" else '0'; 3747 y46 <= data when address = "0101110" else '0'; 3748 y47 <= data when address = "0101111" else '0'; 3749 y48 <= data when address = "0110000" else '0'; 3750 y49 <= data when address = "0110001" else '0'; 3751 y50 <= data when address = "0110010" else '0'; 3752 y51 <= data when address = "0110011" else '0'; 3753 y52 <= data when address = "0110100" else '0'; 3754 y53 <= data when address = "0110101" else '0'; 3755 y54 <= data when address = "0110110" else '0'; 3756 y55 <= data when address = "0110111" else '0'; 3757 y56 <= data when address = "0111000" else '0'; 3758 y57 <= data when address = "0111001" else '0'; 3759 y58 <= data when address = "0111010" else '0'; 3760 y59 <= data when address = "0111011" else '0'; 3761 y60 <= data when address = "0111100" else '0'; 3762 y61 <= data when address = "0111101" else '0'; 3763 y62 <= data when address = "0111110" else '0'; 3764 y63 <= data when address = "0111111" else '0'; 3765 y64 <= data when address = "1000000" else '0'; 3766 y65 <= data when address = "1000001" else '0'; 3767 y66 <= data when address = "1000010" else '0'; 3768 y67 <= data when address = "1000011" else '0'; 3769 y68 <= data when address = "1000100" else '0'; 3770 y69 <= data when address = "1000101" else '0'; 3771 y70 <= data when address = "1000110" else '0'; 3772 y71 <= data when address = "1000111" else '0'; 3773 y72 <= data when address = "1001000" else '0'; 3774 y73 <= data when address = "1001001" else '0'; 3775 y74 <= data when address = "1001010" else '0'; 3776 y75 <= data when address = "1001011" else '0'; 3777 y76 <= data when address = "1001100" else '0'; 3778 y77 <= data when address = "1001101" else '0'; 3779 y78 <= data when address = "1001110" else '0'; 3780 y79 <= data when address = "1001111" else '0'; 3781 y80 <= data when address = "1010000" else '0'; 3782 y81 <= data when address = "1010001" else '0'; 3783 y82 <= data when address = "1010010" else '0'; 3784 y83 <= data when address = "1010011" else '0'; 3785 y84 <= data when address = "1010100" else '0'; 3786 y85 <= data when address = "1010101" else '0'; 3787 y86 <= data when address = "1010110" else '0'; 3788 y87 <= data when address = "1010111" else '0'; 3789 y88 <= data when address = "1011000" else '0'; 3790 y89 <= data when address = "1011001" else '0'; 3791 y90 <= data when address = "1011010" else '0'; 3792 y91 <= data when address = "1011011" else '0'; 3793 y92 <= data when address = "1011100" else '0'; 3794 y93 <= data when address = "1011101" else '0'; 3795 y94 <= data when address = "1011110" else '0'; 3796 y95 <= data when address = "1011111" else '0'; 3797 y96 <= data when address = "1100000" else '0'; 3798 y97 <= data when address = "1100001" else '0'; 3799 y98 <= data when address = "1100010" else '0'; 3800 y99 <= data when address = "1100011" else '0'; 3801 y100 <= data when address = "1100100" else '0'; 3802 y101 <= data when address = "1100101" else '0'; 3803 y102 <= data when address = "1100110" else '0'; 3804 y103 <= data when address = "1100111" else '0'; 3805 y104 <= data when address = "1101000" else '0'; 3806 y105 <= data when address = "1101001" else '0'; 3807 y106 <= data when address = "1101010" else '0'; 3808 y107 <= data when address = "1101011" else '0'; 3809 y108 <= data when address = "1101100" else '0'; 3810 y109 <= data when address = "1101101" else '0'; 3811 y110 <= data when address = "1101110" else '0'; 3812 y111 <= data when address = "1101111" else '0'; 3813 y112 <= data when address = "1110000" else '0'; 3814 y113 <= data when address = "1110001" else '0'; 3815 y114 <= data when address = "1110010" else '0'; 3816 y115 <= data when address = "1110011" else '0'; 3817 y116 <= data when address = "1110100" else '0'; 3818 y117 <= data when address = "1110101" else '0'; 3819 y118 <= data when address = "1110110" else '0'; 3820 y119 <= data when address = "1110111" else '0'; 3821 y120 <= data when address = "1111000" else '0'; 3822 y121 <= data when address = "1111001" else '0'; 3823 y122 <= data when address = "1111010" else '0'; 3824 y123 <= data when address = "1111011" else '0'; 3825 y124 <= data when address = "1111100" else '0'; 3826 y125 <= data when address = "1111101" else '0'; 3827 y126 <= data when address = "1111110" else '0'; 3828 y127 <= data when address = "1111111" else '0'; 3829end; 3830 3831library ieee; 3832use ieee.std_logic_1164.all; 3833 3834entity decoderNx128 is 3835generic( 3836 N: positive 3837); 3838port( 3839 data: in std_logic_vector((N-1) downto 0); 3840 y0: out std_logic_vector((N-1) downto 0); 3841 y1: out std_logic_vector((N-1) downto 0); 3842 y2: out std_logic_vector((N-1) downto 0); 3843 y3: out std_logic_vector((N-1) downto 0); 3844 y4: out std_logic_vector((N-1) downto 0); 3845 y5: out std_logic_vector((N-1) downto 0); 3846 y6: out std_logic_vector((N-1) downto 0); 3847 y7: out std_logic_vector((N-1) downto 0); 3848 y8: out std_logic_vector((N-1) downto 0); 3849 y9: out std_logic_vector((N-1) downto 0); 3850 y10: out std_logic_vector((N-1) downto 0); 3851 y11: out std_logic_vector((N-1) downto 0); 3852 y12: out std_logic_vector((N-1) downto 0); 3853 y13: out std_logic_vector((N-1) downto 0); 3854 y14: out std_logic_vector((N-1) downto 0); 3855 y15: out std_logic_vector((N-1) downto 0); 3856 y16: out std_logic_vector((N-1) downto 0); 3857 y17: out std_logic_vector((N-1) downto 0); 3858 y18: out std_logic_vector((N-1) downto 0); 3859 y19: out std_logic_vector((N-1) downto 0); 3860 y20: out std_logic_vector((N-1) downto 0); 3861 y21: out std_logic_vector((N-1) downto 0); 3862 y22: out std_logic_vector((N-1) downto 0); 3863 y23: out std_logic_vector((N-1) downto 0); 3864 y24: out std_logic_vector((N-1) downto 0); 3865 y25: out std_logic_vector((N-1) downto 0); 3866 y26: out std_logic_vector((N-1) downto 0); 3867 y27: out std_logic_vector((N-1) downto 0); 3868 y28: out std_logic_vector((N-1) downto 0); 3869 y29: out std_logic_vector((N-1) downto 0); 3870 y30: out std_logic_vector((N-1) downto 0); 3871 y31: out std_logic_vector((N-1) downto 0); 3872 y32: out std_logic_vector((N-1) downto 0); 3873 y33: out std_logic_vector((N-1) downto 0); 3874 y34: out std_logic_vector((N-1) downto 0); 3875 y35: out std_logic_vector((N-1) downto 0); 3876 y36: out std_logic_vector((N-1) downto 0); 3877 y37: out std_logic_vector((N-1) downto 0); 3878 y38: out std_logic_vector((N-1) downto 0); 3879 y39: out std_logic_vector((N-1) downto 0); 3880 y40: out std_logic_vector((N-1) downto 0); 3881 y41: out std_logic_vector((N-1) downto 0); 3882 y42: out std_logic_vector((N-1) downto 0); 3883 y43: out std_logic_vector((N-1) downto 0); 3884 y44: out std_logic_vector((N-1) downto 0); 3885 y45: out std_logic_vector((N-1) downto 0); 3886 y46: out std_logic_vector((N-1) downto 0); 3887 y47: out std_logic_vector((N-1) downto 0); 3888 y48: out std_logic_vector((N-1) downto 0); 3889 y49: out std_logic_vector((N-1) downto 0); 3890 y50: out std_logic_vector((N-1) downto 0); 3891 y51: out std_logic_vector((N-1) downto 0); 3892 y52: out std_logic_vector((N-1) downto 0); 3893 y53: out std_logic_vector((N-1) downto 0); 3894 y54: out std_logic_vector((N-1) downto 0); 3895 y55: out std_logic_vector((N-1) downto 0); 3896 y56: out std_logic_vector((N-1) downto 0); 3897 y57: out std_logic_vector((N-1) downto 0); 3898 y58: out std_logic_vector((N-1) downto 0); 3899 y59: out std_logic_vector((N-1) downto 0); 3900 y60: out std_logic_vector((N-1) downto 0); 3901 y61: out std_logic_vector((N-1) downto 0); 3902 y62: out std_logic_vector((N-1) downto 0); 3903 y63: out std_logic_vector((N-1) downto 0); 3904 y64: out std_logic_vector((N-1) downto 0); 3905 y65: out std_logic_vector((N-1) downto 0); 3906 y66: out std_logic_vector((N-1) downto 0); 3907 y67: out std_logic_vector((N-1) downto 0); 3908 y68: out std_logic_vector((N-1) downto 0); 3909 y69: out std_logic_vector((N-1) downto 0); 3910 y70: out std_logic_vector((N-1) downto 0); 3911 y71: out std_logic_vector((N-1) downto 0); 3912 y72: out std_logic_vector((N-1) downto 0); 3913 y73: out std_logic_vector((N-1) downto 0); 3914 y74: out std_logic_vector((N-1) downto 0); 3915 y75: out std_logic_vector((N-1) downto 0); 3916 y76: out std_logic_vector((N-1) downto 0); 3917 y77: out std_logic_vector((N-1) downto 0); 3918 y78: out std_logic_vector((N-1) downto 0); 3919 y79: out std_logic_vector((N-1) downto 0); 3920 y80: out std_logic_vector((N-1) downto 0); 3921 y81: out std_logic_vector((N-1) downto 0); 3922 y82: out std_logic_vector((N-1) downto 0); 3923 y83: out std_logic_vector((N-1) downto 0); 3924 y84: out std_logic_vector((N-1) downto 0); 3925 y85: out std_logic_vector((N-1) downto 0); 3926 y86: out std_logic_vector((N-1) downto 0); 3927 y87: out std_logic_vector((N-1) downto 0); 3928 y88: out std_logic_vector((N-1) downto 0); 3929 y89: out std_logic_vector((N-1) downto 0); 3930 y90: out std_logic_vector((N-1) downto 0); 3931 y91: out std_logic_vector((N-1) downto 0); 3932 y92: out std_logic_vector((N-1) downto 0); 3933 y93: out std_logic_vector((N-1) downto 0); 3934 y94: out std_logic_vector((N-1) downto 0); 3935 y95: out std_logic_vector((N-1) downto 0); 3936 y96: out std_logic_vector((N-1) downto 0); 3937 y97: out std_logic_vector((N-1) downto 0); 3938 y98: out std_logic_vector((N-1) downto 0); 3939 y99: out std_logic_vector((N-1) downto 0); 3940 y100: out std_logic_vector((N-1) downto 0); 3941 y101: out std_logic_vector((N-1) downto 0); 3942 y102: out std_logic_vector((N-1) downto 0); 3943 y103: out std_logic_vector((N-1) downto 0); 3944 y104: out std_logic_vector((N-1) downto 0); 3945 y105: out std_logic_vector((N-1) downto 0); 3946 y106: out std_logic_vector((N-1) downto 0); 3947 y107: out std_logic_vector((N-1) downto 0); 3948 y108: out std_logic_vector((N-1) downto 0); 3949 y109: out std_logic_vector((N-1) downto 0); 3950 y110: out std_logic_vector((N-1) downto 0); 3951 y111: out std_logic_vector((N-1) downto 0); 3952 y112: out std_logic_vector((N-1) downto 0); 3953 y113: out std_logic_vector((N-1) downto 0); 3954 y114: out std_logic_vector((N-1) downto 0); 3955 y115: out std_logic_vector((N-1) downto 0); 3956 y116: out std_logic_vector((N-1) downto 0); 3957 y117: out std_logic_vector((N-1) downto 0); 3958 y118: out std_logic_vector((N-1) downto 0); 3959 y119: out std_logic_vector((N-1) downto 0); 3960 y120: out std_logic_vector((N-1) downto 0); 3961 y121: out std_logic_vector((N-1) downto 0); 3962 y122: out std_logic_vector((N-1) downto 0); 3963 y123: out std_logic_vector((N-1) downto 0); 3964 y124: out std_logic_vector((N-1) downto 0); 3965 y125: out std_logic_vector((N-1) downto 0); 3966 y126: out std_logic_vector((N-1) downto 0); 3967 y127: out std_logic_vector((N-1) downto 0); 3968 address: in std_logic_vector(6 downto 0) 3969); 3970end; 3971 3972architecture struct_decoderNx128 of decoderNx128 is 3973component decoder1x128 is 3974port( 3975 data: in std_logic; 3976 y0: out std_logic; 3977 y1: out std_logic; 3978 y2: out std_logic; 3979 y3: out std_logic; 3980 y4: out std_logic; 3981 y5: out std_logic; 3982 y6: out std_logic; 3983 y7: out std_logic; 3984 y8: out std_logic; 3985 y9: out std_logic; 3986 y10: out std_logic; 3987 y11: out std_logic; 3988 y12: out std_logic; 3989 y13: out std_logic; 3990 y14: out std_logic; 3991 y15: out std_logic; 3992 y16: out std_logic; 3993 y17: out std_logic; 3994 y18: out std_logic; 3995 y19: out std_logic; 3996 y20: out std_logic; 3997 y21: out std_logic; 3998 y22: out std_logic; 3999 y23: out std_logic; 4000 y24: out std_logic; 4001 y25: out std_logic; 4002 y26: out std_logic; 4003 y27: out std_logic; 4004 y28: out std_logic; 4005 y29: out std_logic; 4006 y30: out std_logic; 4007 y31: out std_logic; 4008 y32: out std_logic; 4009 y33: out std_logic; 4010 y34: out std_logic; 4011 y35: out std_logic; 4012 y36: out std_logic; 4013 y37: out std_logic; 4014 y38: out std_logic; 4015 y39: out std_logic; 4016 y40: out std_logic; 4017 y41: out std_logic; 4018 y42: out std_logic; 4019 y43: out std_logic; 4020 y44: out std_logic; 4021 y45: out std_logic; 4022 y46: out std_logic; 4023 y47: out std_logic; 4024 y48: out std_logic; 4025 y49: out std_logic; 4026 y50: out std_logic; 4027 y51: out std_logic; 4028 y52: out std_logic; 4029 y53: out std_logic; 4030 y54: out std_logic; 4031 y55: out std_logic; 4032 y56: out std_logic; 4033 y57: out std_logic; 4034 y58: out std_logic; 4035 y59: out std_logic; 4036 y60: out std_logic; 4037 y61: out std_logic; 4038 y62: out std_logic; 4039 y63: out std_logic; 4040 y64: out std_logic; 4041 y65: out std_logic; 4042 y66: out std_logic; 4043 y67: out std_logic; 4044 y68: out std_logic; 4045 y69: out std_logic; 4046 y70: out std_logic; 4047 y71: out std_logic; 4048 y72: out std_logic; 4049 y73: out std_logic; 4050 y74: out std_logic; 4051 y75: out std_logic; 4052 y76: out std_logic; 4053 y77: out std_logic; 4054 y78: out std_logic; 4055 y79: out std_logic; 4056 y80: out std_logic; 4057 y81: out std_logic; 4058 y82: out std_logic; 4059 y83: out std_logic; 4060 y84: out std_logic; 4061 y85: out std_logic; 4062 y86: out std_logic; 4063 y87: out std_logic; 4064 y88: out std_logic; 4065 y89: out std_logic; 4066 y90: out std_logic; 4067 y91: out std_logic; 4068 y92: out std_logic; 4069 y93: out std_logic; 4070 y94: out std_logic; 4071 y95: out std_logic; 4072 y96: out std_logic; 4073 y97: out std_logic; 4074 y98: out std_logic; 4075 y99: out std_logic; 4076 y100: out std_logic; 4077 y101: out std_logic; 4078 y102: out std_logic; 4079 y103: out std_logic; 4080 y104: out std_logic; 4081 y105: out std_logic; 4082 y106: out std_logic; 4083 y107: out std_logic; 4084 y108: out std_logic; 4085 y109: out std_logic; 4086 y110: out std_logic; 4087 y111: out std_logic; 4088 y112: out std_logic; 4089 y113: out std_logic; 4090 y114: out std_logic; 4091 y115: out std_logic; 4092 y116: out std_logic; 4093 y117: out std_logic; 4094 y118: out std_logic; 4095 y119: out std_logic; 4096 y120: out std_logic; 4097 y121: out std_logic; 4098 y122: out std_logic; 4099 y123: out std_logic; 4100 y124: out std_logic; 4101 y125: out std_logic; 4102 y126: out std_logic; 4103 y127: out std_logic; 4104 address: in std_logic_vector(6 downto 0) 4105); 4106 4107end component; 4108 4109begin 4110 u1: for i in (N-1) downto 0 generate 4111 u: decoder1x128 port map( 4112 data => data(i), 4113 y0 => y0(i), 4114 y1 => y1(i), 4115 y2 => y2(i), 4116 y3 => y3(i), 4117 y4 => y4(i), 4118 y5 => y5(i), 4119 y6 => y6(i), 4120 y7 => y7(i), 4121 y8 => y8(i), 4122 y9 => y9(i), 4123 y10 => y10(i), 4124 y11 => y11(i), 4125 y12 => y12(i), 4126 y13 => y13(i), 4127 y14 => y14(i), 4128 y15 => y15(i), 4129 y16 => y16(i), 4130 y17 => y17(i), 4131 y18 => y18(i), 4132 y19 => y19(i), 4133 y20 => y20(i), 4134 y21 => y21(i), 4135 y22 => y22(i), 4136 y23 => y23(i), 4137 y24 => y24(i), 4138 y25 => y25(i), 4139 y26 => y26(i), 4140 y27 => y27(i), 4141 y28 => y28(i), 4142 y29 => y29(i), 4143 y30 => y30(i), 4144 y31 => y31(i), 4145 y32 => y32(i), 4146 y33 => y33(i), 4147 y34 => y34(i), 4148 y35 => y35(i), 4149 y36 => y36(i), 4150 y37 => y37(i), 4151 y38 => y38(i), 4152 y39 => y39(i), 4153 y40 => y40(i), 4154 y41 => y41(i), 4155 y42 => y42(i), 4156 y43 => y43(i), 4157 y44 => y44(i), 4158 y45 => y45(i), 4159 y46 => y46(i), 4160 y47 => y47(i), 4161 y48 => y48(i), 4162 y49 => y49(i), 4163 y50 => y50(i), 4164 y51 => y51(i), 4165 y52 => y52(i), 4166 y53 => y53(i), 4167 y54 => y54(i), 4168 y55 => y55(i), 4169 y56 => y56(i), 4170 y57 => y57(i), 4171 y58 => y58(i), 4172 y59 => y59(i), 4173 y60 => y60(i), 4174 y61 => y61(i), 4175 y62 => y62(i), 4176 y63 => y63(i), 4177 y64 => y64(i), 4178 y65 => y65(i), 4179 y66 => y66(i), 4180 y67 => y67(i), 4181 y68 => y68(i), 4182 y69 => y69(i), 4183 y70 => y70(i), 4184 y71 => y71(i), 4185 y72 => y72(i), 4186 y73 => y73(i), 4187 y74 => y74(i), 4188 y75 => y75(i), 4189 y76 => y76(i), 4190 y77 => y77(i), 4191 y78 => y78(i), 4192 y79 => y79(i), 4193 y80 => y80(i), 4194 y81 => y81(i), 4195 y82 => y82(i), 4196 y83 => y83(i), 4197 y84 => y84(i), 4198 y85 => y85(i), 4199 y86 => y86(i), 4200 y87 => y87(i), 4201 y88 => y88(i), 4202 y89 => y89(i), 4203 y90 => y90(i), 4204 y91 => y91(i), 4205 y92 => y92(i), 4206 y93 => y93(i), 4207 y94 => y94(i), 4208 y95 => y95(i), 4209 y96 => y96(i), 4210 y97 => y97(i), 4211 y98 => y98(i), 4212 y99 => y99(i), 4213 y100 => y100(i), 4214 y101 => y101(i), 4215 y102 => y102(i), 4216 y103 => y103(i), 4217 y104 => y104(i), 4218 y105 => y105(i), 4219 y106 => y106(i), 4220 y107 => y107(i), 4221 y108 => y108(i), 4222 y109 => y109(i), 4223 y110 => y110(i), 4224 y111 => y111(i), 4225 y112 => y112(i), 4226 y113 => y113(i), 4227 y114 => y114(i), 4228 y115 => y115(i), 4229 y116 => y116(i), 4230 y117 => y117(i), 4231 y118 => y118(i), 4232 y119 => y119(i), 4233 y120 => y120(i), 4234 y121 => y121(i), 4235 y122 => y122(i), 4236 y123 => y123(i), 4237 y124 => y124(i), 4238 y125 => y125(i), 4239 y126 => y126(i), 4240 y127 => y127(i), 4241 address => address 4242 ); 4243 end generate u1; 4244end; 4245 4246library ieee; 4247use ieee.std_logic_1164.all; 4248 4249entity encoder256x1 is 4250port( 4251 data0: in std_logic; 4252 data1: in std_logic; 4253 data2: in std_logic; 4254 data3: in std_logic; 4255 data4: in std_logic; 4256 data5: in std_logic; 4257 data6: in std_logic; 4258 data7: in std_logic; 4259 data8: in std_logic; 4260 data9: in std_logic; 4261 data10: in std_logic; 4262 data11: in std_logic; 4263 data12: in std_logic; 4264 data13: in std_logic; 4265 data14: in std_logic; 4266 data15: in std_logic; 4267 data16: in std_logic; 4268 data17: in std_logic; 4269 data18: in std_logic; 4270 data19: in std_logic; 4271 data20: in std_logic; 4272 data21: in std_logic; 4273 data22: in std_logic; 4274 data23: in std_logic; 4275 data24: in std_logic; 4276 data25: in std_logic; 4277 data26: in std_logic; 4278 data27: in std_logic; 4279 data28: in std_logic; 4280 data29: in std_logic; 4281 data30: in std_logic; 4282 data31: in std_logic; 4283 data32: in std_logic; 4284 data33: in std_logic; 4285 data34: in std_logic; 4286 data35: in std_logic; 4287 data36: in std_logic; 4288 data37: in std_logic; 4289 data38: in std_logic; 4290 data39: in std_logic; 4291 data40: in std_logic; 4292 data41: in std_logic; 4293 data42: in std_logic; 4294 data43: in std_logic; 4295 data44: in std_logic; 4296 data45: in std_logic; 4297 data46: in std_logic; 4298 data47: in std_logic; 4299 data48: in std_logic; 4300 data49: in std_logic; 4301 data50: in std_logic; 4302 data51: in std_logic; 4303 data52: in std_logic; 4304 data53: in std_logic; 4305 data54: in std_logic; 4306 data55: in std_logic; 4307 data56: in std_logic; 4308 data57: in std_logic; 4309 data58: in std_logic; 4310 data59: in std_logic; 4311 data60: in std_logic; 4312 data61: in std_logic; 4313 data62: in std_logic; 4314 data63: in std_logic; 4315 data64: in std_logic; 4316 data65: in std_logic; 4317 data66: in std_logic; 4318 data67: in std_logic; 4319 data68: in std_logic; 4320 data69: in std_logic; 4321 data70: in std_logic; 4322 data71: in std_logic; 4323 data72: in std_logic; 4324 data73: in std_logic; 4325 data74: in std_logic; 4326 data75: in std_logic; 4327 data76: in std_logic; 4328 data77: in std_logic; 4329 data78: in std_logic; 4330 data79: in std_logic; 4331 data80: in std_logic; 4332 data81: in std_logic; 4333 data82: in std_logic; 4334 data83: in std_logic; 4335 data84: in std_logic; 4336 data85: in std_logic; 4337 data86: in std_logic; 4338 data87: in std_logic; 4339 data88: in std_logic; 4340 data89: in std_logic; 4341 data90: in std_logic; 4342 data91: in std_logic; 4343 data92: in std_logic; 4344 data93: in std_logic; 4345 data94: in std_logic; 4346 data95: in std_logic; 4347 data96: in std_logic; 4348 data97: in std_logic; 4349 data98: in std_logic; 4350 data99: in std_logic; 4351 data100: in std_logic; 4352 data101: in std_logic; 4353 data102: in std_logic; 4354 data103: in std_logic; 4355 data104: in std_logic; 4356 data105: in std_logic; 4357 data106: in std_logic; 4358 data107: in std_logic; 4359 data108: in std_logic; 4360 data109: in std_logic; 4361 data110: in std_logic; 4362 data111: in std_logic; 4363 data112: in std_logic; 4364 data113: in std_logic; 4365 data114: in std_logic; 4366 data115: in std_logic; 4367 data116: in std_logic; 4368 data117: in std_logic; 4369 data118: in std_logic; 4370 data119: in std_logic; 4371 data120: in std_logic; 4372 data121: in std_logic; 4373 data122: in std_logic; 4374 data123: in std_logic; 4375 data124: in std_logic; 4376 data125: in std_logic; 4377 data126: in std_logic; 4378 data127: in std_logic; 4379 data128: in std_logic; 4380 data129: in std_logic; 4381 data130: in std_logic; 4382 data131: in std_logic; 4383 data132: in std_logic; 4384 data133: in std_logic; 4385 data134: in std_logic; 4386 data135: in std_logic; 4387 data136: in std_logic; 4388 data137: in std_logic; 4389 data138: in std_logic; 4390 data139: in std_logic; 4391 data140: in std_logic; 4392 data141: in std_logic; 4393 data142: in std_logic; 4394 data143: in std_logic; 4395 data144: in std_logic; 4396 data145: in std_logic; 4397 data146: in std_logic; 4398 data147: in std_logic; 4399 data148: in std_logic; 4400 data149: in std_logic; 4401 data150: in std_logic; 4402 data151: in std_logic; 4403 data152: in std_logic; 4404 data153: in std_logic; 4405 data154: in std_logic; 4406 data155: in std_logic; 4407 data156: in std_logic; 4408 data157: in std_logic; 4409 data158: in std_logic; 4410 data159: in std_logic; 4411 data160: in std_logic; 4412 data161: in std_logic; 4413 data162: in std_logic; 4414 data163: in std_logic; 4415 data164: in std_logic; 4416 data165: in std_logic; 4417 data166: in std_logic; 4418 data167: in std_logic; 4419 data168: in std_logic; 4420 data169: in std_logic; 4421 data170: in std_logic; 4422 data171: in std_logic; 4423 data172: in std_logic; 4424 data173: in std_logic; 4425 data174: in std_logic; 4426 data175: in std_logic; 4427 data176: in std_logic; 4428 data177: in std_logic; 4429 data178: in std_logic; 4430 data179: in std_logic; 4431 data180: in std_logic; 4432 data181: in std_logic; 4433 data182: in std_logic; 4434 data183: in std_logic; 4435 data184: in std_logic; 4436 data185: in std_logic; 4437 data186: in std_logic; 4438 data187: in std_logic; 4439 data188: in std_logic; 4440 data189: in std_logic; 4441 data190: in std_logic; 4442 data191: in std_logic; 4443 data192: in std_logic; 4444 data193: in std_logic; 4445 data194: in std_logic; 4446 data195: in std_logic; 4447 data196: in std_logic; 4448 data197: in std_logic; 4449 data198: in std_logic; 4450 data199: in std_logic; 4451 data200: in std_logic; 4452 data201: in std_logic; 4453 data202: in std_logic; 4454 data203: in std_logic; 4455 data204: in std_logic; 4456 data205: in std_logic; 4457 data206: in std_logic; 4458 data207: in std_logic; 4459 data208: in std_logic; 4460 data209: in std_logic; 4461 data210: in std_logic; 4462 data211: in std_logic; 4463 data212: in std_logic; 4464 data213: in std_logic; 4465 data214: in std_logic; 4466 data215: in std_logic; 4467 data216: in std_logic; 4468 data217: in std_logic; 4469 data218: in std_logic; 4470 data219: in std_logic; 4471 data220: in std_logic; 4472 data221: in std_logic; 4473 data222: in std_logic; 4474 data223: in std_logic; 4475 data224: in std_logic; 4476 data225: in std_logic; 4477 data226: in std_logic; 4478 data227: in std_logic; 4479 data228: in std_logic; 4480 data229: in std_logic; 4481 data230: in std_logic; 4482 data231: in std_logic; 4483 data232: in std_logic; 4484 data233: in std_logic; 4485 data234: in std_logic; 4486 data235: in std_logic; 4487 data236: in std_logic; 4488 data237: in std_logic; 4489 data238: in std_logic; 4490 data239: in std_logic; 4491 data240: in std_logic; 4492 data241: in std_logic; 4493 data242: in std_logic; 4494 data243: in std_logic; 4495 data244: in std_logic; 4496 data245: in std_logic; 4497 data246: in std_logic; 4498 data247: in std_logic; 4499 data248: in std_logic; 4500 data249: in std_logic; 4501 data250: in std_logic; 4502 data251: in std_logic; 4503 data252: in std_logic; 4504 data253: in std_logic; 4505 data254: in std_logic; 4506 data255: in std_logic; 4507 address: in std_logic_vector(7 downto 0); 4508 output: out std_logic 4509); 4510end; 4511 4512architecture struct_encoder256x1 of encoder256x1 is 4513begin 4514 with address select 4515 output <= 4516 data0 when "00000000", 4517 data1 when "00000001", 4518 data2 when "00000010", 4519 data3 when "00000011", 4520 data4 when "00000100", 4521 data5 when "00000101", 4522 data6 when "00000110", 4523 data7 when "00000111", 4524 data8 when "00001000", 4525 data9 when "00001001", 4526 data10 when "00001010", 4527 data11 when "00001011", 4528 data12 when "00001100", 4529 data13 when "00001101", 4530 data14 when "00001110", 4531 data15 when "00001111", 4532 data16 when "00010000", 4533 data17 when "00010001", 4534 data18 when "00010010", 4535 data19 when "00010011", 4536 data20 when "00010100", 4537 data21 when "00010101", 4538 data22 when "00010110", 4539 data23 when "00010111", 4540 data24 when "00011000", 4541 data25 when "00011001", 4542 data26 when "00011010", 4543 data27 when "00011011", 4544 data28 when "00011100", 4545 data29 when "00011101", 4546 data30 when "00011110", 4547 data31 when "00011111", 4548 data32 when "00100000", 4549 data33 when "00100001", 4550 data34 when "00100010", 4551 data35 when "00100011", 4552 data36 when "00100100", 4553 data37 when "00100101", 4554 data38 when "00100110", 4555 data39 when "00100111", 4556 data40 when "00101000", 4557 data41 when "00101001", 4558 data42 when "00101010", 4559 data43 when "00101011", 4560 data44 when "00101100", 4561 data45 when "00101101", 4562 data46 when "00101110", 4563 data47 when "00101111", 4564 data48 when "00110000", 4565 data49 when "00110001", 4566 data50 when "00110010", 4567 data51 when "00110011", 4568 data52 when "00110100", 4569 data53 when "00110101", 4570 data54 when "00110110", 4571 data55 when "00110111", 4572 data56 when "00111000", 4573 data57 when "00111001", 4574 data58 when "00111010", 4575 data59 when "00111011", 4576 data60 when "00111100", 4577 data61 when "00111101", 4578 data62 when "00111110", 4579 data63 when "00111111", 4580 data64 when "01000000", 4581 data65 when "01000001", 4582 data66 when "01000010", 4583 data67 when "01000011", 4584 data68 when "01000100", 4585 data69 when "01000101", 4586 data70 when "01000110", 4587 data71 when "01000111", 4588 data72 when "01001000", 4589 data73 when "01001001", 4590 data74 when "01001010", 4591 data75 when "01001011", 4592 data76 when "01001100", 4593 data77 when "01001101", 4594 data78 when "01001110", 4595 data79 when "01001111", 4596 data80 when "01010000", 4597 data81 when "01010001", 4598 data82 when "01010010", 4599 data83 when "01010011", 4600 data84 when "01010100", 4601 data85 when "01010101", 4602 data86 when "01010110", 4603 data87 when "01010111", 4604 data88 when "01011000", 4605 data89 when "01011001", 4606 data90 when "01011010", 4607 data91 when "01011011", 4608 data92 when "01011100", 4609 data93 when "01011101", 4610 data94 when "01011110", 4611 data95 when "01011111", 4612 data96 when "01100000", 4613 data97 when "01100001", 4614 data98 when "01100010", 4615 data99 when "01100011", 4616 data100 when "01100100", 4617 data101 when "01100101", 4618 data102 when "01100110", 4619 data103 when "01100111", 4620 data104 when "01101000", 4621 data105 when "01101001", 4622 data106 when "01101010", 4623 data107 when "01101011", 4624 data108 when "01101100", 4625 data109 when "01101101", 4626 data110 when "01101110", 4627 data111 when "01101111", 4628 data112 when "01110000", 4629 data113 when "01110001", 4630 data114 when "01110010", 4631 data115 when "01110011", 4632 data116 when "01110100", 4633 data117 when "01110101", 4634 data118 when "01110110", 4635 data119 when "01110111", 4636 data120 when "01111000", 4637 data121 when "01111001", 4638 data122 when "01111010", 4639 data123 when "01111011", 4640 data124 when "01111100", 4641 data125 when "01111101", 4642 data126 when "01111110", 4643 data127 when "01111111", 4644 data128 when "10000000", 4645 data129 when "10000001", 4646 data130 when "10000010", 4647 data131 when "10000011", 4648 data132 when "10000100", 4649 data133 when "10000101", 4650 data134 when "10000110", 4651 data135 when "10000111", 4652 data136 when "10001000", 4653 data137 when "10001001", 4654 data138 when "10001010", 4655 data139 when "10001011", 4656 data140 when "10001100", 4657 data141 when "10001101", 4658 data142 when "10001110", 4659 data143 when "10001111", 4660 data144 when "10010000", 4661 data145 when "10010001", 4662 data146 when "10010010", 4663 data147 when "10010011", 4664 data148 when "10010100", 4665 data149 when "10010101", 4666 data150 when "10010110", 4667 data151 when "10010111", 4668 data152 when "10011000", 4669 data153 when "10011001", 4670 data154 when "10011010", 4671 data155 when "10011011", 4672 data156 when "10011100", 4673 data157 when "10011101", 4674 data158 when "10011110", 4675 data159 when "10011111", 4676 data160 when "10100000", 4677 data161 when "10100001", 4678 data162 when "10100010", 4679 data163 when "10100011", 4680 data164 when "10100100", 4681 data165 when "10100101", 4682 data166 when "10100110", 4683 data167 when "10100111", 4684 data168 when "10101000", 4685 data169 when "10101001", 4686 data170 when "10101010", 4687 data171 when "10101011", 4688 data172 when "10101100", 4689 data173 when "10101101", 4690 data174 when "10101110", 4691 data175 when "10101111", 4692 data176 when "10110000", 4693 data177 when "10110001", 4694 data178 when "10110010", 4695 data179 when "10110011", 4696 data180 when "10110100", 4697 data181 when "10110101", 4698 data182 when "10110110", 4699 data183 when "10110111", 4700 data184 when "10111000", 4701 data185 when "10111001", 4702 data186 when "10111010", 4703 data187 when "10111011", 4704 data188 when "10111100", 4705 data189 when "10111101", 4706 data190 when "10111110", 4707 data191 when "10111111", 4708 data192 when "11000000", 4709 data193 when "11000001", 4710 data194 when "11000010", 4711 data195 when "11000011", 4712 data196 when "11000100", 4713 data197 when "11000101", 4714 data198 when "11000110", 4715 data199 when "11000111", 4716 data200 when "11001000", 4717 data201 when "11001001", 4718 data202 when "11001010", 4719 data203 when "11001011", 4720 data204 when "11001100", 4721 data205 when "11001101", 4722 data206 when "11001110", 4723 data207 when "11001111", 4724 data208 when "11010000", 4725 data209 when "11010001", 4726 data210 when "11010010", 4727 data211 when "11010011", 4728 data212 when "11010100", 4729 data213 when "11010101", 4730 data214 when "11010110", 4731 data215 when "11010111", 4732 data216 when "11011000", 4733 data217 when "11011001", 4734 data218 when "11011010", 4735 data219 when "11011011", 4736 data220 when "11011100", 4737 data221 when "11011101", 4738 data222 when "11011110", 4739 data223 when "11011111", 4740 data224 when "11100000", 4741 data225 when "11100001", 4742 data226 when "11100010", 4743 data227 when "11100011", 4744 data228 when "11100100", 4745 data229 when "11100101", 4746 data230 when "11100110", 4747 data231 when "11100111", 4748 data232 when "11101000", 4749 data233 when "11101001", 4750 data234 when "11101010", 4751 data235 when "11101011", 4752 data236 when "11101100", 4753 data237 when "11101101", 4754 data238 when "11101110", 4755 data239 when "11101111", 4756 data240 when "11110000", 4757 data241 when "11110001", 4758 data242 when "11110010", 4759 data243 when "11110011", 4760 data244 when "11110100", 4761 data245 when "11110101", 4762 data246 when "11110110", 4763 data247 when "11110111", 4764 data248 when "11111000", 4765 data249 when "11111001", 4766 data250 when "11111010", 4767 data251 when "11111011", 4768 data252 when "11111100", 4769 data253 when "11111101", 4770 data254 when "11111110", 4771 data255 when "11111111", 4772 '0' when others; 4773end; 4774 4775library ieee; 4776use ieee.std_logic_1164.all; 4777 4778entity encoder256xN is 4779generic( 4780 N: positive 4781); 4782port( 4783 data0: in std_logic_vector((N-1) downto 0); 4784 data1: in std_logic_vector((N-1) downto 0); 4785 data2: in std_logic_vector((N-1) downto 0); 4786 data3: in std_logic_vector((N-1) downto 0); 4787 data4: in std_logic_vector((N-1) downto 0); 4788 data5: in std_logic_vector((N-1) downto 0); 4789 data6: in std_logic_vector((N-1) downto 0); 4790 data7: in std_logic_vector((N-1) downto 0); 4791 data8: in std_logic_vector((N-1) downto 0); 4792 data9: in std_logic_vector((N-1) downto 0); 4793 data10: in std_logic_vector((N-1) downto 0); 4794 data11: in std_logic_vector((N-1) downto 0); 4795 data12: in std_logic_vector((N-1) downto 0); 4796 data13: in std_logic_vector((N-1) downto 0); 4797 data14: in std_logic_vector((N-1) downto 0); 4798 data15: in std_logic_vector((N-1) downto 0); 4799 data16: in std_logic_vector((N-1) downto 0); 4800 data17: in std_logic_vector((N-1) downto 0); 4801 data18: in std_logic_vector((N-1) downto 0); 4802 data19: in std_logic_vector((N-1) downto 0); 4803 data20: in std_logic_vector((N-1) downto 0); 4804 data21: in std_logic_vector((N-1) downto 0); 4805 data22: in std_logic_vector((N-1) downto 0); 4806 data23: in std_logic_vector((N-1) downto 0); 4807 data24: in std_logic_vector((N-1) downto 0); 4808 data25: in std_logic_vector((N-1) downto 0); 4809 data26: in std_logic_vector((N-1) downto 0); 4810 data27: in std_logic_vector((N-1) downto 0); 4811 data28: in std_logic_vector((N-1) downto 0); 4812 data29: in std_logic_vector((N-1) downto 0); 4813 data30: in std_logic_vector((N-1) downto 0); 4814 data31: in std_logic_vector((N-1) downto 0); 4815 data32: in std_logic_vector((N-1) downto 0); 4816 data33: in std_logic_vector((N-1) downto 0); 4817 data34: in std_logic_vector((N-1) downto 0); 4818 data35: in std_logic_vector((N-1) downto 0); 4819 data36: in std_logic_vector((N-1) downto 0); 4820 data37: in std_logic_vector((N-1) downto 0); 4821 data38: in std_logic_vector((N-1) downto 0); 4822 data39: in std_logic_vector((N-1) downto 0); 4823 data40: in std_logic_vector((N-1) downto 0); 4824 data41: in std_logic_vector((N-1) downto 0); 4825 data42: in std_logic_vector((N-1) downto 0); 4826 data43: in std_logic_vector((N-1) downto 0); 4827 data44: in std_logic_vector((N-1) downto 0); 4828 data45: in std_logic_vector((N-1) downto 0); 4829 data46: in std_logic_vector((N-1) downto 0); 4830 data47: in std_logic_vector((N-1) downto 0); 4831 data48: in std_logic_vector((N-1) downto 0); 4832 data49: in std_logic_vector((N-1) downto 0); 4833 data50: in std_logic_vector((N-1) downto 0); 4834 data51: in std_logic_vector((N-1) downto 0); 4835 data52: in std_logic_vector((N-1) downto 0); 4836 data53: in std_logic_vector((N-1) downto 0); 4837 data54: in std_logic_vector((N-1) downto 0); 4838 data55: in std_logic_vector((N-1) downto 0); 4839 data56: in std_logic_vector((N-1) downto 0); 4840 data57: in std_logic_vector((N-1) downto 0); 4841 data58: in std_logic_vector((N-1) downto 0); 4842 data59: in std_logic_vector((N-1) downto 0); 4843 data60: in std_logic_vector((N-1) downto 0); 4844 data61: in std_logic_vector((N-1) downto 0); 4845 data62: in std_logic_vector((N-1) downto 0); 4846 data63: in std_logic_vector((N-1) downto 0); 4847 data64: in std_logic_vector((N-1) downto 0); 4848 data65: in std_logic_vector((N-1) downto 0); 4849 data66: in std_logic_vector((N-1) downto 0); 4850 data67: in std_logic_vector((N-1) downto 0); 4851 data68: in std_logic_vector((N-1) downto 0); 4852 data69: in std_logic_vector((N-1) downto 0); 4853 data70: in std_logic_vector((N-1) downto 0); 4854 data71: in std_logic_vector((N-1) downto 0); 4855 data72: in std_logic_vector((N-1) downto 0); 4856 data73: in std_logic_vector((N-1) downto 0); 4857 data74: in std_logic_vector((N-1) downto 0); 4858 data75: in std_logic_vector((N-1) downto 0); 4859 data76: in std_logic_vector((N-1) downto 0); 4860 data77: in std_logic_vector((N-1) downto 0); 4861 data78: in std_logic_vector((N-1) downto 0); 4862 data79: in std_logic_vector((N-1) downto 0); 4863 data80: in std_logic_vector((N-1) downto 0); 4864 data81: in std_logic_vector((N-1) downto 0); 4865 data82: in std_logic_vector((N-1) downto 0); 4866 data83: in std_logic_vector((N-1) downto 0); 4867 data84: in std_logic_vector((N-1) downto 0); 4868 data85: in std_logic_vector((N-1) downto 0); 4869 data86: in std_logic_vector((N-1) downto 0); 4870 data87: in std_logic_vector((N-1) downto 0); 4871 data88: in std_logic_vector((N-1) downto 0); 4872 data89: in std_logic_vector((N-1) downto 0); 4873 data90: in std_logic_vector((N-1) downto 0); 4874 data91: in std_logic_vector((N-1) downto 0); 4875 data92: in std_logic_vector((N-1) downto 0); 4876 data93: in std_logic_vector((N-1) downto 0); 4877 data94: in std_logic_vector((N-1) downto 0); 4878 data95: in std_logic_vector((N-1) downto 0); 4879 data96: in std_logic_vector((N-1) downto 0); 4880 data97: in std_logic_vector((N-1) downto 0); 4881 data98: in std_logic_vector((N-1) downto 0); 4882 data99: in std_logic_vector((N-1) downto 0); 4883 data100: in std_logic_vector((N-1) downto 0); 4884 data101: in std_logic_vector((N-1) downto 0); 4885 data102: in std_logic_vector((N-1) downto 0); 4886 data103: in std_logic_vector((N-1) downto 0); 4887 data104: in std_logic_vector((N-1) downto 0); 4888 data105: in std_logic_vector((N-1) downto 0); 4889 data106: in std_logic_vector((N-1) downto 0); 4890 data107: in std_logic_vector((N-1) downto 0); 4891 data108: in std_logic_vector((N-1) downto 0); 4892 data109: in std_logic_vector((N-1) downto 0); 4893 data110: in std_logic_vector((N-1) downto 0); 4894 data111: in std_logic_vector((N-1) downto 0); 4895 data112: in std_logic_vector((N-1) downto 0); 4896 data113: in std_logic_vector((N-1) downto 0); 4897 data114: in std_logic_vector((N-1) downto 0); 4898 data115: in std_logic_vector((N-1) downto 0); 4899 data116: in std_logic_vector((N-1) downto 0); 4900 data117: in std_logic_vector((N-1) downto 0); 4901 data118: in std_logic_vector((N-1) downto 0); 4902 data119: in std_logic_vector((N-1) downto 0); 4903 data120: in std_logic_vector((N-1) downto 0); 4904 data121: in std_logic_vector((N-1) downto 0); 4905 data122: in std_logic_vector((N-1) downto 0); 4906 data123: in std_logic_vector((N-1) downto 0); 4907 data124: in std_logic_vector((N-1) downto 0); 4908 data125: in std_logic_vector((N-1) downto 0); 4909 data126: in std_logic_vector((N-1) downto 0); 4910 data127: in std_logic_vector((N-1) downto 0); 4911 data128: in std_logic_vector((N-1) downto 0); 4912 data129: in std_logic_vector((N-1) downto 0); 4913 data130: in std_logic_vector((N-1) downto 0); 4914 data131: in std_logic_vector((N-1) downto 0); 4915 data132: in std_logic_vector((N-1) downto 0); 4916 data133: in std_logic_vector((N-1) downto 0); 4917 data134: in std_logic_vector((N-1) downto 0); 4918 data135: in std_logic_vector((N-1) downto 0); 4919 data136: in std_logic_vector((N-1) downto 0); 4920 data137: in std_logic_vector((N-1) downto 0); 4921 data138: in std_logic_vector((N-1) downto 0); 4922 data139: in std_logic_vector((N-1) downto 0); 4923 data140: in std_logic_vector((N-1) downto 0); 4924 data141: in std_logic_vector((N-1) downto 0); 4925 data142: in std_logic_vector((N-1) downto 0); 4926 data143: in std_logic_vector((N-1) downto 0); 4927 data144: in std_logic_vector((N-1) downto 0); 4928 data145: in std_logic_vector((N-1) downto 0); 4929 data146: in std_logic_vector((N-1) downto 0); 4930 data147: in std_logic_vector((N-1) downto 0); 4931 data148: in std_logic_vector((N-1) downto 0); 4932 data149: in std_logic_vector((N-1) downto 0); 4933 data150: in std_logic_vector((N-1) downto 0); 4934 data151: in std_logic_vector((N-1) downto 0); 4935 data152: in std_logic_vector((N-1) downto 0); 4936 data153: in std_logic_vector((N-1) downto 0); 4937 data154: in std_logic_vector((N-1) downto 0); 4938 data155: in std_logic_vector((N-1) downto 0); 4939 data156: in std_logic_vector((N-1) downto 0); 4940 data157: in std_logic_vector((N-1) downto 0); 4941 data158: in std_logic_vector((N-1) downto 0); 4942 data159: in std_logic_vector((N-1) downto 0); 4943 data160: in std_logic_vector((N-1) downto 0); 4944 data161: in std_logic_vector((N-1) downto 0); 4945 data162: in std_logic_vector((N-1) downto 0); 4946 data163: in std_logic_vector((N-1) downto 0); 4947 data164: in std_logic_vector((N-1) downto 0); 4948 data165: in std_logic_vector((N-1) downto 0); 4949 data166: in std_logic_vector((N-1) downto 0); 4950 data167: in std_logic_vector((N-1) downto 0); 4951 data168: in std_logic_vector((N-1) downto 0); 4952 data169: in std_logic_vector((N-1) downto 0); 4953 data170: in std_logic_vector((N-1) downto 0); 4954 data171: in std_logic_vector((N-1) downto 0); 4955 data172: in std_logic_vector((N-1) downto 0); 4956 data173: in std_logic_vector((N-1) downto 0); 4957 data174: in std_logic_vector((N-1) downto 0); 4958 data175: in std_logic_vector((N-1) downto 0); 4959 data176: in std_logic_vector((N-1) downto 0); 4960 data177: in std_logic_vector((N-1) downto 0); 4961 data178: in std_logic_vector((N-1) downto 0); 4962 data179: in std_logic_vector((N-1) downto 0); 4963 data180: in std_logic_vector((N-1) downto 0); 4964 data181: in std_logic_vector((N-1) downto 0); 4965 data182: in std_logic_vector((N-1) downto 0); 4966 data183: in std_logic_vector((N-1) downto 0); 4967 data184: in std_logic_vector((N-1) downto 0); 4968 data185: in std_logic_vector((N-1) downto 0); 4969 data186: in std_logic_vector((N-1) downto 0); 4970 data187: in std_logic_vector((N-1) downto 0); 4971 data188: in std_logic_vector((N-1) downto 0); 4972 data189: in std_logic_vector((N-1) downto 0); 4973 data190: in std_logic_vector((N-1) downto 0); 4974 data191: in std_logic_vector((N-1) downto 0); 4975 data192: in std_logic_vector((N-1) downto 0); 4976 data193: in std_logic_vector((N-1) downto 0); 4977 data194: in std_logic_vector((N-1) downto 0); 4978 data195: in std_logic_vector((N-1) downto 0); 4979 data196: in std_logic_vector((N-1) downto 0); 4980 data197: in std_logic_vector((N-1) downto 0); 4981 data198: in std_logic_vector((N-1) downto 0); 4982 data199: in std_logic_vector((N-1) downto 0); 4983 data200: in std_logic_vector((N-1) downto 0); 4984 data201: in std_logic_vector((N-1) downto 0); 4985 data202: in std_logic_vector((N-1) downto 0); 4986 data203: in std_logic_vector((N-1) downto 0); 4987 data204: in std_logic_vector((N-1) downto 0); 4988 data205: in std_logic_vector((N-1) downto 0); 4989 data206: in std_logic_vector((N-1) downto 0); 4990 data207: in std_logic_vector((N-1) downto 0); 4991 data208: in std_logic_vector((N-1) downto 0); 4992 data209: in std_logic_vector((N-1) downto 0); 4993 data210: in std_logic_vector((N-1) downto 0); 4994 data211: in std_logic_vector((N-1) downto 0); 4995 data212: in std_logic_vector((N-1) downto 0); 4996 data213: in std_logic_vector((N-1) downto 0); 4997 data214: in std_logic_vector((N-1) downto 0); 4998 data215: in std_logic_vector((N-1) downto 0); 4999 data216: in std_logic_vector((N-1) downto 0); 5000 data217: in std_logic_vector((N-1) downto 0); 5001 data218: in std_logic_vector((N-1) downto 0); 5002 data219: in std_logic_vector((N-1) downto 0); 5003 data220: in std_logic_vector((N-1) downto 0); 5004 data221: in std_logic_vector((N-1) downto 0); 5005 data222: in std_logic_vector((N-1) downto 0); 5006 data223: in std_logic_vector((N-1) downto 0); 5007 data224: in std_logic_vector((N-1) downto 0); 5008 data225: in std_logic_vector((N-1) downto 0); 5009 data226: in std_logic_vector((N-1) downto 0); 5010 data227: in std_logic_vector((N-1) downto 0); 5011 data228: in std_logic_vector((N-1) downto 0); 5012 data229: in std_logic_vector((N-1) downto 0); 5013 data230: in std_logic_vector((N-1) downto 0); 5014 data231: in std_logic_vector((N-1) downto 0); 5015 data232: in std_logic_vector((N-1) downto 0); 5016 data233: in std_logic_vector((N-1) downto 0); 5017 data234: in std_logic_vector((N-1) downto 0); 5018 data235: in std_logic_vector((N-1) downto 0); 5019 data236: in std_logic_vector((N-1) downto 0); 5020 data237: in std_logic_vector((N-1) downto 0); 5021 data238: in std_logic_vector((N-1) downto 0); 5022 data239: in std_logic_vector((N-1) downto 0); 5023 data240: in std_logic_vector((N-1) downto 0); 5024 data241: in std_logic_vector((N-1) downto 0); 5025 data242: in std_logic_vector((N-1) downto 0); 5026 data243: in std_logic_vector((N-1) downto 0); 5027 data244: in std_logic_vector((N-1) downto 0); 5028 data245: in std_logic_vector((N-1) downto 0); 5029 data246: in std_logic_vector((N-1) downto 0); 5030 data247: in std_logic_vector((N-1) downto 0); 5031 data248: in std_logic_vector((N-1) downto 0); 5032 data249: in std_logic_vector((N-1) downto 0); 5033 data250: in std_logic_vector((N-1) downto 0); 5034 data251: in std_logic_vector((N-1) downto 0); 5035 data252: in std_logic_vector((N-1) downto 0); 5036 data253: in std_logic_vector((N-1) downto 0); 5037 data254: in std_logic_vector((N-1) downto 0); 5038 data255: in std_logic_vector((N-1) downto 0); 5039 address: in std_logic_vector(7 downto 0); 5040 output: out std_logic_vector((N-1) downto 0) 5041); 5042end; 5043 5044architecture struct_encoder256xN of encoder256xN is 5045component encoder256x1 is 5046port( 5047 data0: in std_logic; 5048 data1: in std_logic; 5049 data2: in std_logic; 5050 data3: in std_logic; 5051 data4: in std_logic; 5052 data5: in std_logic; 5053 data6: in std_logic; 5054 data7: in std_logic; 5055 data8: in std_logic; 5056 data9: in std_logic; 5057 data10: in std_logic; 5058 data11: in std_logic; 5059 data12: in std_logic; 5060 data13: in std_logic; 5061 data14: in std_logic; 5062 data15: in std_logic; 5063 data16: in std_logic; 5064 data17: in std_logic; 5065 data18: in std_logic; 5066 data19: in std_logic; 5067 data20: in std_logic; 5068 data21: in std_logic; 5069 data22: in std_logic; 5070 data23: in std_logic; 5071 data24: in std_logic; 5072 data25: in std_logic; 5073 data26: in std_logic; 5074 data27: in std_logic; 5075 data28: in std_logic; 5076 data29: in std_logic; 5077 data30: in std_logic; 5078 data31: in std_logic; 5079 data32: in std_logic; 5080 data33: in std_logic; 5081 data34: in std_logic; 5082 data35: in std_logic; 5083 data36: in std_logic; 5084 data37: in std_logic; 5085 data38: in std_logic; 5086 data39: in std_logic; 5087 data40: in std_logic; 5088 data41: in std_logic; 5089 data42: in std_logic; 5090 data43: in std_logic; 5091 data44: in std_logic; 5092 data45: in std_logic; 5093 data46: in std_logic; 5094 data47: in std_logic; 5095 data48: in std_logic; 5096 data49: in std_logic; 5097 data50: in std_logic; 5098 data51: in std_logic; 5099 data52: in std_logic; 5100 data53: in std_logic; 5101 data54: in std_logic; 5102 data55: in std_logic; 5103 data56: in std_logic; 5104 data57: in std_logic; 5105 data58: in std_logic; 5106 data59: in std_logic; 5107 data60: in std_logic; 5108 data61: in std_logic; 5109 data62: in std_logic; 5110 data63: in std_logic; 5111 data64: in std_logic; 5112 data65: in std_logic; 5113 data66: in std_logic; 5114 data67: in std_logic; 5115 data68: in std_logic; 5116 data69: in std_logic; 5117 data70: in std_logic; 5118 data71: in std_logic; 5119 data72: in std_logic; 5120 data73: in std_logic; 5121 data74: in std_logic; 5122 data75: in std_logic; 5123 data76: in std_logic; 5124 data77: in std_logic; 5125 data78: in std_logic; 5126 data79: in std_logic; 5127 data80: in std_logic; 5128 data81: in std_logic; 5129 data82: in std_logic; 5130 data83: in std_logic; 5131 data84: in std_logic; 5132 data85: in std_logic; 5133 data86: in std_logic; 5134 data87: in std_logic; 5135 data88: in std_logic; 5136 data89: in std_logic; 5137 data90: in std_logic; 5138 data91: in std_logic; 5139 data92: in std_logic; 5140 data93: in std_logic; 5141 data94: in std_logic; 5142 data95: in std_logic; 5143 data96: in std_logic; 5144 data97: in std_logic; 5145 data98: in std_logic; 5146 data99: in std_logic; 5147 data100: in std_logic; 5148 data101: in std_logic; 5149 data102: in std_logic; 5150 data103: in std_logic; 5151 data104: in std_logic; 5152 data105: in std_logic; 5153 data106: in std_logic; 5154 data107: in std_logic; 5155 data108: in std_logic; 5156 data109: in std_logic; 5157 data110: in std_logic; 5158 data111: in std_logic; 5159 data112: in std_logic; 5160 data113: in std_logic; 5161 data114: in std_logic; 5162 data115: in std_logic; 5163 data116: in std_logic; 5164 data117: in std_logic; 5165 data118: in std_logic; 5166 data119: in std_logic; 5167 data120: in std_logic; 5168 data121: in std_logic; 5169 data122: in std_logic; 5170 data123: in std_logic; 5171 data124: in std_logic; 5172 data125: in std_logic; 5173 data126: in std_logic; 5174 data127: in std_logic; 5175 data128: in std_logic; 5176 data129: in std_logic; 5177 data130: in std_logic; 5178 data131: in std_logic; 5179 data132: in std_logic; 5180 data133: in std_logic; 5181 data134: in std_logic; 5182 data135: in std_logic; 5183 data136: in std_logic; 5184 data137: in std_logic; 5185 data138: in std_logic; 5186 data139: in std_logic; 5187 data140: in std_logic; 5188 data141: in std_logic; 5189 data142: in std_logic; 5190 data143: in std_logic; 5191 data144: in std_logic; 5192 data145: in std_logic; 5193 data146: in std_logic; 5194 data147: in std_logic; 5195 data148: in std_logic; 5196 data149: in std_logic; 5197 data150: in std_logic; 5198 data151: in std_logic; 5199 data152: in std_logic; 5200 data153: in std_logic; 5201 data154: in std_logic; 5202 data155: in std_logic; 5203 data156: in std_logic; 5204 data157: in std_logic; 5205 data158: in std_logic; 5206 data159: in std_logic; 5207 data160: in std_logic; 5208 data161: in std_logic; 5209 data162: in std_logic; 5210 data163: in std_logic; 5211 data164: in std_logic; 5212 data165: in std_logic; 5213 data166: in std_logic; 5214 data167: in std_logic; 5215 data168: in std_logic; 5216 data169: in std_logic; 5217 data170: in std_logic; 5218 data171: in std_logic; 5219 data172: in std_logic; 5220 data173: in std_logic; 5221 data174: in std_logic; 5222 data175: in std_logic; 5223 data176: in std_logic; 5224 data177: in std_logic; 5225 data178: in std_logic; 5226 data179: in std_logic; 5227 data180: in std_logic; 5228 data181: in std_logic; 5229 data182: in std_logic; 5230 data183: in std_logic; 5231 data184: in std_logic; 5232 data185: in std_logic; 5233 data186: in std_logic; 5234 data187: in std_logic; 5235 data188: in std_logic; 5236 data189: in std_logic; 5237 data190: in std_logic; 5238 data191: in std_logic; 5239 data192: in std_logic; 5240 data193: in std_logic; 5241 data194: in std_logic; 5242 data195: in std_logic; 5243 data196: in std_logic; 5244 data197: in std_logic; 5245 data198: in std_logic; 5246 data199: in std_logic; 5247 data200: in std_logic; 5248 data201: in std_logic; 5249 data202: in std_logic; 5250 data203: in std_logic; 5251 data204: in std_logic; 5252 data205: in std_logic; 5253 data206: in std_logic; 5254 data207: in std_logic; 5255 data208: in std_logic; 5256 data209: in std_logic; 5257 data210: in std_logic; 5258 data211: in std_logic; 5259 data212: in std_logic; 5260 data213: in std_logic; 5261 data214: in std_logic; 5262 data215: in std_logic; 5263 data216: in std_logic; 5264 data217: in std_logic; 5265 data218: in std_logic; 5266 data219: in std_logic; 5267 data220: in std_logic; 5268 data221: in std_logic; 5269 data222: in std_logic; 5270 data223: in std_logic; 5271 data224: in std_logic; 5272 data225: in std_logic; 5273 data226: in std_logic; 5274 data227: in std_logic; 5275 data228: in std_logic; 5276 data229: in std_logic; 5277 data230: in std_logic; 5278 data231: in std_logic; 5279 data232: in std_logic; 5280 data233: in std_logic; 5281 data234: in std_logic; 5282 data235: in std_logic; 5283 data236: in std_logic; 5284 data237: in std_logic; 5285 data238: in std_logic; 5286 data239: in std_logic; 5287 data240: in std_logic; 5288 data241: in std_logic; 5289 data242: in std_logic; 5290 data243: in std_logic; 5291 data244: in std_logic; 5292 data245: in std_logic; 5293 data246: in std_logic; 5294 data247: in std_logic; 5295 data248: in std_logic; 5296 data249: in std_logic; 5297 data250: in std_logic; 5298 data251: in std_logic; 5299 data252: in std_logic; 5300 data253: in std_logic; 5301 data254: in std_logic; 5302 data255: in std_logic; 5303 address: in std_logic_vector(7 downto 0); 5304 output: out std_logic 5305); 5306end component; 5307 5308begin 5309 u1: for i in (N-1) downto 0 generate 5310 u: encoder256x1 port map( 5311 data0 => data0(i), 5312 data1 => data1(i), 5313 data2 => data2(i), 5314 data3 => data3(i), 5315 data4 => data4(i), 5316 data5 => data5(i), 5317 data6 => data6(i), 5318 data7 => data7(i), 5319 data8 => data8(i), 5320 data9 => data9(i), 5321 data10 => data10(i), 5322 data11 => data11(i), 5323 data12 => data12(i), 5324 data13 => data13(i), 5325 data14 => data14(i), 5326 data15 => data15(i), 5327 data16 => data16(i), 5328 data17 => data17(i), 5329 data18 => data18(i), 5330 data19 => data19(i), 5331 data20 => data20(i), 5332 data21 => data21(i), 5333 data22 => data22(i), 5334 data23 => data23(i), 5335 data24 => data24(i), 5336 data25 => data25(i), 5337 data26 => data26(i), 5338 data27 => data27(i), 5339 data28 => data28(i), 5340 data29 => data29(i), 5341 data30 => data30(i), 5342 data31 => data31(i), 5343 data32 => data32(i), 5344 data33 => data33(i), 5345 data34 => data34(i), 5346 data35 => data35(i), 5347 data36 => data36(i), 5348 data37 => data37(i), 5349 data38 => data38(i), 5350 data39 => data39(i), 5351 data40 => data40(i), 5352 data41 => data41(i), 5353 data42 => data42(i), 5354 data43 => data43(i), 5355 data44 => data44(i), 5356 data45 => data45(i), 5357 data46 => data46(i), 5358 data47 => data47(i), 5359 data48 => data48(i), 5360 data49 => data49(i), 5361 data50 => data50(i), 5362 data51 => data51(i), 5363 data52 => data52(i), 5364 data53 => data53(i), 5365 data54 => data54(i), 5366 data55 => data55(i), 5367 data56 => data56(i), 5368 data57 => data57(i), 5369 data58 => data58(i), 5370 data59 => data59(i), 5371 data60 => data60(i), 5372 data61 => data61(i), 5373 data62 => data62(i), 5374 data63 => data63(i), 5375 data64 => data64(i), 5376 data65 => data65(i), 5377 data66 => data66(i), 5378 data67 => data67(i), 5379 data68 => data68(i), 5380 data69 => data69(i), 5381 data70 => data70(i), 5382 data71 => data71(i), 5383 data72 => data72(i), 5384 data73 => data73(i), 5385 data74 => data74(i), 5386 data75 => data75(i), 5387 data76 => data76(i), 5388 data77 => data77(i), 5389 data78 => data78(i), 5390 data79 => data79(i), 5391 data80 => data80(i), 5392 data81 => data81(i), 5393 data82 => data82(i), 5394 data83 => data83(i), 5395 data84 => data84(i), 5396 data85 => data85(i), 5397 data86 => data86(i), 5398 data87 => data87(i), 5399 data88 => data88(i), 5400 data89 => data89(i), 5401 data90 => data90(i), 5402 data91 => data91(i), 5403 data92 => data92(i), 5404 data93 => data93(i), 5405 data94 => data94(i), 5406 data95 => data95(i), 5407 data96 => data96(i), 5408 data97 => data97(i), 5409 data98 => data98(i), 5410 data99 => data99(i), 5411 data100 => data100(i), 5412 data101 => data101(i), 5413 data102 => data102(i), 5414 data103 => data103(i), 5415 data104 => data104(i), 5416 data105 => data105(i), 5417 data106 => data106(i), 5418 data107 => data107(i), 5419 data108 => data108(i), 5420 data109 => data109(i), 5421 data110 => data110(i), 5422 data111 => data111(i), 5423 data112 => data112(i), 5424 data113 => data113(i), 5425 data114 => data114(i), 5426 data115 => data115(i), 5427 data116 => data116(i), 5428 data117 => data117(i), 5429 data118 => data118(i), 5430 data119 => data119(i), 5431 data120 => data120(i), 5432 data121 => data121(i), 5433 data122 => data122(i), 5434 data123 => data123(i), 5435 data124 => data124(i), 5436 data125 => data125(i), 5437 data126 => data126(i), 5438 data127 => data127(i), 5439 data128 => data128(i), 5440 data129 => data129(i), 5441 data130 => data130(i), 5442 data131 => data131(i), 5443 data132 => data132(i), 5444 data133 => data133(i), 5445 data134 => data134(i), 5446 data135 => data135(i), 5447 data136 => data136(i), 5448 data137 => data137(i), 5449 data138 => data138(i), 5450 data139 => data139(i), 5451 data140 => data140(i), 5452 data141 => data141(i), 5453 data142 => data142(i), 5454 data143 => data143(i), 5455 data144 => data144(i), 5456 data145 => data145(i), 5457 data146 => data146(i), 5458 data147 => data147(i), 5459 data148 => data148(i), 5460 data149 => data149(i), 5461 data150 => data150(i), 5462 data151 => data151(i), 5463 data152 => data152(i), 5464 data153 => data153(i), 5465 data154 => data154(i), 5466 data155 => data155(i), 5467 data156 => data156(i), 5468 data157 => data157(i), 5469 data158 => data158(i), 5470 data159 => data159(i), 5471 data160 => data160(i), 5472 data161 => data161(i), 5473 data162 => data162(i), 5474 data163 => data163(i), 5475 data164 => data164(i), 5476 data165 => data165(i), 5477 data166 => data166(i), 5478 data167 => data167(i), 5479 data168 => data168(i), 5480 data169 => data169(i), 5481 data170 => data170(i), 5482 data171 => data171(i), 5483 data172 => data172(i), 5484 data173 => data173(i), 5485 data174 => data174(i), 5486 data175 => data175(i), 5487 data176 => data176(i), 5488 data177 => data177(i), 5489 data178 => data178(i), 5490 data179 => data179(i), 5491 data180 => data180(i), 5492 data181 => data181(i), 5493 data182 => data182(i), 5494 data183 => data183(i), 5495 data184 => data184(i), 5496 data185 => data185(i), 5497 data186 => data186(i), 5498 data187 => data187(i), 5499 data188 => data188(i), 5500 data189 => data189(i), 5501 data190 => data190(i), 5502 data191 => data191(i), 5503 data192 => data192(i), 5504 data193 => data193(i), 5505 data194 => data194(i), 5506 data195 => data195(i), 5507 data196 => data196(i), 5508 data197 => data197(i), 5509 data198 => data198(i), 5510 data199 => data199(i), 5511 data200 => data200(i), 5512 data201 => data201(i), 5513 data202 => data202(i), 5514 data203 => data203(i), 5515 data204 => data204(i), 5516 data205 => data205(i), 5517 data206 => data206(i), 5518 data207 => data207(i), 5519 data208 => data208(i), 5520 data209 => data209(i), 5521 data210 => data210(i), 5522 data211 => data211(i), 5523 data212 => data212(i), 5524 data213 => data213(i), 5525 data214 => data214(i), 5526 data215 => data215(i), 5527 data216 => data216(i), 5528 data217 => data217(i), 5529 data218 => data218(i), 5530 data219 => data219(i), 5531 data220 => data220(i), 5532 data221 => data221(i), 5533 data222 => data222(i), 5534 data223 => data223(i), 5535 data224 => data224(i), 5536 data225 => data225(i), 5537 data226 => data226(i), 5538 data227 => data227(i), 5539 data228 => data228(i), 5540 data229 => data229(i), 5541 data230 => data230(i), 5542 data231 => data231(i), 5543 data232 => data232(i), 5544 data233 => data233(i), 5545 data234 => data234(i), 5546 data235 => data235(i), 5547 data236 => data236(i), 5548 data237 => data237(i), 5549 data238 => data238(i), 5550 data239 => data239(i), 5551 data240 => data240(i), 5552 data241 => data241(i), 5553 data242 => data242(i), 5554 data243 => data243(i), 5555 data244 => data244(i), 5556 data245 => data245(i), 5557 data246 => data246(i), 5558 data247 => data247(i), 5559 data248 => data248(i), 5560 data249 => data249(i), 5561 data250 => data250(i), 5562 data251 => data251(i), 5563 data252 => data252(i), 5564 data253 => data253(i), 5565 data254 => data254(i), 5566 data255 => data255(i), 5567 address => address, 5568 output => output(i) 5569 ); 5570 end generate u1; 5571end; 5572 5573library ieee; 5574use ieee.std_logic_1164.all; 5575 5576entity decoder1x256 is 5577port( 5578 data: in std_logic; 5579 y0: out std_logic; 5580 y1: out std_logic; 5581 y2: out std_logic; 5582 y3: out std_logic; 5583 y4: out std_logic; 5584 y5: out std_logic; 5585 y6: out std_logic; 5586 y7: out std_logic; 5587 y8: out std_logic; 5588 y9: out std_logic; 5589 y10: out std_logic; 5590 y11: out std_logic; 5591 y12: out std_logic; 5592 y13: out std_logic; 5593 y14: out std_logic; 5594 y15: out std_logic; 5595 y16: out std_logic; 5596 y17: out std_logic; 5597 y18: out std_logic; 5598 y19: out std_logic; 5599 y20: out std_logic; 5600 y21: out std_logic; 5601 y22: out std_logic; 5602 y23: out std_logic; 5603 y24: out std_logic; 5604 y25: out std_logic; 5605 y26: out std_logic; 5606 y27: out std_logic; 5607 y28: out std_logic; 5608 y29: out std_logic; 5609 y30: out std_logic; 5610 y31: out std_logic; 5611 y32: out std_logic; 5612 y33: out std_logic; 5613 y34: out std_logic; 5614 y35: out std_logic; 5615 y36: out std_logic; 5616 y37: out std_logic; 5617 y38: out std_logic; 5618 y39: out std_logic; 5619 y40: out std_logic; 5620 y41: out std_logic; 5621 y42: out std_logic; 5622 y43: out std_logic; 5623 y44: out std_logic; 5624 y45: out std_logic; 5625 y46: out std_logic; 5626 y47: out std_logic; 5627 y48: out std_logic; 5628 y49: out std_logic; 5629 y50: out std_logic; 5630 y51: out std_logic; 5631 y52: out std_logic; 5632 y53: out std_logic; 5633 y54: out std_logic; 5634 y55: out std_logic; 5635 y56: out std_logic; 5636 y57: out std_logic; 5637 y58: out std_logic; 5638 y59: out std_logic; 5639 y60: out std_logic; 5640 y61: out std_logic; 5641 y62: out std_logic; 5642 y63: out std_logic; 5643 y64: out std_logic; 5644 y65: out std_logic; 5645 y66: out std_logic; 5646 y67: out std_logic; 5647 y68: out std_logic; 5648 y69: out std_logic; 5649 y70: out std_logic; 5650 y71: out std_logic; 5651 y72: out std_logic; 5652 y73: out std_logic; 5653 y74: out std_logic; 5654 y75: out std_logic; 5655 y76: out std_logic; 5656 y77: out std_logic; 5657 y78: out std_logic; 5658 y79: out std_logic; 5659 y80: out std_logic; 5660 y81: out std_logic; 5661 y82: out std_logic; 5662 y83: out std_logic; 5663 y84: out std_logic; 5664 y85: out std_logic; 5665 y86: out std_logic; 5666 y87: out std_logic; 5667 y88: out std_logic; 5668 y89: out std_logic; 5669 y90: out std_logic; 5670 y91: out std_logic; 5671 y92: out std_logic; 5672 y93: out std_logic; 5673 y94: out std_logic; 5674 y95: out std_logic; 5675 y96: out std_logic; 5676 y97: out std_logic; 5677 y98: out std_logic; 5678 y99: out std_logic; 5679 y100: out std_logic; 5680 y101: out std_logic; 5681 y102: out std_logic; 5682 y103: out std_logic; 5683 y104: out std_logic; 5684 y105: out std_logic; 5685 y106: out std_logic; 5686 y107: out std_logic; 5687 y108: out std_logic; 5688 y109: out std_logic; 5689 y110: out std_logic; 5690 y111: out std_logic; 5691 y112: out std_logic; 5692 y113: out std_logic; 5693 y114: out std_logic; 5694 y115: out std_logic; 5695 y116: out std_logic; 5696 y117: out std_logic; 5697 y118: out std_logic; 5698 y119: out std_logic; 5699 y120: out std_logic; 5700 y121: out std_logic; 5701 y122: out std_logic; 5702 y123: out std_logic; 5703 y124: out std_logic; 5704 y125: out std_logic; 5705 y126: out std_logic; 5706 y127: out std_logic; 5707 y128: out std_logic; 5708 y129: out std_logic; 5709 y130: out std_logic; 5710 y131: out std_logic; 5711 y132: out std_logic; 5712 y133: out std_logic; 5713 y134: out std_logic; 5714 y135: out std_logic; 5715 y136: out std_logic; 5716 y137: out std_logic; 5717 y138: out std_logic; 5718 y139: out std_logic; 5719 y140: out std_logic; 5720 y141: out std_logic; 5721 y142: out std_logic; 5722 y143: out std_logic; 5723 y144: out std_logic; 5724 y145: out std_logic; 5725 y146: out std_logic; 5726 y147: out std_logic; 5727 y148: out std_logic; 5728 y149: out std_logic; 5729 y150: out std_logic; 5730 y151: out std_logic; 5731 y152: out std_logic; 5732 y153: out std_logic; 5733 y154: out std_logic; 5734 y155: out std_logic; 5735 y156: out std_logic; 5736 y157: out std_logic; 5737 y158: out std_logic; 5738 y159: out std_logic; 5739 y160: out std_logic; 5740 y161: out std_logic; 5741 y162: out std_logic; 5742 y163: out std_logic; 5743 y164: out std_logic; 5744 y165: out std_logic; 5745 y166: out std_logic; 5746 y167: out std_logic; 5747 y168: out std_logic; 5748 y169: out std_logic; 5749 y170: out std_logic; 5750 y171: out std_logic; 5751 y172: out std_logic; 5752 y173: out std_logic; 5753 y174: out std_logic; 5754 y175: out std_logic; 5755 y176: out std_logic; 5756 y177: out std_logic; 5757 y178: out std_logic; 5758 y179: out std_logic; 5759 y180: out std_logic; 5760 y181: out std_logic; 5761 y182: out std_logic; 5762 y183: out std_logic; 5763 y184: out std_logic; 5764 y185: out std_logic; 5765 y186: out std_logic; 5766 y187: out std_logic; 5767 y188: out std_logic; 5768 y189: out std_logic; 5769 y190: out std_logic; 5770 y191: out std_logic; 5771 y192: out std_logic; 5772 y193: out std_logic; 5773 y194: out std_logic; 5774 y195: out std_logic; 5775 y196: out std_logic; 5776 y197: out std_logic; 5777 y198: out std_logic; 5778 y199: out std_logic; 5779 y200: out std_logic; 5780 y201: out std_logic; 5781 y202: out std_logic; 5782 y203: out std_logic; 5783 y204: out std_logic; 5784 y205: out std_logic; 5785 y206: out std_logic; 5786 y207: out std_logic; 5787 y208: out std_logic; 5788 y209: out std_logic; 5789 y210: out std_logic; 5790 y211: out std_logic; 5791 y212: out std_logic; 5792 y213: out std_logic; 5793 y214: out std_logic; 5794 y215: out std_logic; 5795 y216: out std_logic; 5796 y217: out std_logic; 5797 y218: out std_logic; 5798 y219: out std_logic; 5799 y220: out std_logic; 5800 y221: out std_logic; 5801 y222: out std_logic; 5802 y223: out std_logic; 5803 y224: out std_logic; 5804 y225: out std_logic; 5805 y226: out std_logic; 5806 y227: out std_logic; 5807 y228: out std_logic; 5808 y229: out std_logic; 5809 y230: out std_logic; 5810 y231: out std_logic; 5811 y232: out std_logic; 5812 y233: out std_logic; 5813 y234: out std_logic; 5814 y235: out std_logic; 5815 y236: out std_logic; 5816 y237: out std_logic; 5817 y238: out std_logic; 5818 y239: out std_logic; 5819 y240: out std_logic; 5820 y241: out std_logic; 5821 y242: out std_logic; 5822 y243: out std_logic; 5823 y244: out std_logic; 5824 y245: out std_logic; 5825 y246: out std_logic; 5826 y247: out std_logic; 5827 y248: out std_logic; 5828 y249: out std_logic; 5829 y250: out std_logic; 5830 y251: out std_logic; 5831 y252: out std_logic; 5832 y253: out std_logic; 5833 y254: out std_logic; 5834 y255: out std_logic; 5835 address: in std_logic_vector(7 downto 0) 5836); 5837end; 5838 5839architecture struct_decoder1x256 of decoder1x256 is 5840begin 5841 y0 <= data when address = "00000000" else '0'; 5842 y1 <= data when address = "00000001" else '0'; 5843 y2 <= data when address = "00000010" else '0'; 5844 y3 <= data when address = "00000011" else '0'; 5845 y4 <= data when address = "00000100" else '0'; 5846 y5 <= data when address = "00000101" else '0'; 5847 y6 <= data when address = "00000110" else '0'; 5848 y7 <= data when address = "00000111" else '0'; 5849 y8 <= data when address = "00001000" else '0'; 5850 y9 <= data when address = "00001001" else '0'; 5851 y10 <= data when address = "00001010" else '0'; 5852 y11 <= data when address = "00001011" else '0'; 5853 y12 <= data when address = "00001100" else '0'; 5854 y13 <= data when address = "00001101" else '0'; 5855 y14 <= data when address = "00001110" else '0'; 5856 y15 <= data when address = "00001111" else '0'; 5857 y16 <= data when address = "00010000" else '0'; 5858 y17 <= data when address = "00010001" else '0'; 5859 y18 <= data when address = "00010010" else '0'; 5860 y19 <= data when address = "00010011" else '0'; 5861 y20 <= data when address = "00010100" else '0'; 5862 y21 <= data when address = "00010101" else '0'; 5863 y22 <= data when address = "00010110" else '0'; 5864 y23 <= data when address = "00010111" else '0'; 5865 y24 <= data when address = "00011000" else '0'; 5866 y25 <= data when address = "00011001" else '0'; 5867 y26 <= data when address = "00011010" else '0'; 5868 y27 <= data when address = "00011011" else '0'; 5869 y28 <= data when address = "00011100" else '0'; 5870 y29 <= data when address = "00011101" else '0'; 5871 y30 <= data when address = "00011110" else '0'; 5872 y31 <= data when address = "00011111" else '0'; 5873 y32 <= data when address = "00100000" else '0'; 5874 y33 <= data when address = "00100001" else '0'; 5875 y34 <= data when address = "00100010" else '0'; 5876 y35 <= data when address = "00100011" else '0'; 5877 y36 <= data when address = "00100100" else '0'; 5878 y37 <= data when address = "00100101" else '0'; 5879 y38 <= data when address = "00100110" else '0'; 5880 y39 <= data when address = "00100111" else '0'; 5881 y40 <= data when address = "00101000" else '0'; 5882 y41 <= data when address = "00101001" else '0'; 5883 y42 <= data when address = "00101010" else '0'; 5884 y43 <= data when address = "00101011" else '0'; 5885 y44 <= data when address = "00101100" else '0'; 5886 y45 <= data when address = "00101101" else '0'; 5887 y46 <= data when address = "00101110" else '0'; 5888 y47 <= data when address = "00101111" else '0'; 5889 y48 <= data when address = "00110000" else '0'; 5890 y49 <= data when address = "00110001" else '0'; 5891 y50 <= data when address = "00110010" else '0'; 5892 y51 <= data when address = "00110011" else '0'; 5893 y52 <= data when address = "00110100" else '0'; 5894 y53 <= data when address = "00110101" else '0'; 5895 y54 <= data when address = "00110110" else '0'; 5896 y55 <= data when address = "00110111" else '0'; 5897 y56 <= data when address = "00111000" else '0'; 5898 y57 <= data when address = "00111001" else '0'; 5899 y58 <= data when address = "00111010" else '0'; 5900 y59 <= data when address = "00111011" else '0'; 5901 y60 <= data when address = "00111100" else '0'; 5902 y61 <= data when address = "00111101" else '0'; 5903 y62 <= data when address = "00111110" else '0'; 5904 y63 <= data when address = "00111111" else '0'; 5905 y64 <= data when address = "01000000" else '0'; 5906 y65 <= data when address = "01000001" else '0'; 5907 y66 <= data when address = "01000010" else '0'; 5908 y67 <= data when address = "01000011" else '0'; 5909 y68 <= data when address = "01000100" else '0'; 5910 y69 <= data when address = "01000101" else '0'; 5911 y70 <= data when address = "01000110" else '0'; 5912 y71 <= data when address = "01000111" else '0'; 5913 y72 <= data when address = "01001000" else '0'; 5914 y73 <= data when address = "01001001" else '0'; 5915 y74 <= data when address = "01001010" else '0'; 5916 y75 <= data when address = "01001011" else '0'; 5917 y76 <= data when address = "01001100" else '0'; 5918 y77 <= data when address = "01001101" else '0'; 5919 y78 <= data when address = "01001110" else '0'; 5920 y79 <= data when address = "01001111" else '0'; 5921 y80 <= data when address = "01010000" else '0'; 5922 y81 <= data when address = "01010001" else '0'; 5923 y82 <= data when address = "01010010" else '0'; 5924 y83 <= data when address = "01010011" else '0'; 5925 y84 <= data when address = "01010100" else '0'; 5926 y85 <= data when address = "01010101" else '0'; 5927 y86 <= data when address = "01010110" else '0'; 5928 y87 <= data when address = "01010111" else '0'; 5929 y88 <= data when address = "01011000" else '0'; 5930 y89 <= data when address = "01011001" else '0'; 5931 y90 <= data when address = "01011010" else '0'; 5932 y91 <= data when address = "01011011" else '0'; 5933 y92 <= data when address = "01011100" else '0'; 5934 y93 <= data when address = "01011101" else '0'; 5935 y94 <= data when address = "01011110" else '0'; 5936 y95 <= data when address = "01011111" else '0'; 5937 y96 <= data when address = "01100000" else '0'; 5938 y97 <= data when address = "01100001" else '0'; 5939 y98 <= data when address = "01100010" else '0'; 5940 y99 <= data when address = "01100011" else '0'; 5941 y100 <= data when address = "01100100" else '0'; 5942 y101 <= data when address = "01100101" else '0'; 5943 y102 <= data when address = "01100110" else '0'; 5944 y103 <= data when address = "01100111" else '0'; 5945 y104 <= data when address = "01101000" else '0'; 5946 y105 <= data when address = "01101001" else '0'; 5947 y106 <= data when address = "01101010" else '0'; 5948 y107 <= data when address = "01101011" else '0'; 5949 y108 <= data when address = "01101100" else '0'; 5950 y109 <= data when address = "01101101" else '0'; 5951 y110 <= data when address = "01101110" else '0'; 5952 y111 <= data when address = "01101111" else '0'; 5953 y112 <= data when address = "01110000" else '0'; 5954 y113 <= data when address = "01110001" else '0'; 5955 y114 <= data when address = "01110010" else '0'; 5956 y115 <= data when address = "01110011" else '0'; 5957 y116 <= data when address = "01110100" else '0'; 5958 y117 <= data when address = "01110101" else '0'; 5959 y118 <= data when address = "01110110" else '0'; 5960 y119 <= data when address = "01110111" else '0'; 5961 y120 <= data when address = "01111000" else '0'; 5962 y121 <= data when address = "01111001" else '0'; 5963 y122 <= data when address = "01111010" else '0'; 5964 y123 <= data when address = "01111011" else '0'; 5965 y124 <= data when address = "01111100" else '0'; 5966 y125 <= data when address = "01111101" else '0'; 5967 y126 <= data when address = "01111110" else '0'; 5968 y127 <= data when address = "01111111" else '0'; 5969 y128 <= data when address = "10000000" else '0'; 5970 y129 <= data when address = "10000001" else '0'; 5971 y130 <= data when address = "10000010" else '0'; 5972 y131 <= data when address = "10000011" else '0'; 5973 y132 <= data when address = "10000100" else '0'; 5974 y133 <= data when address = "10000101" else '0'; 5975 y134 <= data when address = "10000110" else '0'; 5976 y135 <= data when address = "10000111" else '0'; 5977 y136 <= data when address = "10001000" else '0'; 5978 y137 <= data when address = "10001001" else '0'; 5979 y138 <= data when address = "10001010" else '0'; 5980 y139 <= data when address = "10001011" else '0'; 5981 y140 <= data when address = "10001100" else '0'; 5982 y141 <= data when address = "10001101" else '0'; 5983 y142 <= data when address = "10001110" else '0'; 5984 y143 <= data when address = "10001111" else '0'; 5985 y144 <= data when address = "10010000" else '0'; 5986 y145 <= data when address = "10010001" else '0'; 5987 y146 <= data when address = "10010010" else '0'; 5988 y147 <= data when address = "10010011" else '0'; 5989 y148 <= data when address = "10010100" else '0'; 5990 y149 <= data when address = "10010101" else '0'; 5991 y150 <= data when address = "10010110" else '0'; 5992 y151 <= data when address = "10010111" else '0'; 5993 y152 <= data when address = "10011000" else '0'; 5994 y153 <= data when address = "10011001" else '0'; 5995 y154 <= data when address = "10011010" else '0'; 5996 y155 <= data when address = "10011011" else '0'; 5997 y156 <= data when address = "10011100" else '0'; 5998 y157 <= data when address = "10011101" else '0'; 5999 y158 <= data when address = "10011110" else '0'; 6000 y159 <= data when address = "10011111" else '0'; 6001 y160 <= data when address = "10100000" else '0'; 6002 y161 <= data when address = "10100001" else '0'; 6003 y162 <= data when address = "10100010" else '0'; 6004 y163 <= data when address = "10100011" else '0'; 6005 y164 <= data when address = "10100100" else '0'; 6006 y165 <= data when address = "10100101" else '0'; 6007 y166 <= data when address = "10100110" else '0'; 6008 y167 <= data when address = "10100111" else '0'; 6009 y168 <= data when address = "10101000" else '0'; 6010 y169 <= data when address = "10101001" else '0'; 6011 y170 <= data when address = "10101010" else '0'; 6012 y171 <= data when address = "10101011" else '0'; 6013 y172 <= data when address = "10101100" else '0'; 6014 y173 <= data when address = "10101101" else '0'; 6015 y174 <= data when address = "10101110" else '0'; 6016 y175 <= data when address = "10101111" else '0'; 6017 y176 <= data when address = "10110000" else '0'; 6018 y177 <= data when address = "10110001" else '0'; 6019 y178 <= data when address = "10110010" else '0'; 6020 y179 <= data when address = "10110011" else '0'; 6021 y180 <= data when address = "10110100" else '0'; 6022 y181 <= data when address = "10110101" else '0'; 6023 y182 <= data when address = "10110110" else '0'; 6024 y183 <= data when address = "10110111" else '0'; 6025 y184 <= data when address = "10111000" else '0'; 6026 y185 <= data when address = "10111001" else '0'; 6027 y186 <= data when address = "10111010" else '0'; 6028 y187 <= data when address = "10111011" else '0'; 6029 y188 <= data when address = "10111100" else '0'; 6030 y189 <= data when address = "10111101" else '0'; 6031 y190 <= data when address = "10111110" else '0'; 6032 y191 <= data when address = "10111111" else '0'; 6033 y192 <= data when address = "11000000" else '0'; 6034 y193 <= data when address = "11000001" else '0'; 6035 y194 <= data when address = "11000010" else '0'; 6036 y195 <= data when address = "11000011" else '0'; 6037 y196 <= data when address = "11000100" else '0'; 6038 y197 <= data when address = "11000101" else '0'; 6039 y198 <= data when address = "11000110" else '0'; 6040 y199 <= data when address = "11000111" else '0'; 6041 y200 <= data when address = "11001000" else '0'; 6042 y201 <= data when address = "11001001" else '0'; 6043 y202 <= data when address = "11001010" else '0'; 6044 y203 <= data when address = "11001011" else '0'; 6045 y204 <= data when address = "11001100" else '0'; 6046 y205 <= data when address = "11001101" else '0'; 6047 y206 <= data when address = "11001110" else '0'; 6048 y207 <= data when address = "11001111" else '0'; 6049 y208 <= data when address = "11010000" else '0'; 6050 y209 <= data when address = "11010001" else '0'; 6051 y210 <= data when address = "11010010" else '0'; 6052 y211 <= data when address = "11010011" else '0'; 6053 y212 <= data when address = "11010100" else '0'; 6054 y213 <= data when address = "11010101" else '0'; 6055 y214 <= data when address = "11010110" else '0'; 6056 y215 <= data when address = "11010111" else '0'; 6057 y216 <= data when address = "11011000" else '0'; 6058 y217 <= data when address = "11011001" else '0'; 6059 y218 <= data when address = "11011010" else '0'; 6060 y219 <= data when address = "11011011" else '0'; 6061 y220 <= data when address = "11011100" else '0'; 6062 y221 <= data when address = "11011101" else '0'; 6063 y222 <= data when address = "11011110" else '0'; 6064 y223 <= data when address = "11011111" else '0'; 6065 y224 <= data when address = "11100000" else '0'; 6066 y225 <= data when address = "11100001" else '0'; 6067 y226 <= data when address = "11100010" else '0'; 6068 y227 <= data when address = "11100011" else '0'; 6069 y228 <= data when address = "11100100" else '0'; 6070 y229 <= data when address = "11100101" else '0'; 6071 y230 <= data when address = "11100110" else '0'; 6072 y231 <= data when address = "11100111" else '0'; 6073 y232 <= data when address = "11101000" else '0'; 6074 y233 <= data when address = "11101001" else '0'; 6075 y234 <= data when address = "11101010" else '0'; 6076 y235 <= data when address = "11101011" else '0'; 6077 y236 <= data when address = "11101100" else '0'; 6078 y237 <= data when address = "11101101" else '0'; 6079 y238 <= data when address = "11101110" else '0'; 6080 y239 <= data when address = "11101111" else '0'; 6081 y240 <= data when address = "11110000" else '0'; 6082 y241 <= data when address = "11110001" else '0'; 6083 y242 <= data when address = "11110010" else '0'; 6084 y243 <= data when address = "11110011" else '0'; 6085 y244 <= data when address = "11110100" else '0'; 6086 y245 <= data when address = "11110101" else '0'; 6087 y246 <= data when address = "11110110" else '0'; 6088 y247 <= data when address = "11110111" else '0'; 6089 y248 <= data when address = "11111000" else '0'; 6090 y249 <= data when address = "11111001" else '0'; 6091 y250 <= data when address = "11111010" else '0'; 6092 y251 <= data when address = "11111011" else '0'; 6093 y252 <= data when address = "11111100" else '0'; 6094 y253 <= data when address = "11111101" else '0'; 6095 y254 <= data when address = "11111110" else '0'; 6096 y255 <= data when address = "11111111" else '0'; 6097end; 6098 6099library ieee; 6100use ieee.std_logic_1164.all; 6101 6102entity decoderNx256 is 6103generic( 6104 N: positive 6105); 6106port( 6107 data: in std_logic_vector((N-1) downto 0); 6108 y0: out std_logic_vector((N-1) downto 0); 6109 y1: out std_logic_vector((N-1) downto 0); 6110 y2: out std_logic_vector((N-1) downto 0); 6111 y3: out std_logic_vector((N-1) downto 0); 6112 y4: out std_logic_vector((N-1) downto 0); 6113 y5: out std_logic_vector((N-1) downto 0); 6114 y6: out std_logic_vector((N-1) downto 0); 6115 y7: out std_logic_vector((N-1) downto 0); 6116 y8: out std_logic_vector((N-1) downto 0); 6117 y9: out std_logic_vector((N-1) downto 0); 6118 y10: out std_logic_vector((N-1) downto 0); 6119 y11: out std_logic_vector((N-1) downto 0); 6120 y12: out std_logic_vector((N-1) downto 0); 6121 y13: out std_logic_vector((N-1) downto 0); 6122 y14: out std_logic_vector((N-1) downto 0); 6123 y15: out std_logic_vector((N-1) downto 0); 6124 y16: out std_logic_vector((N-1) downto 0); 6125 y17: out std_logic_vector((N-1) downto 0); 6126 y18: out std_logic_vector((N-1) downto 0); 6127 y19: out std_logic_vector((N-1) downto 0); 6128 y20: out std_logic_vector((N-1) downto 0); 6129 y21: out std_logic_vector((N-1) downto 0); 6130 y22: out std_logic_vector((N-1) downto 0); 6131 y23: out std_logic_vector((N-1) downto 0); 6132 y24: out std_logic_vector((N-1) downto 0); 6133 y25: out std_logic_vector((N-1) downto 0); 6134 y26: out std_logic_vector((N-1) downto 0); 6135 y27: out std_logic_vector((N-1) downto 0); 6136 y28: out std_logic_vector((N-1) downto 0); 6137 y29: out std_logic_vector((N-1) downto 0); 6138 y30: out std_logic_vector((N-1) downto 0); 6139 y31: out std_logic_vector((N-1) downto 0); 6140 y32: out std_logic_vector((N-1) downto 0); 6141 y33: out std_logic_vector((N-1) downto 0); 6142 y34: out std_logic_vector((N-1) downto 0); 6143 y35: out std_logic_vector((N-1) downto 0); 6144 y36: out std_logic_vector((N-1) downto 0); 6145 y37: out std_logic_vector((N-1) downto 0); 6146 y38: out std_logic_vector((N-1) downto 0); 6147 y39: out std_logic_vector((N-1) downto 0); 6148 y40: out std_logic_vector((N-1) downto 0); 6149 y41: out std_logic_vector((N-1) downto 0); 6150 y42: out std_logic_vector((N-1) downto 0); 6151 y43: out std_logic_vector((N-1) downto 0); 6152 y44: out std_logic_vector((N-1) downto 0); 6153 y45: out std_logic_vector((N-1) downto 0); 6154 y46: out std_logic_vector((N-1) downto 0); 6155 y47: out std_logic_vector((N-1) downto 0); 6156 y48: out std_logic_vector((N-1) downto 0); 6157 y49: out std_logic_vector((N-1) downto 0); 6158 y50: out std_logic_vector((N-1) downto 0); 6159 y51: out std_logic_vector((N-1) downto 0); 6160 y52: out std_logic_vector((N-1) downto 0); 6161 y53: out std_logic_vector((N-1) downto 0); 6162 y54: out std_logic_vector((N-1) downto 0); 6163 y55: out std_logic_vector((N-1) downto 0); 6164 y56: out std_logic_vector((N-1) downto 0); 6165 y57: out std_logic_vector((N-1) downto 0); 6166 y58: out std_logic_vector((N-1) downto 0); 6167 y59: out std_logic_vector((N-1) downto 0); 6168 y60: out std_logic_vector((N-1) downto 0); 6169 y61: out std_logic_vector((N-1) downto 0); 6170 y62: out std_logic_vector((N-1) downto 0); 6171 y63: out std_logic_vector((N-1) downto 0); 6172 y64: out std_logic_vector((N-1) downto 0); 6173 y65: out std_logic_vector((N-1) downto 0); 6174 y66: out std_logic_vector((N-1) downto 0); 6175 y67: out std_logic_vector((N-1) downto 0); 6176 y68: out std_logic_vector((N-1) downto 0); 6177 y69: out std_logic_vector((N-1) downto 0); 6178 y70: out std_logic_vector((N-1) downto 0); 6179 y71: out std_logic_vector((N-1) downto 0); 6180 y72: out std_logic_vector((N-1) downto 0); 6181 y73: out std_logic_vector((N-1) downto 0); 6182 y74: out std_logic_vector((N-1) downto 0); 6183 y75: out std_logic_vector((N-1) downto 0); 6184 y76: out std_logic_vector((N-1) downto 0); 6185 y77: out std_logic_vector((N-1) downto 0); 6186 y78: out std_logic_vector((N-1) downto 0); 6187 y79: out std_logic_vector((N-1) downto 0); 6188 y80: out std_logic_vector((N-1) downto 0); 6189 y81: out std_logic_vector((N-1) downto 0); 6190 y82: out std_logic_vector((N-1) downto 0); 6191 y83: out std_logic_vector((N-1) downto 0); 6192 y84: out std_logic_vector((N-1) downto 0); 6193 y85: out std_logic_vector((N-1) downto 0); 6194 y86: out std_logic_vector((N-1) downto 0); 6195 y87: out std_logic_vector((N-1) downto 0); 6196 y88: out std_logic_vector((N-1) downto 0); 6197 y89: out std_logic_vector((N-1) downto 0); 6198 y90: out std_logic_vector((N-1) downto 0); 6199 y91: out std_logic_vector((N-1) downto 0); 6200 y92: out std_logic_vector((N-1) downto 0); 6201 y93: out std_logic_vector((N-1) downto 0); 6202 y94: out std_logic_vector((N-1) downto 0); 6203 y95: out std_logic_vector((N-1) downto 0); 6204 y96: out std_logic_vector((N-1) downto 0); 6205 y97: out std_logic_vector((N-1) downto 0); 6206 y98: out std_logic_vector((N-1) downto 0); 6207 y99: out std_logic_vector((N-1) downto 0); 6208 y100: out std_logic_vector((N-1) downto 0); 6209 y101: out std_logic_vector((N-1) downto 0); 6210 y102: out std_logic_vector((N-1) downto 0); 6211 y103: out std_logic_vector((N-1) downto 0); 6212 y104: out std_logic_vector((N-1) downto 0); 6213 y105: out std_logic_vector((N-1) downto 0); 6214 y106: out std_logic_vector((N-1) downto 0); 6215 y107: out std_logic_vector((N-1) downto 0); 6216 y108: out std_logic_vector((N-1) downto 0); 6217 y109: out std_logic_vector((N-1) downto 0); 6218 y110: out std_logic_vector((N-1) downto 0); 6219 y111: out std_logic_vector((N-1) downto 0); 6220 y112: out std_logic_vector((N-1) downto 0); 6221 y113: out std_logic_vector((N-1) downto 0); 6222 y114: out std_logic_vector((N-1) downto 0); 6223 y115: out std_logic_vector((N-1) downto 0); 6224 y116: out std_logic_vector((N-1) downto 0); 6225 y117: out std_logic_vector((N-1) downto 0); 6226 y118: out std_logic_vector((N-1) downto 0); 6227 y119: out std_logic_vector((N-1) downto 0); 6228 y120: out std_logic_vector((N-1) downto 0); 6229 y121: out std_logic_vector((N-1) downto 0); 6230 y122: out std_logic_vector((N-1) downto 0); 6231 y123: out std_logic_vector((N-1) downto 0); 6232 y124: out std_logic_vector((N-1) downto 0); 6233 y125: out std_logic_vector((N-1) downto 0); 6234 y126: out std_logic_vector((N-1) downto 0); 6235 y127: out std_logic_vector((N-1) downto 0); 6236 y128: out std_logic_vector((N-1) downto 0); 6237 y129: out std_logic_vector((N-1) downto 0); 6238 y130: out std_logic_vector((N-1) downto 0); 6239 y131: out std_logic_vector((N-1) downto 0); 6240 y132: out std_logic_vector((N-1) downto 0); 6241 y133: out std_logic_vector((N-1) downto 0); 6242 y134: out std_logic_vector((N-1) downto 0); 6243 y135: out std_logic_vector((N-1) downto 0); 6244 y136: out std_logic_vector((N-1) downto 0); 6245 y137: out std_logic_vector((N-1) downto 0); 6246 y138: out std_logic_vector((N-1) downto 0); 6247 y139: out std_logic_vector((N-1) downto 0); 6248 y140: out std_logic_vector((N-1) downto 0); 6249 y141: out std_logic_vector((N-1) downto 0); 6250 y142: out std_logic_vector((N-1) downto 0); 6251 y143: out std_logic_vector((N-1) downto 0); 6252 y144: out std_logic_vector((N-1) downto 0); 6253 y145: out std_logic_vector((N-1) downto 0); 6254 y146: out std_logic_vector((N-1) downto 0); 6255 y147: out std_logic_vector((N-1) downto 0); 6256 y148: out std_logic_vector((N-1) downto 0); 6257 y149: out std_logic_vector((N-1) downto 0); 6258 y150: out std_logic_vector((N-1) downto 0); 6259 y151: out std_logic_vector((N-1) downto 0); 6260 y152: out std_logic_vector((N-1) downto 0); 6261 y153: out std_logic_vector((N-1) downto 0); 6262 y154: out std_logic_vector((N-1) downto 0); 6263 y155: out std_logic_vector((N-1) downto 0); 6264 y156: out std_logic_vector((N-1) downto 0); 6265 y157: out std_logic_vector((N-1) downto 0); 6266 y158: out std_logic_vector((N-1) downto 0); 6267 y159: out std_logic_vector((N-1) downto 0); 6268 y160: out std_logic_vector((N-1) downto 0); 6269 y161: out std_logic_vector((N-1) downto 0); 6270 y162: out std_logic_vector((N-1) downto 0); 6271 y163: out std_logic_vector((N-1) downto 0); 6272 y164: out std_logic_vector((N-1) downto 0); 6273 y165: out std_logic_vector((N-1) downto 0); 6274 y166: out std_logic_vector((N-1) downto 0); 6275 y167: out std_logic_vector((N-1) downto 0); 6276 y168: out std_logic_vector((N-1) downto 0); 6277 y169: out std_logic_vector((N-1) downto 0); 6278 y170: out std_logic_vector((N-1) downto 0); 6279 y171: out std_logic_vector((N-1) downto 0); 6280 y172: out std_logic_vector((N-1) downto 0); 6281 y173: out std_logic_vector((N-1) downto 0); 6282 y174: out std_logic_vector((N-1) downto 0); 6283 y175: out std_logic_vector((N-1) downto 0); 6284 y176: out std_logic_vector((N-1) downto 0); 6285 y177: out std_logic_vector((N-1) downto 0); 6286 y178: out std_logic_vector((N-1) downto 0); 6287 y179: out std_logic_vector((N-1) downto 0); 6288 y180: out std_logic_vector((N-1) downto 0); 6289 y181: out std_logic_vector((N-1) downto 0); 6290 y182: out std_logic_vector((N-1) downto 0); 6291 y183: out std_logic_vector((N-1) downto 0); 6292 y184: out std_logic_vector((N-1) downto 0); 6293 y185: out std_logic_vector((N-1) downto 0); 6294 y186: out std_logic_vector((N-1) downto 0); 6295 y187: out std_logic_vector((N-1) downto 0); 6296 y188: out std_logic_vector((N-1) downto 0); 6297 y189: out std_logic_vector((N-1) downto 0); 6298 y190: out std_logic_vector((N-1) downto 0); 6299 y191: out std_logic_vector((N-1) downto 0); 6300 y192: out std_logic_vector((N-1) downto 0); 6301 y193: out std_logic_vector((N-1) downto 0); 6302 y194: out std_logic_vector((N-1) downto 0); 6303 y195: out std_logic_vector((N-1) downto 0); 6304 y196: out std_logic_vector((N-1) downto 0); 6305 y197: out std_logic_vector((N-1) downto 0); 6306 y198: out std_logic_vector((N-1) downto 0); 6307 y199: out std_logic_vector((N-1) downto 0); 6308 y200: out std_logic_vector((N-1) downto 0); 6309 y201: out std_logic_vector((N-1) downto 0); 6310 y202: out std_logic_vector((N-1) downto 0); 6311 y203: out std_logic_vector((N-1) downto 0); 6312 y204: out std_logic_vector((N-1) downto 0); 6313 y205: out std_logic_vector((N-1) downto 0); 6314 y206: out std_logic_vector((N-1) downto 0); 6315 y207: out std_logic_vector((N-1) downto 0); 6316 y208: out std_logic_vector((N-1) downto 0); 6317 y209: out std_logic_vector((N-1) downto 0); 6318 y210: out std_logic_vector((N-1) downto 0); 6319 y211: out std_logic_vector((N-1) downto 0); 6320 y212: out std_logic_vector((N-1) downto 0); 6321 y213: out std_logic_vector((N-1) downto 0); 6322 y214: out std_logic_vector((N-1) downto 0); 6323 y215: out std_logic_vector((N-1) downto 0); 6324 y216: out std_logic_vector((N-1) downto 0); 6325 y217: out std_logic_vector((N-1) downto 0); 6326 y218: out std_logic_vector((N-1) downto 0); 6327 y219: out std_logic_vector((N-1) downto 0); 6328 y220: out std_logic_vector((N-1) downto 0); 6329 y221: out std_logic_vector((N-1) downto 0); 6330 y222: out std_logic_vector((N-1) downto 0); 6331 y223: out std_logic_vector((N-1) downto 0); 6332 y224: out std_logic_vector((N-1) downto 0); 6333 y225: out std_logic_vector((N-1) downto 0); 6334 y226: out std_logic_vector((N-1) downto 0); 6335 y227: out std_logic_vector((N-1) downto 0); 6336 y228: out std_logic_vector((N-1) downto 0); 6337 y229: out std_logic_vector((N-1) downto 0); 6338 y230: out std_logic_vector((N-1) downto 0); 6339 y231: out std_logic_vector((N-1) downto 0); 6340 y232: out std_logic_vector((N-1) downto 0); 6341 y233: out std_logic_vector((N-1) downto 0); 6342 y234: out std_logic_vector((N-1) downto 0); 6343 y235: out std_logic_vector((N-1) downto 0); 6344 y236: out std_logic_vector((N-1) downto 0); 6345 y237: out std_logic_vector((N-1) downto 0); 6346 y238: out std_logic_vector((N-1) downto 0); 6347 y239: out std_logic_vector((N-1) downto 0); 6348 y240: out std_logic_vector((N-1) downto 0); 6349 y241: out std_logic_vector((N-1) downto 0); 6350 y242: out std_logic_vector((N-1) downto 0); 6351 y243: out std_logic_vector((N-1) downto 0); 6352 y244: out std_logic_vector((N-1) downto 0); 6353 y245: out std_logic_vector((N-1) downto 0); 6354 y246: out std_logic_vector((N-1) downto 0); 6355 y247: out std_logic_vector((N-1) downto 0); 6356 y248: out std_logic_vector((N-1) downto 0); 6357 y249: out std_logic_vector((N-1) downto 0); 6358 y250: out std_logic_vector((N-1) downto 0); 6359 y251: out std_logic_vector((N-1) downto 0); 6360 y252: out std_logic_vector((N-1) downto 0); 6361 y253: out std_logic_vector((N-1) downto 0); 6362 y254: out std_logic_vector((N-1) downto 0); 6363 y255: out std_logic_vector((N-1) downto 0); 6364 address: in std_logic_vector(7 downto 0) 6365); 6366end; 6367 6368architecture struct_decoderNx256 of decoderNx256 is 6369component decoder1x256 is 6370port( 6371 data: in std_logic; 6372 y0: out std_logic; 6373 y1: out std_logic; 6374 y2: out std_logic; 6375 y3: out std_logic; 6376 y4: out std_logic; 6377 y5: out std_logic; 6378 y6: out std_logic; 6379 y7: out std_logic; 6380 y8: out std_logic; 6381 y9: out std_logic; 6382 y10: out std_logic; 6383 y11: out std_logic; 6384 y12: out std_logic; 6385 y13: out std_logic; 6386 y14: out std_logic; 6387 y15: out std_logic; 6388 y16: out std_logic; 6389 y17: out std_logic; 6390 y18: out std_logic; 6391 y19: out std_logic; 6392 y20: out std_logic; 6393 y21: out std_logic; 6394 y22: out std_logic; 6395 y23: out std_logic; 6396 y24: out std_logic; 6397 y25: out std_logic; 6398 y26: out std_logic; 6399 y27: out std_logic; 6400 y28: out std_logic; 6401 y29: out std_logic; 6402 y30: out std_logic; 6403 y31: out std_logic; 6404 y32: out std_logic; 6405 y33: out std_logic; 6406 y34: out std_logic; 6407 y35: out std_logic; 6408 y36: out std_logic; 6409 y37: out std_logic; 6410 y38: out std_logic; 6411 y39: out std_logic; 6412 y40: out std_logic; 6413 y41: out std_logic; 6414 y42: out std_logic; 6415 y43: out std_logic; 6416 y44: out std_logic; 6417 y45: out std_logic; 6418 y46: out std_logic; 6419 y47: out std_logic; 6420 y48: out std_logic; 6421 y49: out std_logic; 6422 y50: out std_logic; 6423 y51: out std_logic; 6424 y52: out std_logic; 6425 y53: out std_logic; 6426 y54: out std_logic; 6427 y55: out std_logic; 6428 y56: out std_logic; 6429 y57: out std_logic; 6430 y58: out std_logic; 6431 y59: out std_logic; 6432 y60: out std_logic; 6433 y61: out std_logic; 6434 y62: out std_logic; 6435 y63: out std_logic; 6436 y64: out std_logic; 6437 y65: out std_logic; 6438 y66: out std_logic; 6439 y67: out std_logic; 6440 y68: out std_logic; 6441 y69: out std_logic; 6442 y70: out std_logic; 6443 y71: out std_logic; 6444 y72: out std_logic; 6445 y73: out std_logic; 6446 y74: out std_logic; 6447 y75: out std_logic; 6448 y76: out std_logic; 6449 y77: out std_logic; 6450 y78: out std_logic; 6451 y79: out std_logic; 6452 y80: out std_logic; 6453 y81: out std_logic; 6454 y82: out std_logic; 6455 y83: out std_logic; 6456 y84: out std_logic; 6457 y85: out std_logic; 6458 y86: out std_logic; 6459 y87: out std_logic; 6460 y88: out std_logic; 6461 y89: out std_logic; 6462 y90: out std_logic; 6463 y91: out std_logic; 6464 y92: out std_logic; 6465 y93: out std_logic; 6466 y94: out std_logic; 6467 y95: out std_logic; 6468 y96: out std_logic; 6469 y97: out std_logic; 6470 y98: out std_logic; 6471 y99: out std_logic; 6472 y100: out std_logic; 6473 y101: out std_logic; 6474 y102: out std_logic; 6475 y103: out std_logic; 6476 y104: out std_logic; 6477 y105: out std_logic; 6478 y106: out std_logic; 6479 y107: out std_logic; 6480 y108: out std_logic; 6481 y109: out std_logic; 6482 y110: out std_logic; 6483 y111: out std_logic; 6484 y112: out std_logic; 6485 y113: out std_logic; 6486 y114: out std_logic; 6487 y115: out std_logic; 6488 y116: out std_logic; 6489 y117: out std_logic; 6490 y118: out std_logic; 6491 y119: out std_logic; 6492 y120: out std_logic; 6493 y121: out std_logic; 6494 y122: out std_logic; 6495 y123: out std_logic; 6496 y124: out std_logic; 6497 y125: out std_logic; 6498 y126: out std_logic; 6499 y127: out std_logic; 6500 y128: out std_logic; 6501 y129: out std_logic; 6502 y130: out std_logic; 6503 y131: out std_logic; 6504 y132: out std_logic; 6505 y133: out std_logic; 6506 y134: out std_logic; 6507 y135: out std_logic; 6508 y136: out std_logic; 6509 y137: out std_logic; 6510 y138: out std_logic; 6511 y139: out std_logic; 6512 y140: out std_logic; 6513 y141: out std_logic; 6514 y142: out std_logic; 6515 y143: out std_logic; 6516 y144: out std_logic; 6517 y145: out std_logic; 6518 y146: out std_logic; 6519 y147: out std_logic; 6520 y148: out std_logic; 6521 y149: out std_logic; 6522 y150: out std_logic; 6523 y151: out std_logic; 6524 y152: out std_logic; 6525 y153: out std_logic; 6526 y154: out std_logic; 6527 y155: out std_logic; 6528 y156: out std_logic; 6529 y157: out std_logic; 6530 y158: out std_logic; 6531 y159: out std_logic; 6532 y160: out std_logic; 6533 y161: out std_logic; 6534 y162: out std_logic; 6535 y163: out std_logic; 6536 y164: out std_logic; 6537 y165: out std_logic; 6538 y166: out std_logic; 6539 y167: out std_logic; 6540 y168: out std_logic; 6541 y169: out std_logic; 6542 y170: out std_logic; 6543 y171: out std_logic; 6544 y172: out std_logic; 6545 y173: out std_logic; 6546 y174: out std_logic; 6547 y175: out std_logic; 6548 y176: out std_logic; 6549 y177: out std_logic; 6550 y178: out std_logic; 6551 y179: out std_logic; 6552 y180: out std_logic; 6553 y181: out std_logic; 6554 y182: out std_logic; 6555 y183: out std_logic; 6556 y184: out std_logic; 6557 y185: out std_logic; 6558 y186: out std_logic; 6559 y187: out std_logic; 6560 y188: out std_logic; 6561 y189: out std_logic; 6562 y190: out std_logic; 6563 y191: out std_logic; 6564 y192: out std_logic; 6565 y193: out std_logic; 6566 y194: out std_logic; 6567 y195: out std_logic; 6568 y196: out std_logic; 6569 y197: out std_logic; 6570 y198: out std_logic; 6571 y199: out std_logic; 6572 y200: out std_logic; 6573 y201: out std_logic; 6574 y202: out std_logic; 6575 y203: out std_logic; 6576 y204: out std_logic; 6577 y205: out std_logic; 6578 y206: out std_logic; 6579 y207: out std_logic; 6580 y208: out std_logic; 6581 y209: out std_logic; 6582 y210: out std_logic; 6583 y211: out std_logic; 6584 y212: out std_logic; 6585 y213: out std_logic; 6586 y214: out std_logic; 6587 y215: out std_logic; 6588 y216: out std_logic; 6589 y217: out std_logic; 6590 y218: out std_logic; 6591 y219: out std_logic; 6592 y220: out std_logic; 6593 y221: out std_logic; 6594 y222: out std_logic; 6595 y223: out std_logic; 6596 y224: out std_logic; 6597 y225: out std_logic; 6598 y226: out std_logic; 6599 y227: out std_logic; 6600 y228: out std_logic; 6601 y229: out std_logic; 6602 y230: out std_logic; 6603 y231: out std_logic; 6604 y232: out std_logic; 6605 y233: out std_logic; 6606 y234: out std_logic; 6607 y235: out std_logic; 6608 y236: out std_logic; 6609 y237: out std_logic; 6610 y238: out std_logic; 6611 y239: out std_logic; 6612 y240: out std_logic; 6613 y241: out std_logic; 6614 y242: out std_logic; 6615 y243: out std_logic; 6616 y244: out std_logic; 6617 y245: out std_logic; 6618 y246: out std_logic; 6619 y247: out std_logic; 6620 y248: out std_logic; 6621 y249: out std_logic; 6622 y250: out std_logic; 6623 y251: out std_logic; 6624 y252: out std_logic; 6625 y253: out std_logic; 6626 y254: out std_logic; 6627 y255: out std_logic; 6628 address: in std_logic_vector(7 downto 0) 6629); 6630 6631end component; 6632 6633begin 6634 u1: for i in (N-1) downto 0 generate 6635 u: decoder1x256 port map( 6636 data => data(i), 6637 y0 => y0(i), 6638 y1 => y1(i), 6639 y2 => y2(i), 6640 y3 => y3(i), 6641 y4 => y4(i), 6642 y5 => y5(i), 6643 y6 => y6(i), 6644 y7 => y7(i), 6645 y8 => y8(i), 6646 y9 => y9(i), 6647 y10 => y10(i), 6648 y11 => y11(i), 6649 y12 => y12(i), 6650 y13 => y13(i), 6651 y14 => y14(i), 6652 y15 => y15(i), 6653 y16 => y16(i), 6654 y17 => y17(i), 6655 y18 => y18(i), 6656 y19 => y19(i), 6657 y20 => y20(i), 6658 y21 => y21(i), 6659 y22 => y22(i), 6660 y23 => y23(i), 6661 y24 => y24(i), 6662 y25 => y25(i), 6663 y26 => y26(i), 6664 y27 => y27(i), 6665 y28 => y28(i), 6666 y29 => y29(i), 6667 y30 => y30(i), 6668 y31 => y31(i), 6669 y32 => y32(i), 6670 y33 => y33(i), 6671 y34 => y34(i), 6672 y35 => y35(i), 6673 y36 => y36(i), 6674 y37 => y37(i), 6675 y38 => y38(i), 6676 y39 => y39(i), 6677 y40 => y40(i), 6678 y41 => y41(i), 6679 y42 => y42(i), 6680 y43 => y43(i), 6681 y44 => y44(i), 6682 y45 => y45(i), 6683 y46 => y46(i), 6684 y47 => y47(i), 6685 y48 => y48(i), 6686 y49 => y49(i), 6687 y50 => y50(i), 6688 y51 => y51(i), 6689 y52 => y52(i), 6690 y53 => y53(i), 6691 y54 => y54(i), 6692 y55 => y55(i), 6693 y56 => y56(i), 6694 y57 => y57(i), 6695 y58 => y58(i), 6696 y59 => y59(i), 6697 y60 => y60(i), 6698 y61 => y61(i), 6699 y62 => y62(i), 6700 y63 => y63(i), 6701 y64 => y64(i), 6702 y65 => y65(i), 6703 y66 => y66(i), 6704 y67 => y67(i), 6705 y68 => y68(i), 6706 y69 => y69(i), 6707 y70 => y70(i), 6708 y71 => y71(i), 6709 y72 => y72(i), 6710 y73 => y73(i), 6711 y74 => y74(i), 6712 y75 => y75(i), 6713 y76 => y76(i), 6714 y77 => y77(i), 6715 y78 => y78(i), 6716 y79 => y79(i), 6717 y80 => y80(i), 6718 y81 => y81(i), 6719 y82 => y82(i), 6720 y83 => y83(i), 6721 y84 => y84(i), 6722 y85 => y85(i), 6723 y86 => y86(i), 6724 y87 => y87(i), 6725 y88 => y88(i), 6726 y89 => y89(i), 6727 y90 => y90(i), 6728 y91 => y91(i), 6729 y92 => y92(i), 6730 y93 => y93(i), 6731 y94 => y94(i), 6732 y95 => y95(i), 6733 y96 => y96(i), 6734 y97 => y97(i), 6735 y98 => y98(i), 6736 y99 => y99(i), 6737 y100 => y100(i), 6738 y101 => y101(i), 6739 y102 => y102(i), 6740 y103 => y103(i), 6741 y104 => y104(i), 6742 y105 => y105(i), 6743 y106 => y106(i), 6744 y107 => y107(i), 6745 y108 => y108(i), 6746 y109 => y109(i), 6747 y110 => y110(i), 6748 y111 => y111(i), 6749 y112 => y112(i), 6750 y113 => y113(i), 6751 y114 => y114(i), 6752 y115 => y115(i), 6753 y116 => y116(i), 6754 y117 => y117(i), 6755 y118 => y118(i), 6756 y119 => y119(i), 6757 y120 => y120(i), 6758 y121 => y121(i), 6759 y122 => y122(i), 6760 y123 => y123(i), 6761 y124 => y124(i), 6762 y125 => y125(i), 6763 y126 => y126(i), 6764 y127 => y127(i), 6765 y128 => y128(i), 6766 y129 => y129(i), 6767 y130 => y130(i), 6768 y131 => y131(i), 6769 y132 => y132(i), 6770 y133 => y133(i), 6771 y134 => y134(i), 6772 y135 => y135(i), 6773 y136 => y136(i), 6774 y137 => y137(i), 6775 y138 => y138(i), 6776 y139 => y139(i), 6777 y140 => y140(i), 6778 y141 => y141(i), 6779 y142 => y142(i), 6780 y143 => y143(i), 6781 y144 => y144(i), 6782 y145 => y145(i), 6783 y146 => y146(i), 6784 y147 => y147(i), 6785 y148 => y148(i), 6786 y149 => y149(i), 6787 y150 => y150(i), 6788 y151 => y151(i), 6789 y152 => y152(i), 6790 y153 => y153(i), 6791 y154 => y154(i), 6792 y155 => y155(i), 6793 y156 => y156(i), 6794 y157 => y157(i), 6795 y158 => y158(i), 6796 y159 => y159(i), 6797 y160 => y160(i), 6798 y161 => y161(i), 6799 y162 => y162(i), 6800 y163 => y163(i), 6801 y164 => y164(i), 6802 y165 => y165(i), 6803 y166 => y166(i), 6804 y167 => y167(i), 6805 y168 => y168(i), 6806 y169 => y169(i), 6807 y170 => y170(i), 6808 y171 => y171(i), 6809 y172 => y172(i), 6810 y173 => y173(i), 6811 y174 => y174(i), 6812 y175 => y175(i), 6813 y176 => y176(i), 6814 y177 => y177(i), 6815 y178 => y178(i), 6816 y179 => y179(i), 6817 y180 => y180(i), 6818 y181 => y181(i), 6819 y182 => y182(i), 6820 y183 => y183(i), 6821 y184 => y184(i), 6822 y185 => y185(i), 6823 y186 => y186(i), 6824 y187 => y187(i), 6825 y188 => y188(i), 6826 y189 => y189(i), 6827 y190 => y190(i), 6828 y191 => y191(i), 6829 y192 => y192(i), 6830 y193 => y193(i), 6831 y194 => y194(i), 6832 y195 => y195(i), 6833 y196 => y196(i), 6834 y197 => y197(i), 6835 y198 => y198(i), 6836 y199 => y199(i), 6837 y200 => y200(i), 6838 y201 => y201(i), 6839 y202 => y202(i), 6840 y203 => y203(i), 6841 y204 => y204(i), 6842 y205 => y205(i), 6843 y206 => y206(i), 6844 y207 => y207(i), 6845 y208 => y208(i), 6846 y209 => y209(i), 6847 y210 => y210(i), 6848 y211 => y211(i), 6849 y212 => y212(i), 6850 y213 => y213(i), 6851 y214 => y214(i), 6852 y215 => y215(i), 6853 y216 => y216(i), 6854 y217 => y217(i), 6855 y218 => y218(i), 6856 y219 => y219(i), 6857 y220 => y220(i), 6858 y221 => y221(i), 6859 y222 => y222(i), 6860 y223 => y223(i), 6861 y224 => y224(i), 6862 y225 => y225(i), 6863 y226 => y226(i), 6864 y227 => y227(i), 6865 y228 => y228(i), 6866 y229 => y229(i), 6867 y230 => y230(i), 6868 y231 => y231(i), 6869 y232 => y232(i), 6870 y233 => y233(i), 6871 y234 => y234(i), 6872 y235 => y235(i), 6873 y236 => y236(i), 6874 y237 => y237(i), 6875 y238 => y238(i), 6876 y239 => y239(i), 6877 y240 => y240(i), 6878 y241 => y241(i), 6879 y242 => y242(i), 6880 y243 => y243(i), 6881 y244 => y244(i), 6882 y245 => y245(i), 6883 y246 => y246(i), 6884 y247 => y247(i), 6885 y248 => y248(i), 6886 y249 => y249(i), 6887 y250 => y250(i), 6888 y251 => y251(i), 6889 y252 => y252(i), 6890 y253 => y253(i), 6891 y254 => y254(i), 6892 y255 => y255(i), 6893 address => address 6894 ); 6895 end generate u1; 6896end; 6897 6898library ieee; 6899use ieee.std_logic_1164.all; 6900 6901entity counterN is 6902generic( 6903 N: positive 6904); 6905port( 6906 clock: in std_logic; 6907 carry_in: in std_logic; 6908 clock_enable: in std_logic; 6909 resetn: in std_logic; 6910 output: out std_logic_vector((N-1) downto 0); 6911 carry_out: out std_logic 6912); 6913end; 6914 6915architecture struct_counterN of counterN is 6916component incrementerN is 6917generic( 6918 N: positive 6919); 6920port( 6921 input: in std_logic_vector((N-1) downto 0); 6922 carry_in: in std_logic; 6923 sum: out std_logic_vector((N-1) downto 0); 6924 carry_out: out std_logic 6925); 6926end component; 6927 6928component andNbit is 6929generic( 6930 N: positive 6931); 6932port( 6933 input: in std_logic_vector((N-1) downto 0); 6934 y: out std_logic 6935); 6936end component; 6937 6938component synchronous_latchN is 6939generic( 6940 N: positive 6941); 6942port( 6943 rstn: in std_logic; 6944 clock: in std_logic; 6945 clock_enable: in std_logic; 6946 d: in std_logic_vector((N-1) downto 0); 6947 q: out std_logic_vector((N-1) downto 0) 6948); 6949end component; 6950 6951signal counter_out: std_logic_vector(N downto 0); 6952 6953signal incrementer_out: std_logic_vector(N downto 0); 6954 6955signal all_ones: std_logic; 6956 6957begin 6958 u1: incrementerN 6959 generic map( 6960 N => N 6961 ) 6962 port map( 6963 input => counter_out((N-1) downto 0), 6964 carry_in => carry_in, 6965 sum => incrementer_out((N-1) downto 0), 6966 carry_out => incrementer_out(N) 6967 ); 6968 6969 u2: synchronous_latchN 6970 generic map( 6971 N => (N + 1) 6972 ) 6973 port map( 6974 rstn => resetn, 6975 clock => clock, 6976 clock_enable => clock_enable, 6977 d => incrementer_out, 6978 q => counter_out 6979 ); 6980 6981 u3: andNbit 6982 generic map( 6983 N => N 6984 ) 6985 port map( 6986 input => counter_out((N-1) downto 0), 6987 y => all_ones 6988 ); 6989 6990 carry_out <= all_ones and carry_in; 6991 output <= counter_out((N-1) downto 0); 6992end; 6993