1library ieee;
2use ieee.std_logic_1164.all;
3use ieee.numeric_std.all;
4
5
6entity ent is
7end ent;
8
9
10architecture sim of ent is
11
12  signal s_clk  : std_logic := '1';
13  signal s_test : std_logic := '0';
14
15begin
16
17  s_clk <= not s_clk after 5 ns;
18  s_test <= '1' after 30 ns,
19            '0' after 40 ns;
20
21  process is
22  begin
23    wait until rising_edge(s_clk);
24    -- This works
25    if s_test'stable(10 ns) then
26      report "s_test stable";
27    else
28      report "s_test changed";
29    end if;
30  end process;
31
32  -- This works
33  -- psl assert always (s_test'stable)@rising_edge(s_clk);
34
35  -- This leads to an compile error
36  -- psl assert always (s_test'stable(10 ns))@rising_edge(s_clk);
37
38end architecture sim;
39