1library ieee;
2use ieee.std_logic_1164.all;
3
4entity recv is
5  port (
6    rst : std_logic;
7    clk : std_logic;
8    rx : std_logic;
9    byte : out std_logic_vector (7 downto 0);
10    b_err : out std_logic;
11    b_en : out std_logic);
12end recv;
13
14architecture behav of recv
15is
16    type state_t is
17         (s_wait, s0, s1, s2, s3, s4, s5, s6, s7, s_parity, s_stop);
18    signal state: state_t;
19    signal parity: std_logic;
20    signal err : std_logic;
21    signal en : std_logic;
22begin
23  process (clk) is
24  begin
25    if rising_edge(clk) then
26      if rst = '1' then
27        state <= s_wait;
28        err <= '0';
29        en <= '0';
30      else
31        en <= '0';
32        case state is
33          when s_wait =>
34            if rx = '0' then
35              state <= s0;
36              err <= '0';
37              parity <= '0';
38            end if;
39          when s0 =>
40            byte (0) <= rx;
41            parity <= parity xor rx;
42            state <= s1;
43          when s1 =>
44            byte (1) <= rx;
45            parity <= parity xor rx;
46            state <= s2;
47          when s2 =>
48            byte (2) <= rx;
49            parity <= parity xor rx;
50            state <= s3;
51          when s3 =>
52            byte (3) <= rx;
53            parity <= parity xor rx;
54            state <= s4;
55          when s4 =>
56            byte (4) <= rx;
57            parity <= parity xor rx;
58            state <= s5;
59          when s5 =>
60            byte (5) <= rx;
61            parity <= parity xor rx;
62            state <= s6;
63          when s6 =>
64            byte (6) <= rx;
65            parity <= parity xor rx;
66            state <= s7;
67          when s7 =>
68            byte (7) <= rx;
69            parity <= parity xor rx;
70            state <= s_parity;
71          when s_parity =>
72            if rx /= parity then
73              err <= '1';
74            end if;
75            state <= s_stop;
76          when s_stop =>
77            if rx /= '1' then
78              err <= '1';
79            end if;
80            en <= '1';
81            state <= s_wait;
82        end case;
83      end if;
84    end if;
85  end process;
86
87    b_en <= en;
88    b_err <= err;
89
90    --psl default clock is rising_edge(clk);
91    --psl restrict {rst;(not rst)[*]};
92
93    assert rst = '1' or err /= '1' report "parity error" severity error;
94end behav;
95