1--
2-- Dual-Port Block RAM with Two Write Ports
3-- Modelization with a protected shared variable
4-- Simulates without warning in VHDL-2002 simulators
5--
6-- Download: ftp://ftp.xilinx.com/pub/documentation/misc/xstug_examples.zip
7-- File: HDL_Coding_Techniques/rams/ram_protected_sharedvar.vhd
8--
9library ieee;
10use ieee.std_logic_1164.all;
11use ieee.std_logic_unsigned.all;
12
13package ram_pkg is
14
15  subtype data_type is std_logic_vector(15 downto 0);
16
17  type ram_type is protected
18
19    procedure write (
20      addr : std_logic_vector(6 downto 0);
21      data : data_type);
22
23    impure function read (
24      addr : std_logic_vector(6 downto 0))
25      return data_type;
26
27  end protected ram_type;
28
29end ram_pkg;
30
31
32package body ram_pkg is
33
34  type ram_array is array(0 to 127) of data_type;
35
36  type ram_type is protected body
37
38    variable ram : ram_array;
39
40    procedure write (
41      addr : std_logic_vector(6 downto 0);
42      data : data_type) is
43    begin
44      ram(conv_integer(addr)) := data;
45    end procedure write;
46
47    impure function read (
48      addr : std_logic_vector(6 downto 0))
49      return data_type is
50    begin
51      return ram(conv_integer(addr));
52    end function read;
53
54  end protected body ram_type;
55
56end ram_pkg;
57
58
59library ieee;
60use ieee.std_logic_1164.all;
61use ieee.std_logic_unsigned.all;
62
63library work;
64use work.ram_pkg.all;
65
66
67entity ram_protected_sharedvar is
68
69  generic (
70    DATA_WIDTH : integer := 16;
71    ADDR_WIDTH : integer := 7
72  );
73  port(
74    clka  : in  std_logic;
75    clkb  : in  std_logic;
76    ena   : in  std_logic;
77    enb   : in  std_logic;
78    wea   : in  std_logic;
79    web   : in  std_logic;
80    addra : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
81    addrb : in  std_logic_vector(ADDR_WIDTH-1 downto 0);
82    dia   : in  std_logic_vector(DATA_WIDTH-1 downto 0);
83    dib   : in  std_logic_vector(DATA_WIDTH-1 downto 0);
84    doa   : out std_logic_vector(DATA_WIDTH-1 downto 0);
85    dob   : out std_logic_vector(DATA_WIDTH-1 downto 0));
86
87end ram_protected_sharedvar;
88
89architecture behavioral of ram_protected_sharedvar is
90
91    shared variable RAM : ram_type;
92
93begin
94
95    process (CLKA)
96    begin
97        if rising_edge(clka) then
98            if ENA = '1' then
99                doa <= RAM.read(addra);
100                if WEA = '1' then
101                  RAM.write(addra, dia);
102                end if;
103            end if;
104        end if;
105    end process;
106
107    process (CLKB)
108    begin
109        if rising_edge(clkb) then
110            if ENB = '1' then
111                dob <= RAM.read(addrb);
112                if WEB = '1' then
113                  RAM.write(addrb, dib);
114                end if;
115            end if;
116        end if;
117    end process;
118
119end behavioral;
120