1library ieee; 2use ieee.std_logic_1164.all; 3 4entity adds is 5 port ( 6 li : integer; 7 ri : integer; 8 l4 : std_logic_vector (3 downto 0); 9 r3 : std_logic_vector (2 downto 0); 10 11 add_u4u3u : out std_logic_vector (3 downto 0); 12 add_s4s3s : out std_logic_vector (3 downto 0); 13 add_u4s3s : out std_logic_vector (4 downto 0); 14 add_s4u3s : out std_logic_vector (3 downto 0); 15 add_u4iu : out std_logic_vector (3 downto 0); 16 add_iu3u : out std_logic_vector (2 downto 0); 17 add_s4is : out std_logic_vector (3 downto 0); 18 add_is3s : out std_logic_vector (2 downto 0); 19 add_u4lu : out std_logic_vector (3 downto 0); 20 add_lu3u : out std_logic_vector (2 downto 0); 21 add_s4ls : out std_logic_vector (3 downto 0); 22 add_ls3s : out std_logic_vector (2 downto 0); 23 24 add_u4u3v : out std_logic_vector (3 downto 0); 25 add_s4s3v : out std_logic_vector (3 downto 0); 26 add_u4s3v : out std_logic_vector (4 downto 0); 27 add_s4u3v : out std_logic_vector (3 downto 0); 28 add_u4iv : out std_logic_vector (3 downto 0); 29 add_iu3v : out std_logic_vector (2 downto 0); 30 add_s4iv : out std_logic_vector (3 downto 0); 31 add_is3v : out std_logic_vector (2 downto 0); 32 add_u4lv : out std_logic_vector (3 downto 0); 33 add_lu3v : out std_logic_vector (2 downto 0); 34 add_s4lv : out std_logic_vector (3 downto 0); 35 add_ls3v : out std_logic_vector (2 downto 0)); 36end adds; 37 38library ieee; 39use ieee.std_logic_arith.all; 40 41architecture behav of adds is 42begin 43 add_u4u3u <= std_logic_vector (unsigned'(unsigned(l4) + unsigned(r3))); 44 add_s4s3s <= std_logic_vector (signed'(signed(l4) + signed(r3))); 45 add_u4s3s <= std_logic_vector (signed'(unsigned(l4) + signed(r3))); 46 add_s4u3s <= std_logic_vector (signed'(signed(l4) + unsigned(r3))); 47 add_u4iu <= std_logic_vector (unsigned'(unsigned(l4) + ri)); 48 add_iu3u <= std_logic_vector (unsigned'(li + unsigned(r3))); 49 add_s4is <= std_logic_vector (signed'(signed(l4) + ri)); 50 add_is3s <= std_logic_vector (signed'(li + signed(r3))); 51 add_u4lu <= std_logic_vector (unsigned'(unsigned(l4) + r3(0))); 52 add_lu3u <= std_logic_vector (unsigned'(l4(0) + unsigned(r3))); 53 add_s4ls <= std_logic_vector (signed'(signed(l4) + r3(0))); 54 add_ls3s <= std_logic_vector (signed'(l4(0) + signed(r3))); 55 56 add_u4u3v <= unsigned(l4) + unsigned(r3); 57 add_s4s3v <= signed(l4) + signed(r3); 58 add_u4s3v <= unsigned(l4) + signed(r3); 59 add_s4u3v <= signed(l4) + unsigned(r3); 60 add_u4iv <= unsigned(l4) + ri; 61 add_iu3v <= li + unsigned(r3); 62 add_s4iv <= signed(l4) + ri; 63 add_is3v <= li + signed(r3); 64 add_u4lv <= unsigned(l4) + r3(0); 65 add_lu3v <= l4(0) + unsigned(r3); 66 add_s4lv <= signed(l4) + r3(0); 67 add_ls3v <= l4(0) + signed(r3); 68end behav; 69