1library ieee; 2use ieee.std_logic_1164.all; 3use ieee.std_logic_arith.all; 4 5entity tb_cmpeq is 6end; 7 8architecture behav of tb_cmpeq is 9 signal li : integer := 0; 10 signal ri : integer := 0; 11 signal l4 : std_logic_vector (3 downto 0) := "0000"; 12 signal r3 : std_logic_vector (2 downto 0) := "000"; 13 signal eq_u4u3 : boolean; 14 signal eq_s4s3 : boolean; 15 signal eq_u4s3 : boolean; 16 signal eq_s4u3 : boolean; 17 signal eq_u4i : boolean; 18 signal eq_iu3 : boolean; 19 signal eq_s4i : boolean; 20 signal eq_is3 : boolean; 21begin 22 23 dut: entity work.cmpeq 24 port map ( 25 l4 => l4, 26 r3 => r3, 27 li => li, 28 ri => ri, 29 eq_u4u3 => eq_u4u3, 30 eq_s4s3 => eq_s4s3, 31 eq_u4s3 => eq_u4s3, 32 eq_s4u3 => eq_s4u3, 33 eq_u4i => eq_u4i, 34 eq_iu3 => eq_iu3, 35 eq_s4i => eq_s4i, 36 eq_is3 => eq_is3); 37 38 process 39 begin 40 for i in -8 to 7 loop 41 li <= i; 42 l4 <= conv_std_logic_vector (i, 4); 43 for j in -4 to 3 loop 44 r3 <= conv_std_logic_vector (j, 3); 45 ri <= j; 46 wait for 1 ns; 47 report "u4u3: " & integer'image(i) & " = " & integer'image(j) & " = " 48 & boolean'image(eq_u4u3); 49 report "s4s3: " & integer'image(i) & " = " & integer'image(j) & " = " 50 & boolean'image(eq_s4s3); 51 report "u4s3: " & integer'image(i) & " = " & integer'image(j) & " = " 52 & boolean'image(eq_u4s3); 53 report "s4u3: " & integer'image(i) & " = " & integer'image(j) & " = " 54 & boolean'image(eq_s4u3); 55 report "u4i: " & integer'image(i) & " = " & integer'image(j) & " = " 56 & boolean'image(eq_u4i); 57 report "iu3: " & integer'image(i) & " = " & integer'image(j) & " = " 58 & boolean'image(eq_iu3); 59 report "s4i: " & integer'image(i) & " = " & integer'image(j) & " = " 60 & boolean'image(eq_s4i); 61 report "is3: " & integer'image(i) & " = " & integer'image(j) & " = " 62 & boolean'image(eq_is3); 63 end loop; 64 end loop; 65 wait; 66 end process; 67end behav; 68