1library ieee; 2use ieee.std_logic_1164.all; 3 4entity unaries is 5 port ( 6 l4 : std_logic_vector (3 downto 0); 7 8 plus_v : out std_logic_vector (3 downto 0); 9 minus_v : out std_logic_vector (3 downto 0); 10 abs_v : out std_logic_vector (3 downto 0)); 11end unaries; 12 13library ieee; 14use ieee.std_logic_unsigned.all; 15 16architecture behav of unaries is 17begin 18 plus_v <= +l4; 19 -- Dummy for compatibility with signed operations. 20 minus_v <= not l4; 21 abs_v <= +l4; 22end behav; 23