1 2-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc 3 4-- This file is part of VESTs (Vhdl tESTs). 5 6-- VESTs is free software; you can redistribute it and/or modify it 7-- under the terms of the GNU General Public License as published by the 8-- Free Software Foundation; either version 2 of the License, or (at 9-- your option) any later version. 10 11-- VESTs is distributed in the hope that it will be useful, but WITHOUT 12-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14-- for more details. 15 16-- You should have received a copy of the GNU General Public License 17-- along with VESTs; if not, write to the Free Software Foundation, 18-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 20-- --------------------------------------------------------------------- 21-- 22-- $Id: ch_03_fg_03_07.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $ 23-- $Revision: 1.3 $ 24-- 25-- --------------------------------------------------------------------- 26 27entity SR_flipflop is 28 port ( S, R : in bit; Q : out bit ); 29end entity SR_flipflop; 30 31architecture checking of SR_flipflop is 32begin 33 34 set_reset : process (S, R) is 35 begin 36 assert S = '1' nand R = '1'; 37 if S = '1' then 38 Q <= '1'; 39 end if; 40 if R = '1' then 41 Q <= '0'; 42 end if; 43 end process set_reset; 44 45end architecture checking; 46