1 2-- Copyright (C) 2001 Bill Billowitch. 3 4-- Some of the work to develop this test suite was done with Air Force 5-- support. The Air Force and Bill Billowitch assume no 6-- responsibilities for this software. 7 8-- This file is part of VESTs (Vhdl tESTs). 9 10-- VESTs is free software; you can redistribute it and/or modify it 11-- under the terms of the GNU General Public License as published by the 12-- Free Software Foundation; either version 2 of the License, or (at 13-- your option) any later version. 14 15-- VESTs is distributed in the hope that it will be useful, but WITHOUT 16-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 18-- for more details. 19 20-- You should have received a copy of the GNU General Public License 21-- along with VESTs; if not, write to the Free Software Foundation, 22-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 24-- --------------------------------------------------------------------- 25-- 26-- $Id: tc867.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $ 27-- $Revision: 1.2 $ 28-- 29-- --------------------------------------------------------------------- 30 31package c01s03b01x00p12n01i00867pkg is 32 constant low_number : integer := 0; 33 constant hi_number : integer := 3; 34 subtype hi_to_low_range is integer range low_number to hi_number; 35 type boolean_vector is array (natural range <>) of boolean; 36 type severity_level_vector is array (natural range <>) of severity_level; 37 type integer_vector is array (natural range <>) of integer; 38 type real_vector is array (natural range <>) of real; 39 type time_vector is array (natural range <>) of time; 40 type natural_vector is array (natural range <>) of natural; 41 type positive_vector is array (natural range <>) of positive; 42 type record_std_package is record 43 a: boolean; 44 b: bit; 45 c:character; 46 d:severity_level; 47 e:integer; 48 f:real; 49 g:time; 50 h:natural; 51 i:positive; 52 end record; 53 type array_rec_std is array (natural range <>) of record_std_package; 54 type four_value is ('Z','0','1','X'); 55--enumerated type 56 constant C1 : boolean := true; 57 constant C2 : bit := '1'; 58 constant C3 : character := 's'; 59 constant C4 : severity_level := note; 60 constant C5 : integer := 3; 61 constant C6 : real := 3.0; 62 constant C7 : time := 3 ns; 63 constant C8 : natural := 1; 64 constant C9 : positive := 1; 65 subtype dumy is integer range 0 to 3; 66 signal Sin1 : bit_vector(0 to 5) ; 67 signal Sin2 : boolean_vector(0 to 5) ; 68 signal Sin4 : severity_level_vector(0 to 5) ; 69 signal Sin5 : integer_vector(0 to 5) ; 70 signal Sin6 : real_vector(0 to 5) ; 71 signal Sin7 : time_vector(0 to 5) ; 72 signal Sin8 : natural_vector(0 to 5) ; 73 signal Sin9 : positive_vector(0 to 5) ; 74 signal Sin10: array_rec_std(0 to 5) ; 75end c01s03b01x00p12n01i00867pkg; 76 77use work.c01s03b01x00p12n01i00867pkg.all; 78entity test is 79 port( 80 sigin1 : in boolean ; 81 sigout1 : out boolean ; 82 sigin2 : in bit ; 83 sigout2 : out bit ; 84 sigin4 : in severity_level ; 85 sigout4 : out severity_level ; 86 sigin5 : in integer ; 87 sigout5 : out integer ; 88 sigin6 : in real ; 89 sigout6 : out real ; 90 sigin7 : in time ; 91 sigout7 : out time ; 92 sigin8 : in natural ; 93 sigout8 : out natural ; 94 sigin9 : in positive ; 95 sigout9 : out positive ; 96 sigin10 : in record_std_package ; 97 sigout10 : out record_std_package 98 ); 99end; 100 101architecture test of test is 102begin 103 sigout1 <= sigin1; 104 sigout2 <= sigin2; 105 sigout4 <= sigin4; 106 sigout5 <= sigin5; 107 sigout6 <= sigin6; 108 sigout7 <= sigin7; 109 sigout8 <= sigin8; 110 sigout9 <= sigin9; 111 sigout10 <= sigin10; 112end; 113 114configuration testbench of test is 115 for test 116 end for; 117end; 118 119use work.c01s03b01x00p12n01i00867pkg.all; 120ENTITY c01s03b01x00p12n01i00867ent IS 121 generic( 122 zero : integer := 0; 123 one : integer := 1; 124 two : integer := 2; 125 three: integer := 3; 126 four : integer := 4; 127 five : integer := 5; 128 six : integer := 6; 129 seven: integer := 7; 130 eight: integer := 8; 131 nine : integer := 9; 132 fifteen:integer:= 15; 133 dumb : bit_vector(0 to 3) := "1010"); 134END c01s03b01x00p12n01i00867ent; 135 136ARCHITECTURE c01s03b01x00p12n01i00867arch OF c01s03b01x00p12n01i00867ent IS 137 component test 138 port( 139 sigin1 : in boolean ; 140 sigout1 : out boolean ; 141 sigin2 : in bit ; 142 sigout2 : out bit ; 143 sigin4 : in severity_level ; 144 sigout4 : out severity_level ; 145 sigin5 : in integer ; 146 sigout5 : out integer ; 147 sigin6 : in real ; 148 sigout6 : out real ; 149 sigin7 : in time ; 150 sigout7 : out time ; 151 sigin8 : in natural ; 152 sigout8 : out natural ; 153 sigin9 : in positive ; 154 sigout9 : out positive ; 155 sigin10 : in record_std_package ; 156 sigout10 : out record_std_package 157 ); 158 end component; 159begin 160 Sin1(zero) <='1'; 161 Sin2(zero) <= true; 162 Sin4(zero) <= note; 163 Sin5(zero) <= 3; 164 Sin6(zero) <= 3.0; 165 Sin7(zero) <= 3 ns; 166 Sin8(zero) <= 1; 167 Sin9(zero) <= 1; 168 Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9); 169 K:block 170 component test 171 port( 172 sigin1 : in boolean ; 173 sigout1 : out boolean ; 174 sigin2 : in bit ; 175 sigout2 : out bit ; 176 sigin4 : in severity_level ; 177 sigout4 : out severity_level ; 178 sigin5 : in integer ; 179 sigout5 : out integer ; 180 sigin6 : in real ; 181 sigout6 : out real ; 182 sigin7 : in time ; 183 sigout7 : out time ; 184 sigin8 : in natural ; 185 sigout8 : out natural ; 186 sigin9 : in positive ; 187 sigout9 : out positive ; 188 sigin10 : in record_std_package ; 189 sigout10 : out record_std_package 190 ); 191 end component; 192 193 BEGIN 194 T5 : test 195 port map 196 ( 197 Sin2(4),Sin2(5), 198 Sin1(4),Sin1(5), 199 Sin4(4),Sin4(5), 200 Sin5(4),Sin5(5), 201 Sin6(4),Sin6(5), 202 Sin7(4),Sin7(5), 203 Sin8(4),Sin8(5), 204 Sin9(4),Sin9(5), 205 Sin10(4),Sin10(5) 206 ); 207 G: for i in zero to three generate 208 T1:test 209 port map 210 ( 211 Sin2(i),Sin2(i+1), 212 Sin1(i),Sin1(i+1), 213 Sin4(i),Sin4(i+1), 214 Sin5(i),Sin5(i+1), 215 Sin6(i),Sin6(i+1), 216 Sin7(i),Sin7(i+1), 217 Sin8(i),Sin8(i+1), 218 Sin9(i),Sin9(i+1), 219 Sin10(i),Sin10(i+1) 220 ); 221 end generate; 222 end block; 223 TESTING: PROCESS 224 BEGIN 225 wait for 1 ns; 226 assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure; 227 assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure; 228 assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure; 229 assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure; 230 assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure; 231 assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure; 232 assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure; 233 assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure; 234 assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure; 235 assert NOT( Sin1(0) = sin1(5) and 236 Sin2(0) = Sin2(5) and 237 Sin4(0) = Sin4(5) and 238 Sin5(0) = Sin5(5) and 239 Sin6(0) = Sin6(5) and 240 Sin7(0) = Sin7(5) and 241 Sin8(0) = Sin8(5) and 242 Sin9(0) = Sin9(5) and 243 Sin10(0)= Sin10(0) ) 244 report "***PASSED TEST: c01s03b01x00p12n01i00867" 245 severity NOTE; 246 assert ( Sin1(0) = sin1(5) and 247 Sin2(0) = Sin2(5) and 248 Sin4(0) = Sin4(5) and 249 Sin5(0) = Sin5(5) and 250 Sin6(0) = Sin6(5) and 251 Sin7(0) = Sin7(5) and 252 Sin8(0) = Sin8(5) and 253 Sin9(0) = Sin9(5) and 254 Sin10(0)= Sin10(0) ) 255 report "***FAILED TEST: c01s03b01x00p12n01i00867 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index." 256 severity ERROR; 257 wait; 258 END PROCESS TESTING; 259 260END c01s03b01x00p12n01i00867arch; 261 262configuration c01s03b01x00p12n01i00867cfg of c01s03b01x00p12n01i00867ent is 263 for c01s03b01x00p12n01i00867arch 264 for K 265 for T5:test use configuration work.testbench; 266 end for; 267 for G(one) 268 for T1:test 269 use configuration work.testbench; 270 end for; 271 end for; 272 for G(dumy'low) 273 for T1:test 274 use configuration work.testbench; 275 end for; 276 end for; 277 for G(2 to dumy'high) 278 for T1:test 279 use configuration work.testbench; 280 end for; 281 end for; 282 end for; 283 end for; 284end; 285