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26
27-- ---------------------------------------------------------------------
28--
29-- $Id: bjt_npn_gen.ams,v 1.1 2002-03-27 22:11:16 paw Exp $
30-- $Revision: 1.1 $
31--
32-- ---------------------------------------------------------------------
33
34--------------------------------------------------------------------
35--  Ebers-moll Model for a transistor                             --
36--  VHDL-AMS Implementation                                       --
37--  Developed at the Distributed Processing Lab at the University --
38--  of Cincinnati                                                 --
39--  by VishwaShanth Kasula on May 10, 1999                        --
40--------------------------------------------------------------------
41--  Circuit Topology                                              --
42--  BJT Ebers-Moll static model
43--  Testbench Ckt to evaluate the DC operatioing point of an npn BJT,
44--  Sedra smith page no. 152, fig 4.9
45--------------------------------------------------------------------
46-- Three regions are simulated
47-- Active region, vbb = 4.0 V
48-- Saturation region, vbb = 6.0 V
49-- Cutoff region, vbb = 0.0;
50
51PACKAGE electricalSystem IS
52    NATURE electrical IS real ACROSS real THROUGH ground reference;
53    FUNCTION SIN(X : real) RETURN real;
54    FUNCTION EXP(X : real) RETURN real;
55END PACKAGE electricalSystem;
56
57
58use work.electricalsystem.all;
59
60entity bjt_npn is
61  generic(isat : real := 1.0e-16;         -- Saturation Current
62          bf : real := 100.0;           -- Ideal maximus forward current
63          br : real := 1.0;             -- ideal maximum reverse current
64          rb : real := 1.0e-5;          -- Base resistance
65          rc : real := 1.0e-5;          -- collector resistance
66          re : real := 1.0e-5;          -- emmiter resistance
67          vaf : real := 100.0);         -- Forward Early Voltage
68  port(terminal e,b,c : electrical);
69end bjt_npn;
70
71architecture structure of bjt_npn is
72  terminal b1, c1, e1 : electrical;
73  quantity vbo across ib through b to b1;
74  quantity vco across ic through c to c1;
75  quantity veo across ie through e to e1;
76  quantity vct across Ict through c1 to e1;--current source
77  quantity vbe across ibe through b1 to e1;
78  quantity vbc across ibc through b1 to c1;
79  quantity vce : real := 1.0;           -- used to calculate VCE
80  constant gmin : real := 1.0e-12;      -- condutsnce in parallel with every pn junction
81  constant vt : real := 0.02589; -- thermal voltage
82
83begin
84  brk : break vbe => 1.0, vbc => -1.0;
85
86  diodecond1 : if(vbe > -5.0*vt) use
87    diodebef : ibe == ((isat*(exp(vbe/vt) - 1.0)) + (gmin*vbe))/bf;
88  elsif(vbe <= -5.0*vt ) use
89    diodeber: ibe == ((-1.0*isat) + (gmin*vbe))/bf;
90  end use;
91  diodecond2 : if(vbc > -5.0*vt) use
92    diodebcf : ibc == ((isat*(exp(vbc/vt) - 1.0)) + (gmin*vbc))/br;
93  elsif(vbc <= -5.0*vt) use
94    diodebcr : ibc == ((-1.0*isat) + (gmin*vbc))/br;
95  end use;
96  bres : vbo == ib * 1.0e-6;
97  cres : vco == ic * 1.0e-6;
98  eres : veo == ie * 1.0e-6;
99  kcl_eqn : ie == -1.0*(ib + ic);
100  vcevolt : vce == vbe - vbc;
101  ictdep : Ict == ((Ibe*bf) - (Ibc*br)) * (1.0 -(vbc/vaf));
102
103end architecture structure;
104
105
106--*****************************************************
107--TEST BENCH
108use std.textio.all;
109use work.electricalsystem.all;
110
111entity bjt_testbench is
112end bjt_testbench;
113
114architecture structure of bjt_testbench is
115  terminal t1, t2, t3, t4 : electrical ;
116  component bjt_npn_comp
117    generic(isat : real := 1.0e-16;         -- Saturation Current
118            bf : real := 100.0;           -- Ideal maximus forward current
119            br : real := 1.0;             -- ideal maximum reverse current
120            rb : real := 1.0e-5;          -- Base resistance
121            rc : real := 1.0e-5;          -- collector resistance
122            re : real := 1.0e-5;          -- emmiter resistance
123            vaf : real := 100.0);         -- Forward Early Voltage
124    port(terminal e,b,c : electrical);
125  end component;
126  for all : bjt_npn_comp use entity work.bjt_npn(structure);
127
128  quantity vcc across icc through t1 to electrical'reference;
129  quantity vrc across irc through t1 to t2;
130  quantity vbb across ibb through t3 to electrical'reference;
131  quantity vre across ire through t4 to electrical'reference;
132
133begin
134
135   bjt : bjt_npn_comp
136     generic map (isat => 1.8104e-15, vaf => 100.0)
137     port map(t4,t3,t2);
138   emres : vre == ire * 3.3e3;
139   ccurr : vcc == 10.0;
140   ecurr : vbb == 6.0;
141   cores : vrc == irc * 4.7e3;
142
143end architecture structure;
144