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27-- ---------------------------------------------------------------------
28--
29-- $Id: bjt_pnp_gen.ams,v 1.1 2002-03-27 22:11:16 paw Exp $
30-- $Revision: 1.1 $
31--
32-- ---------------------------------------------------------------------
33
34-----------------------------------------------------------------------------
35--  Ebers-moll Model for a transistor                             --
36--  VHDL-AMS Implementation                                       --
37--  Developed at the Distributed Processing Lab at the University --
38--  of Cincinnati                                                 --
39--  by VishwaShanth Kasula on May 10, 1999                        --
40--------------------------------------------------------------------
41--  Circuit Topology                                              --
42--  BJT Ebers-Moll static model
43--  Testbench Ckt to evaluate the DC operatioing point of an pnp BJT,
44--  Sedra smith page no. 155, fig 4.11
45--------------------------------------------------------------------
46
47PACKAGE electricalSystem IS
48    NATURE electrical IS real ACROSS real THROUGH ground reference;
49    FUNCTION SIN(X : real) RETURN real;
50    FUNCTION EXP(X : real) RETURN real;
51END PACKAGE electricalSystem;
52
53
54use work.electricalsystem.all;
55
56entity bjt_pnp is
57  generic(isat : real := 1.0e-16;         -- Saturation Current
58          bf : real := 100.0;           -- Ideal maximus forward current
59          br : real := 1.0;             -- ideal maximum reverse current
60          rb : real := 1.0e-5;          -- Base resistance
61          rc : real := 1.0e-5;          -- collector resistance
62          re : real := 1.0e-5;          -- emmiter resistance
63          vaf : real := 100.0);         -- Forward Early Voltage
64  port(terminal e,b,c : electrical);
65end bjt_pnp;
66
67architecture structure of bjt_pnp is
68  terminal b1, c1, e1 : electrical;
69  quantity vbo across ib through b1 to b;
70  quantity vco across ic through c1 to c;
71  quantity veo across ie through e1 to e;
72  quantity vct across Ict through e1 to c1;--current source
73  quantity vbe across ibe through e1 to b1;
74  quantity vbc across ibc through c1 to b1;
75  quantity vce : real := 1.0;           -- used to calculate VCE
76  constant gmin : real := 1.0e-12;      -- condutsnce in parallel with every pn junction
77  constant vt : real := 0.02589; -- thermal voltage
78
79begin
80  brk : break vbe => 1.0, vbc => -1.0;
81
82  diodecond1 : if(vbe > -5.0*vt) use
83    diodebef : ibe == ((isat*(exp(vbe/vt) - 1.0)) + (gmin*vbe))/bf;
84  elsif(vbe <= -5.0*vt ) use
85    diodeber: ibe == ((-1.0*isat) + (gmin*vbe))/bf;
86  end use;
87  diodecond2 : if(vbc > -5.0*vt) use
88    diodebcf : ibc == ((isat*(exp(vbc/vt) - 1.0)) + (gmin*vbc))/br;
89  elsif(vbc <= -5.0*vt) use
90    diodebcr : ibc == ((-1.0*isat) + (gmin*vbc))/br;
91  end use;
92  bres : vbo == ib * 1.0e-6;
93  cres : vco == ic * 1.0e-6;
94  eres : veo == ie * 1.0e-6;
95  kcl_eqn : ie == -1.0*(ib + ic);
96  vcevolt : vce == vbe - vbc;
97  ictdep : Ict == ((Ibe*bf) - (Ibc*br)) * (1.0 -(vbc/vaf));
98
99end architecture structure;
100
101
102--*****************************************************
103--TEST BENCH
104use std.textio.all;
105use work.electricalsystem.all;
106
107entity bjt_testbench is
108end bjt_testbench;
109
110architecture structure of bjt_testbench is
111  terminal t1, t2, t3, t4 : electrical ;
112  component bjt_pnp_comp
113    generic(isat : real := 1.0e-16;         -- Saturation Current
114            bf : real := 100.0;           -- Ideal maximus forward current
115            br : real := 1.0;             -- ideal maximum reverse current
116            rb : real := 1.0e-5;          -- Base resistance
117            rc : real := 1.0e-5;          -- collector resistance
118            re : real := 1.0e-5;          -- emmiter resistance
119            vaf : real := 100.0);         -- Forward Early Voltage
120    port(terminal e,b,c : electrical);
121  end component;
122  for all : bjt_pnp_comp use entity work.bjt_pnp(structure);
123
124  quantity vcc across icc through t4 to electrical'reference;
125  quantity vrc across irc through t3 to t4;
126  quantity vee across iee through t1 to electrical'reference;
127  quantity vre across ire through t1 to t2;
128
129begin
130
131   bjt : bjt_pnp_comp
132     generic map (isat => 1.8104e-15)
133     port map(t2,ground,t3);
134   emres : vre == ire * 2.0e3;
135   ccurr : vcc == -10.0;
136   ecurr : vee == 10.0;
137   cores : vrc == irc * 1.0e3;
138
139end architecture structure;
140