1 2-- Copyright (C) 2000-2002 The University of Cincinnati. 3-- All rights reserved. 4 5-- This file is part of VESTs (Vhdl tESTs). 6 7-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE 8-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE 9-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, 10-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY 11-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR 12-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. 13 14-- By using or copying this Software, Licensee agrees to abide by the 15-- intellectual property laws, and all other applicable laws of the U.S., 16-- and the terms of this license. 17 18-- You may modify, distribute, and use the software contained in this 19-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, 20-- June 1991. A copy of this license agreement can be found in the file 21-- "COPYING", distributed with this archive. 22 23-- You should have received a copy of the GNU General Public License 24-- along with VESTs; if not, write to the Free Software Foundation, 25-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 26 27-- --------------------------------------------------------------------- 28-- 29-- $Id: static_pjfet.ams,v 1.1 2002-03-27 22:11:16 paw Exp $ 30-- $Revision: 1.1 $ 31-- 32-- --------------------------------------------------------------------- 33 34-- This ckt is used to find the output and transfer characteristics of an 35-- p-channel JFET model. 36-- The model is Spice2 model, taken from the SPICE book, pg 142, fig 3.7 37------------------------------------------------------------------------ 38-- The ckt used here is from sedra and smith's page no. 216, fig 5.20 39------------------------------------------------------------------------ 40 41PACKAGE electricalSystem IS 42 NATURE electrical IS real ACROSS real THROUGH ground reference; 43 FUNCTION POW(X,Y: real) RETURN real; 44 FUNCTION SIN(X : real) RETURN real; 45 FUNCTION EXP(X : real) RETURN real; 46 FUNCTION SQRT(X : real) RETURN real; 47END PACKAGE electricalSystem; 48 49 50----------------------------------------------------------------------- 51-- G D1 rd D 52-- o-----|>|--o-------/\/\---------o 53-- | | 54-- - Id ( ) 55-- V | 56-- - | 57-- S1 o----------o 58-- | 59-- > 60-- < rs 61-- | 62-- 0 S 63----------------------------------------------------------------------- 64 65----- P-JFET 66--use std.textio.all; 67use work.electricalsystem.all; 68 69entity pjfet is 70 generic(T : real := 300.0; 71 vto : real := -2.0; -- Zero-bais threshold voltage 72 beta : real := 1.0e-4; -- transconductance parameter 73 lambda : real := 0.0; -- channel lenght modulation 74 af : real := 1.0; -- flicker noise exponent 75 kf : real := 0.0; -- flicker noise coefficient 76 iss : real := 1.0e-14; -- gate junction saturation current 77 pb : real := 1.0; -- gate junction potential 78 fc : real := 0.5; -- forward-bais depletion capacitance coeff 79 cgd : real := 4.0e-11; -- zero-bais gate-drain junction cap 80 cgs : real := 4.0e-11; -- zero-bias gate-source junction cap 81 rd : real := 1.0e-6; -- drain ohmic resistance 82 rs : real := 1.0e-6); -- source ohmic resistance 83 port (terminal g,s,d : electrical); 84end entity pjfet; 85 86architecture behav of pjfet is 87 terminal d1, s1 : electrical; 88 quantity vds across id through s1 to d1; 89 quantity vrd across ird through d1 to d; 90 quantity vrs across irs through s to s1; 91 quantity vgs across igs through s1 to g; 92 quantity vgd across igd through d1 to g; 93 constant gmin : real := 1.0e-12; 94 quantity ktq : real := 2.586e-2; -- (kT/q) thermal voltage at T=300K 95 --constant k : real := 1.38e-23; -- J/K ..... boltzman constant 96 -- T = 300 K ............ Absolute temperature 97 --constant q : real := 1.60e-19; -- C ....... magnitude of electron charge 98 quantity vds_free : real := 2.0; 99 quantity vgs_free : real := 0.0; 100 quantity vgd_free : real := 2.0; 101 102begin 103 ------ Setting initial conditions 104 initreg : break vgs => 0.0, vds => 2.0, vgd => 2.0; 105 therm_volt : ktq == 2.586e-2 * (T/300.0); 106 dres : vrd == ird * rd; 107 oup_res : vds_free == vds; 108 inp_res : vgs_free == vgs; 109 vgdf : vgd_free == vgd; 110 sres : vrs == irs * rs; 111 112---- Current is in Amps. 113-- Normal mode 114 ------ Cut off Region 115 regions : if((vgs <= vto) and (vds >= 0.0))use 116 gncn : id == 1.0e-9 * vds; 117 ------ Linear Region 118 elsif((vds < (vgs-vto)) and (vgs > vto) and (vds >= 0.0)) use 119 gnln : id == vds*beta*((2.0*(vgs_free-vto)) - vds_free)*(1.0 + lambda*vds_free); 120 ------ Saturation Region 121 elsif((vds >= vgs-vto) and (vgs > vto) and (vds >= 0.0)) use 122 gnsn : id == beta*(pow((vgs_free-vto),2.0))*(1.0 + lambda*vds_free); 123 124-- Inversted mode 125 ------ Cut off Region 126 elsif((vgd <= vto) and (vds < 0.0))use 127 gnci : id == 1.0e-9 * vds; 128 ------ Linear Region 129 elsif(((-1.0*vds) < (vgd-vto)) and (vgd > vto) and (vds < 0.0)) use 130 gnli : id == vds*beta*((2.0*(vgd_free-vto)) + vds_free)*(1.0 - lambda*vds_free); 131 ------ Saturation Region 132 elsif(((-1.0*vds) >= vgd-vto) and (vgd > vto) and (vds < 0.0)) use 133 gnsi : id == -1.0*(beta)*(pow((vgd_free-vto),2.0))*(1.0 - lambda*vds_free); 134 end use; 135 136----- Gate diode equations 137 initsub : break vgd => 0.0, vgs => 0.0, igs => 0.0, igd => 0.0; 138 139 ----- Gate to source 140 subcond1 : if(vgs > -5.0*ktq) use 141 gsf : igs == ((iss*(exp(vgs/ktq) - 1.0)) + (gmin*vgs)); 142 elsif(vgs <= -5.0*ktq ) use 143 gsr : igs == -1.0*iss + (gmin*vgs); 144 end use; 145 ----- Gate to drain 146 subcond2 : if(vgd > -5.0*ktq) use 147 gdf : igd == ((iss*(exp(vgd/ktq) - 1.0)) + (gmin*vgd)); 148 elsif(vgd <= -5.0*ktq ) use 149 gdr : igd == -1.0*iss + (gmin*vgd); 150 end use; 151 152end architecture behav; --- of pjfet; 153 154---- DC Voltage source 155 156use work.electricalsystem.all; 157 158entity DCVSrc is 159 generic (v : real := 10.0); -- voltage 160 port (terminal pos, neg : electrical); 161end entity DCVSrc; 162 163architecture behav of DCVSrc is 164 terminal temp : electrical; 165 quantity vdc across idc through temp to neg; 166 quantity vtemp across itemp through pos to temp; 167 168begin 169 170 VSrc : vdc == v; 171 temp_volt : vtemp == itemp * 1.0e-03; 172 173end architecture behav; --- of DCVSrc 174 175 176------ pjfet amplifier circuit 177 178use std.textio.all; 179use work.electricalsystem.all; 180 181entity pjfet_ckt is 182end entity; 183 184architecture test of pjfet_ckt is 185 terminal t1, t2, t3, t4: electrical; 186-- quantity vin across iin through ain to electrical'reference; 187-- quantity vout across iout through t2 to electrical'reference; 188 quantity vb across ib through t1 to t2; 189-- quantity ibt through t1 to t2; 190 quantity vrd1 across ird1 through t3 to t4; 191 quantity vdd across idd through t1 to electrical'reference; 192 quantity vss across iss through t4 to electrical'reference; 193 194 195 -- signal vds_sig, vgs_sig : real := 0.0; 196 197 component pjfet_comp is 198 generic(T : real := 300.0; 199 vto : real := -2.0; -- Zero-bais threshold voltage 200 beta : real := 1.0e-4; -- transconductance parameter 201 lambda : real := 0.0; -- channel lenght modulation 202 af : real := 1.0; -- flicker noise exponent 203 kf : real := 0.0; -- flicker noise coefficient 204 iss : real := 1.0e-14; -- gate junction saturation current 205 pb : real := 1.0; -- gate junction potential 206 fc : real := 0.5; -- forward-bais depletion capacitance coeff 207 cgd : real := 4.0e-11; -- zero-bais gate-drain junction cap 208 cgs : real := 4.0e-11; -- zero-bias gate-source junction cap 209 rd : real := 1.0e-6; -- drain ohmic resistance 210 rs : real := 1.0e-6); -- source ohmic resistance 211 port (terminal g,s,d : electrical); 212 end component; 213 for all :pjfet_comp use entity work.pjfet(behav); 214 215begin 216 217 jn1 : pjfet_comp 218 generic map(vto => -2.0, beta => 1.0e-3, lambda => 0.04) 219 port map(ground, t2, t3); 220 221-- brk : break on vgs_sig,vds_sig; 222-- inp : vin == vgs_sig; 223-- oup : vout == vds_sig; 224-- oup : vout == iout * 1.0e8; 225-- cap : icout == 1.0e-13 * vcout'dot; 226-- capbrk : break vcout => 0.0; 227 rd1 : vrd1 == ird1 * 2.0e3; 228 src1 : vdd == 5.0; 229 src2 : vss == -5.0; 230 curr : ib == 1.0e-3; 231-- curt : vb == ibt * 1.0e6; 232 233-- inputtestbench:PROCESS 234-- FILE test_IN : text OPEN READ_MODE IS "pjfet_anal.in"; 235-- VARIABLE linebuf : line; 236-- VARIABLE xds, xgs : real := 0.0; 237-- BEGIN 238 239-- WHILE(NOT(endfile(test_IN))) LOOP 240-- readline(test_IN,linebuf); 241-- read(linebuf,xgs); 242-- read(linebuf,xds); 243-- vgs_sig <= xgs; 244-- vds_sig <= xds; 245-- WAIT FOR 1 ns; 246-- END LOOP; 247-- WAIT; 248-- END process; --- inputtestbench 249 250end architecture test; -- pjfet_ckt 251